/* Spill 128 bit SSE registers */
store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
- } else if (get_mode_size_bits(mode) == 8) {
- store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
- res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
} else {
- store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
+ store = get_mode_size_bits(mode) == 8
+ ? new_bd_ia32_Store_8bit(dbgi, block, ptr, noreg, nomem, val)
+ : new_bd_ia32_Store (dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
}
panic("unexpected frame user while collection frame entity nodes");
case iro_ia32_FnstCW:
- case iro_ia32_Store8Bit:
case iro_ia32_Store:
case iro_ia32_fst:
case iro_ia32_fist:
be_set_emitter(op_ia32_ShrMem, bemit_shrmem);
be_set_emitter(op_ia32_Stc, bemit_stc);
be_set_emitter(op_ia32_Store, bemit_store);
- be_set_emitter(op_ia32_Store8Bit, bemit_store);
be_set_emitter(op_ia32_Sub, bemit_sub);
be_set_emitter(op_ia32_SubMem, bemit_submem);
be_set_emitter(op_ia32_SubSP, bemit_subsp);
ir_mode *conv_mode;
ir_mode *store_mode;
- if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
+ if (!is_ia32_Store(node))
return;
- assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
pred_proj = get_irn_n(node, n_ia32_Store_val);
if (is_Proj(pred_proj)) {
pred = get_Proj_pred(pred_proj);
Store => {
op_flags => [ "uses_memory", "fragile" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp" ],
- out => [ "none", "none", "none" ] },
- ins => [ "base", "index", "mem", "val" ],
- outs => [ "M", "X_regular", "X_except" ],
- emit => 'mov%M %#S3, %AM',
- latency => 2,
-},
-
-Store8Bit => {
- op_flags => [ "uses_memory", "fragile" ],
- state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ],
- out => ["none", "none", "none" ] },
+ constructors => {
+ "" => {
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "none", "none", "none" ] }
+ },
+ "8bit" => {
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ],
+ out => [ "none", "none", "none" ] }
+ }
+ },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_regular", "X_except" ],
emit => 'mov%M %#S3, %AM',
new_val = create_immediate_or_transform(val);
assert(mode != mode_b);
- if (dest_bits == 8) {
- new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- } else {
- new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- }
+ new_node = dest_bits == 8
+ ? new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, new_val)
+ : new_bd_ia32_Store (dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
}
ir_set_throws_exception(new_node, throws_exception);
dbg_info *dbgi = get_irn_dbg_info(node);
long pn = get_Proj_proj(node);
- if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
+ if (is_ia32_Store(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
ir_graph *const irg = get_Block_irg(new_block);
/* mov ecx, <env> */
val = ia32_create_Immediate(irg, NULL, 0, 0xB9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
/* jmp rel <callee> */
val = ia32_create_Immediate(irg, NULL, 0, 0xE9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);