use vfp mnemonics rather than hard-coded opcodes in arm setjmp/longjmp

the code to save/restore vfp registers needs to build even when the
configured target does not have fpu; this is because code using vfp
fpu (but with the standard soft-float EABI) may call a libc built for
a soft-float only, and the EABI considers these registers call-saved
when they exist. thus, extra directives are used to force the
assembler to allow vfp instructions and to avoid marking the resulting
object files as requiring vfp.

moving away from using hard-coded opcode words is necessary in order
to eventually support producing thumb2-only output for cortex-m.

conditional execution of these instructions based on hwcap flags was
already implemented. when building for arm (non-thumb) output, the
only currently-supported configuration, this commit does not change
the code emitted.

diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s
index c3d15ae..82bce83 100644 (file)
--- a/src/setjmp/arm/longjmp.s
+++ b/src/setjmp/arm/longjmp.s
@@ -20,7 +20,11 @@ longjmp:
        ldc p2, cr4, [ip], #48
 2:     tst r1,#0x40
        beq 2f
-       .word 0xecbc8b10 /* vldmia ip!, {d8-d15} */
+       .fpu vfp
+       vldmia ip!, {d8-d15}
+       .fpu softvfp
+       .eabi_attribute 10, 0
+       .eabi_attribute 27, 0
 2:     tst r1,#0x200
        beq 3f
        ldcl p1, cr10, [ip], #8

diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s
index 19f8abc..32db7d8 100644 (file)
--- a/src/setjmp/arm/setjmp.s
+++ b/src/setjmp/arm/setjmp.s
@@ -22,7 +22,11 @@ setjmp:
        stc p2, cr4, [ip], #48
 2:     tst r1,#0x40
        beq 2f
-       .word 0xecac8b10 /* vstmia ip!, {d8-d15} */
+       .fpu vfp
+       vstmia ip!, {d8-d15}
+       .fpu softvfp
+       .eabi_attribute 10, 0
+       .eabi_attribute 27, 0
 2:     tst r1,#0x200
        beq 3f
        stcl p1, cr10, [ip], #8