-#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
+#include "libc.h"
-#define a_barrier a_barrier
-static inline void a_barrier()
-{
- __asm__ __volatile__("dmb ish");
-}
+#if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
+#define BLX "mov lr,pc\n\tbx"
+#else
+#define BLX "blx"
+#endif
-#define a_cas a_cas
-static inline int a_cas(volatile int *p, int t, int s)
-{
- int old;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%3\n"
- " cmp %0,%1\n"
- " bne 1f\n"
- " strex %0,%2,%3\n"
- " cmp %0, #0\n"
- " bne 1b\n"
- " mov %0, %1\n"
- "1: dmb ish\n"
- : "=&r"(old)
- : "r"(t), "r"(s), "Q"(*p)
- : "memory", "cc" );
- return old;
-}
+extern hidden uintptr_t __a_cas_ptr, __a_barrier_ptr;
-#define a_swap a_swap
-static inline int a_swap(volatile int *x, int v)
-{
- int old, tmp;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%3\n"
- " strex %1,%2,%3\n"
- " cmp %1, #0\n"
- " bne 1b\n"
- " dmb ish\n"
- : "=&r"(old), "=&r"(tmp)
- : "r"(v), "Q"(*x)
- : "memory", "cc" );
- return old;
-}
+#if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
+ || __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
-#define a_fetch_add a_fetch_add
-static inline int a_fetch_add(volatile int *x, int v)
+#define a_ll a_ll
+static inline int a_ll(volatile int *p)
{
- int old, tmp;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%3\n"
- " add %0,%0,%2\n"
- " strex %1,%0,%3\n"
- " cmp %1, #0\n"
- " bne 1b\n"
- " dmb ish\n"
- : "=&r"(old), "=&r"(tmp)
- : "r"(v), "Q"(*x)
- : "memory", "cc" );
- return old-v;
+ int v;
+ __asm__ __volatile__ ("ldrex %0, %1" : "=r"(v) : "Q"(*p));
+ return v;
}
-#define a_inc a_inc
-static inline void a_inc(volatile int *x)
+#define a_sc a_sc
+static inline int a_sc(volatile int *p, int v)
{
- int tmp, tmp2;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%2\n"
- " add %0,%0,#1\n"
- " strex %1,%0,%2\n"
- " cmp %1, #0\n"
- " bne 1b\n"
- " dmb ish\n"
- : "=&r"(tmp), "=&r"(tmp2)
- : "Q"(*x)
- : "memory", "cc" );
+ int r;
+ __asm__ __volatile__ ("strex %0,%2,%1" : "=&r"(r), "=Q"(*p) : "r"(v) : "memory");
+ return !r;
}
-#define a_dec a_dec
-static inline void a_dec(volatile int *x)
+#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
+
+#define a_barrier a_barrier
+static inline void a_barrier()
{
- int tmp, tmp2;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%2\n"
- " sub %0,%0,#1\n"
- " strex %1,%0,%2\n"
- " cmp %1, #0\n"
- " bne 1b\n"
- " dmb ish\n"
- : "=&r"(tmp), "=&r"(tmp2)
- : "Q"(*x)
- : "memory", "cc" );
+ __asm__ __volatile__ ("dmb ish" : : : "memory");
}
-#define a_and a_and
-static inline void a_and(volatile int *x, int v)
+#endif
+
+#define a_pre_llsc a_barrier
+#define a_post_llsc a_barrier
+
+#else
+
+#define a_cas a_cas
+static inline int a_cas(volatile int *p, int t, int s)
{
- int tmp, tmp2;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%3\n"
- " and %0,%0,%2\n"
- " strex %1,%0,%3\n"
- " cmp %1, #0\n"
- " bne 1b\n"
- " dmb ish\n"
- : "=&r"(tmp), "=&r"(tmp2)
- : "r"(v), "Q"(*x)
- : "memory", "cc" );
+ for (;;) {
+ register int r0 __asm__("r0") = t;
+ register int r1 __asm__("r1") = s;
+ register volatile int *r2 __asm__("r2") = p;
+ register uintptr_t r3 __asm__("r3") = __a_cas_ptr;
+ int old;
+ __asm__ __volatile__ (
+ BLX " r3"
+ : "+r"(r0), "+r"(r3) : "r"(r1), "r"(r2)
+ : "memory", "lr", "ip", "cc" );
+ if (!r0) return t;
+ if ((old=*p)!=t) return old;
+ }
}
-#define a_or a_or
-static inline void a_or(volatile int *x, int v)
+#endif
+
+#ifndef a_barrier
+#define a_barrier a_barrier
+static inline void a_barrier()
{
- int tmp, tmp2;
- __asm__ __volatile__(
- " dmb ish\n"
- "1: ldrex %0,%3\n"
- " orr %0,%0,%2\n"
- " strex %1,%0,%3\n"
- " cmp %1, #0\n"
- " bne 1b\n"
- " dmb ish\n"
- : "=&r"(tmp), "=&r"(tmp2)
- : "r"(v), "Q"(*x)
- : "memory", "cc" );
+ register uintptr_t ip __asm__("ip") = __a_barrier_ptr;
+ __asm__ __volatile__( BLX " ip" : "+r"(ip) : : "memory", "cc", "lr" );
}
+#endif
-#define a_store a_store
-static inline void a_store(volatile int *p, int x)
+#define a_crash a_crash
+static inline void a_crash()
{
__asm__ __volatile__(
- " dmb ish\n"
- " str %1,%0\n"
- " dmb ish\n"
- : "=m"(*p)
- : "r"(x)
- : "memory", "cc" );
-}
-
+#ifndef __thumb__
+ ".word 0xe7f000f0"
#else
+ ".short 0xdeff"
+#endif
+ : : : "memory");
+}
-int __a_cas(int, int, volatile int *) __attribute__((__visibility__("hidden")));
-#define __k_cas __a_cas
+#if __ARM_ARCH >= 5 && (!__thumb__ || __thumb2__)
-#define a_barrier a_barrier
-static inline void a_barrier()
+#define a_clz_32 a_clz_32
+static inline int a_clz_32(uint32_t x)
{
- __asm__ __volatile__("bl __a_barrier"
- : : : "memory", "cc", "ip", "lr" );
+ __asm__ ("clz %0, %1" : "=r"(x) : "r"(x));
+ return x;
}
-#define a_cas a_cas
-static inline int a_cas(volatile int *p, int t, int s)
+#if __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
+
+#define a_ctz_32 a_ctz_32
+static inline int a_ctz_32(uint32_t x)
{
- int old;
- for (;;) {
- if (!__k_cas(t, s, p))
- return t;
- if ((old=*p) != t)
- return old;
- }
+ uint32_t xr;
+ __asm__ ("rbit %0, %1" : "=r"(xr) : "r"(x));
+ return a_clz_32(xr);
}
#endif
+
+#endif
projects / musl / blobdiff