4 * Copyright (C) 2008 The Android Open Source Project
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17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 * Optimized memcpy() for ARM.
35 * note that memcpy() always returns the destination pointer,
36 * so we have to preserve R0.
40 * This file has been modified from the original for use in musl libc.
41 * The main changes are: addition of .type memcpy,%function to make the
42 * code safely callable from thumb mode, adjusting the return
43 * instructions to be compatible with pre-thumb ARM cpus, removal of
44 * prefetch code that is not compatible with older cpus and support for
45 * building as thumb 2.
51 .type memcpy,%function
53 /* The stack must always be 64-bits aligned to be compliant with the
54 * ARM ABI. Since we have to save R0, we might as well save R4
55 * which we can use for better pipelining of the reads below
59 stmfd sp!, {r0, r4, lr}
60 /* Making room for r5-r11 which will be spilled later */
64 /* it simplifies things to take care of len<4 early */
66 blo copy_last_3_and_return
68 /* compute the offset to align the source
69 * offset = (4-(src&3))&3 = -src & 3
75 /* align source to 32 bits. We need to insert 2 instructions between
76 * a ldr[b|h] and str[b|h] because byte and half-word instructions
80 sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
90 /* see if src and dst are aligned together (congruent) */
95 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
96 * frame. Don't update sp.
100 /* align the destination to a cache-line */
103 beq congruent_aligned32
107 /* conditionnaly copies 0 to 7 words (length in r3) */
108 movs r12, r3, lsl #28
109 ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
110 ldmmi r1!, {r8, r9} /* 8 bytes */
111 stmcs r0!, {r4, r5, r6, r7}
114 ldrne r10,[r1], #4 /* 4 bytes */
120 * here source is aligned to 32 bytes.
125 blo less_than_32_left
128 * We preload a cache-line up to 64 bytes ahead. On the 926, this will
129 * stall only until the requested world is fetched, but the linefill
130 * continues in the the background.
131 * While the linefill is going, we write our previous cache-line
132 * into the write-buffer (which should have some free space).
133 * When the linefill is done, the writebuffer will
134 * start dumping its content into memory
136 * While all this is going, we then load a full cache line into
137 * 8 registers, this cache line should be in the cache by now
138 * (or partly in the cache).
140 * This code should work well regardless of the source/dest alignment.
144 /* Align the preload register to a cache-line because the cpu does
145 * "critical word first" (the first word requested is loaded first).
150 1: ldmia r1!, { r4-r11 }
154 * NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
155 * for ARM9 preload will not be safely guarded by the preceding subs.
156 * When it is safely guarded the only possibility to have SIGSEGV here
157 * is because the caller overstates the length.
159 @ ldrhi r3, [r12], #32 /* cheap ARM9 preload */
160 stmia r0!, { r4-r11 }
167 * less than 32 bytes left at this point (length in r2)
170 /* skip all this if there is nothing to do, which should
171 * be a common case (if not executed the code below takes
177 /* conditionnaly copies 0 to 31 bytes */
178 movs r12, r2, lsl #28
179 ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
180 ldmmi r1!, {r8, r9} /* 8 bytes */
181 stmcs r0!, {r4, r5, r6, r7}
183 movs r12, r2, lsl #30
184 ldrcs r3, [r1], #4 /* 4 bytes */
185 ldrhmi r4, [r1], #2 /* 2 bytes */
189 ldrbne r3, [r1] /* last byte */
192 /* we're done! restore everything and return */
193 1: ldmfd sp!, {r5-r11}
194 ldmfd sp!, {r0, r4, lr}
197 /********************************************************************/
201 * here source is aligned to 4 bytes
202 * but destination is not.
204 * in the code below r2 is the number of bytes read
205 * (the number of bytes written is always smaller, because we have
206 * partial words in the shift queue)
209 blo copy_last_3_and_return
211 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
212 * frame. Don't update sp.
216 /* compute shifts needed to align src to dest */
218 and r5, r5, #3 /* r5 = # bytes in partial words */
219 mov r12, r5, lsl #3 /* r12 = right */
220 rsb lr, r12, #32 /* lr = left */
222 /* read the first word */
226 /* write a partial word (0 to 3 bytes), such that destination
227 * becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
238 blo partial_word_tail
240 /* Align destination to 32 bytes (cache line boundary) */
251 blo partial_word_tail
253 /* copy 32 bytes at a time */
255 blo less_than_thirtytwo
257 /* Use immediate mode for the shifts, because there is an extra cycle
258 * for register shifts, which could account for up to 50% of
270 ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
273 orr r3, r3, r4, lsl #16
275 orr r4, r4, r5, lsl #16
277 orr r5, r5, r6, lsl #16
279 orr r6, r6, r7, lsl #16
281 orr r7, r7, r8, lsl #16
283 orr r8, r8, r9, lsl #16
285 orr r9, r9, r10, lsl #16
286 mov r10, r10, lsr #16
287 orr r10, r10, r11, lsl #16
288 stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
291 b less_than_thirtytwo
296 ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
299 orr r3, r3, r4, lsl #24
301 orr r4, r4, r5, lsl #24
303 orr r5, r5, r6, lsl #24
305 orr r6, r6, r7, lsl #24
307 orr r7, r7, r8, lsl #24
309 orr r8, r8, r9, lsl #24
311 orr r9, r9, r10, lsl #24
313 orr r10, r10, r11, lsl #24
314 stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
317 b less_than_thirtytwo
322 ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
325 orr r3, r3, r4, lsl #8
327 orr r4, r4, r5, lsl #8
329 orr r5, r5, r6, lsl #8
331 orr r6, r6, r7, lsl #8
333 orr r7, r7, r8, lsl #8
335 orr r8, r8, r9, lsl #8
337 orr r9, r9, r10, lsl #8
338 mov r10, r10, lsr #24
339 orr r10, r10, r11, lsl #8
340 stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
345 /* copy the last 0 to 31 bytes of the source */
346 rsb r12, lr, #32 /* we corrupted r12, recompute it */
349 blo partial_word_tail
361 /* we have a partial word in the input buffer */
362 movs r5, lr, lsl #(31-3)
369 /* Refill spilled registers from the stack. Don't update sp. */
372 copy_last_3_and_return:
373 movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
381 /* we're done! restore sp and spilled registers and return */
383 ldmfd sp!, {r0, r4, lr}