1 #if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
2 #define BLX "mov lr,pc\n\tbx"
7 extern uintptr_t __attribute__((__visibility__("hidden")))
8 __a_cas_ptr, __a_barrier_ptr;
10 #if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
11 || __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
14 static inline int a_ll(volatile int *p)
17 __asm__ __volatile__ ("ldrex %0, %1" : "=r"(v) : "Q"(*p));
22 static inline int a_sc(volatile int *p, int v)
25 __asm__ __volatile__ ("strex %0,%2,%1" : "=&r"(r), "=Q"(*p) : "r"(v) : "memory");
29 #if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
31 #define a_barrier a_barrier
32 static inline void a_barrier()
34 __asm__ __volatile__ ("dmb ish" : : : "memory");
39 #define a_pre_llsc a_barrier
40 #define a_post_llsc a_barrier
45 static inline int a_cas(volatile int *p, int t, int s)
48 register int r0 __asm__("r0") = t;
49 register int r1 __asm__("r1") = s;
50 register volatile int *r2 __asm__("r2") = p;
51 register uintptr_t r3 __asm__("r3") = __a_cas_ptr;
53 __asm__ __volatile__ (
55 : "+r"(r0), "+r"(r3) : "r"(r1), "r"(r2)
56 : "memory", "lr", "ip", "cc" );
58 if ((old=*p)!=t) return old;
65 #define a_barrier a_barrier
66 static inline void a_barrier()
68 register uintptr_t ip __asm__("ip") = __a_barrier_ptr;
69 __asm__ __volatile__( BLX " ip" : "+r"(ip) : : "memory", "cc", "lr" );
73 #define a_crash a_crash
74 static inline void a_crash()
87 #define a_clz_32 a_clz_32
88 static inline int a_clz_32(uint32_t x)
90 __asm__ ("clz %0, %1" : "=r"(x) : "r"(x));
94 #if __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
96 #define a_ctz_32 a_ctz_32
97 static inline int a_ctz_32(uint32_t x)
100 __asm__ ("rbit %0, %1" : "=r"(xr) : "r"(x));