From ede86ffb1270f07437edcc8ea3dd5d46530f93eb Mon Sep 17 00:00:00 2001 From: Michael Beck Date: Tue, 11 Mar 2008 23:35:22 +0000 Subject: [PATCH] refactored immediates: - now stored as long values (should be enough) - floating point values are emitted right [r18088] --- ir/be/arm/arm_emitter.c | 13 ++- ir/be/arm/arm_new_nodes.c | 122 ++++++++++++++++++------- ir/be/arm/arm_new_nodes.h | 20 +++-- ir/be/arm/arm_nodes_attr.h | 41 +++++++-- ir/be/arm/arm_spec.pl | 180 +++++++++++++++++++------------------ ir/be/arm/arm_transform.c | 112 ++++++++++------------- 6 files changed, 286 insertions(+), 202 deletions(-) diff --git a/ir/be/arm/arm_emitter.c b/ir/be/arm/arm_emitter.c index 08485759e..53be01863 100644 --- a/ir/be/arm/arm_emitter.c +++ b/ir/be/arm/arm_emitter.c @@ -222,9 +222,9 @@ void arm_emit_immediate(const ir_node *node) { const arm_attr_t *attr = get_arm_attr_const(node); if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) { - be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_value(node))); + be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node))); } else if (ARM_GET_FPA_IMM(attr)) { - be_emit_irprintf("#0x%F", get_arm_value(node)); + be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node))); } else if (is_arm_SymConst(node)) be_emit_ident(get_arm_symconst_id(node)); else { @@ -240,7 +240,7 @@ void arm_emit_shift(const ir_node *node) { mod = get_arm_shift_modifier(node); if (ARM_HAS_SHIFT(mod)) { - long v = get_tarval_long(get_arm_value(node)); + long v = get_arm_imm_value(node); be_emit_irprintf(", %s #%l", arm_shf_mod_name(mod), v); } @@ -297,7 +297,7 @@ static void emit_arm_fpaConst(const ir_node *irn) { unsigned label; ir_mode *mode; - key.u.tv = get_arm_value(irn); + key.u.tv = get_fpaConst_value(irn); key.is_ident = 0; key.label = 0; entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic)); @@ -478,7 +478,7 @@ static int reg_cmp(const void *a, const void *b) { * Create the CopyB instruction sequence. */ static void emit_arm_CopyB(const ir_node *irn) { - unsigned int size = get_tarval_long(get_arm_value(irn)); + unsigned size = (unsigned)get_arm_imm_value(irn); const char *tgt = arch_register_get_name(get_in_reg(irn, 0)); const char *src = arch_register_get_name(get_in_reg(irn, 1)); @@ -505,7 +505,7 @@ static void emit_arm_CopyB(const ir_node *irn) { be_emit_string(src); be_emit_cstring(")->("); arm_emit_source_register(irn, 0); - be_emit_irprintf(" [%d bytes], Uses ", size); + be_emit_irprintf(" [%u bytes], Uses ", size); be_emit_string(t0); be_emit_cstring(", "); be_emit_string(t1); @@ -1164,7 +1164,6 @@ void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) { ir_node *last_block = NULL; cg = arm_cg; - isa = (const arm_isa_t *)cg->arch_env->isa; arch_env = cg->arch_env; sym_or_tv = new_set(cmp_sym_or_tv, 8); diff --git a/ir/be/arm/arm_new_nodes.c b/ir/be/arm/arm_new_nodes.c index 3f4daf3fe..544e1331e 100644 --- a/ir/be/arm/arm_new_nodes.c +++ b/ir/be/arm/arm_new_nodes.c @@ -55,10 +55,27 @@ * Returns the shift modifier string. */ const char *arm_shf_mod_name(arm_shift_modifier mod) { - static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" }; + static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" }; return names[mod]; } +/** + * Return the fpa immediate from the encoding. + */ +const char *arm_get_fpa_imm_name(long imm_value) { + static const char *fpa_imm[] = { + "0", + "1", + "2", + "3", + "4", + "5", + "10", + "0.5" + }; + return fpa_imm[imm_value]; +} + /*********************************************************************************** * _ _ _ __ * | | (_) | | / _| @@ -167,11 +184,11 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { case dump_node_nodeattr_txt: mod = ARM_GET_SHF_MOD(attr); if (ARM_HAS_SHIFT(mod)) { - fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), get_tarval_long(attr->value)); + fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), attr->imm_value); } else if (mod == ARM_SHF_IMM) { /* immediate */ - fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->value)); + fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->imm_value)); } break; @@ -225,22 +242,17 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } fprintf(F, " (%d)\n", attr->flags); - if (get_arm_value(n)) { - if (is_arm_CopyB(n)) { - fprintf(F, "size = %lu\n", get_tarval_long(get_arm_value(n))); + if (is_arm_CopyB(n)) { + fprintf(F, "size = %lu\n", get_arm_imm_value(n)); + } else { + long v = get_arm_imm_value(n); + if (ARM_GET_FPA_IMM(attr)) { + fprintf(F, "immediate float value = %s\n", arm_get_fpa_imm_name(v)); } else { - if (mode_is_float(get_irn_mode(n))) { - fprintf(F, "float value = (%f)\n", (double) get_tarval_double(get_arm_value(n))); - } else if (mode_is_int(get_irn_mode(n))) { - long v = get_tarval_long(get_arm_value(n)); - fprintf(F, "long value = %ld (0x%08lx)\n", v, v); - } else if (mode_is_reference(get_irn_mode(n))) { - fprintf(F, "pointer\n"); - } else { - assert(0 && "unbehandelter Typ im const-Knoten"); - } + fprintf(F, "immediate value = %ld (0x%08lx)\n", v, v); } } + if (is_arm_CmpBra(n) && get_arm_CondJmp_proj_num(n) >= 0) { fprintf(F, "proj_num = (%d)\n", get_arm_CondJmp_proj_num(n)); } @@ -290,6 +302,20 @@ const arm_SymConst_attr_t *get_arm_SymConst_attr_const(const ir_node *node) { return get_irn_generic_attr_const(node); } +static const arm_fpaConst_attr_t *get_arm_fpaConst_attr_const(const ir_node *node) { + const arm_attr_t *attr = get_arm_attr_const(node); + const arm_fpaConst_attr_t *fpa_attr = CONST_CAST_ARM_ATTR(arm_fpaConst_attr_t, attr); + + return fpa_attr; +} + +static arm_fpaConst_attr_t *get_arm_fpaConst_attr(ir_node *node) { + arm_attr_t *attr = get_arm_attr(node); + arm_fpaConst_attr_t *fpa_attr = CAST_ARM_ATTR(arm_fpaConst_attr_t, attr); + + return fpa_attr; +} + static int is_arm_CondJmp(const ir_node *node) { int code = get_arm_irn_opcode(node); @@ -464,20 +490,37 @@ int get_arm_n_res(const ir_node *node) { const arm_attr_t *attr = get_arm_attr_const(node); return ARR_LEN(attr->slots); } + /** - * Returns the tarvalue + * Returns the immediate value */ -tarval *get_arm_value(const ir_node *node) { +long get_arm_imm_value(const ir_node *node) { const arm_attr_t *attr = get_arm_attr_const(node); - return attr->value; + return attr->imm_value; } /** - * Sets the tarvalue + * Sets the tarval value */ -void set_arm_value(ir_node *node, tarval *tv) { +void set_arm_imm_value(ir_node *node, long imm_value) { arm_attr_t *attr = get_arm_attr(node); - attr->value = tv; + attr->imm_value = imm_value; +} + +/** + * Returns the fpaConst value + */ +tarval *get_fpaConst_value(const ir_node *node) { + const arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr_const(node); + return attr->tv; +} + +/** + * Sets the tarval value + */ +void set_fpaConst_value(ir_node *node, tarval *tv) { + arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr(node); + attr->tv = tv; } /** @@ -567,7 +610,7 @@ static void init_arm_attributes(ir_node *node, int flags, attr->out_req = out_reqs; attr->flags = flags; attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE; - attr->value = NULL; + attr->imm_value = 0; attr->out_flags = NEW_ARR_D(int, obst, n_res); memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0])); @@ -624,16 +667,22 @@ void arm_set_optimizers(void) { */ } -static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b) { - const arm_SymConst_attr_t *attr_a = get_irn_generic_attr_const(a); - const arm_SymConst_attr_t *attr_b = get_irn_generic_attr_const(b); - return attr_a->symconst_id != attr_b->symconst_id; -} - static int cmp_attr_arm(ir_node *a, ir_node *b) { arm_attr_t *attr_a = get_irn_generic_attr(a); arm_attr_t *attr_b = get_irn_generic_attr(b); - return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value); + return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value); +} + +static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b) { + const arm_SymConst_attr_t *attr_a; + const arm_SymConst_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_irn_generic_attr_const(a); + attr_b = get_irn_generic_attr_const(b); + return attr_a->symconst_id != attr_b->symconst_id; } static int cmp_attr_arm_CondJmp(ir_node *a, ir_node *b) { @@ -650,6 +699,19 @@ static int cmp_attr_arm_SwitchJmp(ir_node *a, ir_node *b) { return 1; } +static int cmp_attr_arm_fpaConst(ir_node *a, ir_node *b) { + const arm_fpaConst_attr_t *attr_a; + const arm_fpaConst_attr_t *attr_b; + + if (cmp_attr_arm(a, b)) + return 1; + + attr_a = get_arm_fpaConst_attr_const(a); + attr_b = get_arm_fpaConst_attr_const(b); + + return attr_a->tv != attr_b->tv; +} + /** copies the ARM attributes of a node. */ static void arm_copy_attr(const ir_node *old_node, ir_node *new_node) { ir_graph *irg = get_irn_irg(new_node); diff --git a/ir/be/arm/arm_new_nodes.h b/ir/be/arm/arm_new_nodes.h index a9f378a0a..a2c494441 100644 --- a/ir/be/arm/arm_new_nodes.h +++ b/ir/be/arm/arm_new_nodes.h @@ -145,14 +145,24 @@ void set_arm_out_flags(ir_node *node, arch_irn_flags_t flags, int pos); arch_irn_flags_t get_arm_out_flags(const ir_node *node, int pos); /** - * Returns the tarval + * Returns the immediate value */ -tarval *get_arm_value(const ir_node *node); +long get_arm_imm_value(const ir_node *node); /** - * Sets the tarval + * Sets the immediate value */ -void set_arm_value(ir_node *node, tarval *tv); +void set_arm_imm_value(ir_node *node, long imm_value); + +/** +* Return the tarval of a fpaConst +*/ +tarval *get_fpaConst_value(const ir_node *node); + +/** + * Sets the tarval of a fpaConst + */ +void set_fpaConst_value(ir_node *node, tarval *tv); /** * Returns the proj num @@ -198,7 +208,7 @@ arm_shift_modifier get_arm_shift_modifier(const ir_node *node); /** * Decode an immediate with shifter operand */ -unsigned int arm_decode_imm_w_shift(tarval *tv); +unsigned int arm_decode_imm_w_shift(long imm_value); /* Include the generated headers */ #include "gen_arm_new_nodes.h" diff --git a/ir/be/arm/arm_nodes_attr.h b/ir/be/arm/arm_nodes_attr.h index 2e531d663..599011370 100644 --- a/ir/be/arm/arm_nodes_attr.h +++ b/ir/be/arm/arm_nodes_attr.h @@ -19,8 +19,8 @@ /** * @file - * @brief declarations for arm node attributes - * @author Oliver Richter, Tobias Gneist + * @brief declarations for ARM node attributes + * @author Oliver Richter, Tobias Gneist, Michael Beck * @version $Id$ */ #ifndef FIRM_BE_ARM_ARM_NODES_ATTR_H @@ -87,6 +87,19 @@ typedef enum _arm_condition { /** Set the condition code to flags */ #define ARM_SET_COND(attr, code) ((attr)->instr_fl = (((attr)->instr_fl & ~(15 << 4)) | ((code) << 4))) +/** Encoding for fpa immediates */ +enum fpa_immediates { + fpa_null = 0, + fpa_one, + fpa_two, + fpa_three, + fpa_four, + fpa_five, + fpa_ten, + fpa_half, + fpa_max +}; + /** Generic ARM node attributes. */ typedef struct _arm_attr_t { except_attr exc; /**< the exception attribute. MUST be the first one. */ @@ -97,7 +110,7 @@ typedef struct _arm_attr_t { ir_mode *op_mode; /**< operation mode if different from node's mode */ unsigned instr_fl; /**< condition code, shift modifier */ - tarval *value; /**< immediate */ + long imm_value; /**< immediate */ int *out_flags; /**< flags for each produced value */ const arch_register_t **slots; /**< register slots for assigned registers */ @@ -105,26 +118,40 @@ typedef struct _arm_attr_t { /** Attributes for a SymConst */ typedef struct _arm_SymConst_attr_t { - arm_attr_t attr; + arm_attr_t attr; /**< base attributes */ ident *symconst_id; /**< for SymConsts: its ident */ } arm_SymConst_attr_t; /** Attributes for a CondJmp */ typedef struct _arm_CondJmp_attr_t { - arm_attr_t attr; + arm_attr_t attr; /**< base attributes */ int proj_num; } arm_CondJmp_attr_t; /** Attributes for a SwitchJmp */ typedef struct _arm_SwitchJmp_attr_t { - arm_attr_t attr; + arm_attr_t attr; /**< base attributes */ int n_projs; - long default_proj_num; + long default_proj_num; } arm_SwitchJmp_attr_t; +/** Attributes for a fpaConst */ +typedef struct _arm_fpaConst_attr_t { + arm_attr_t attr; /**< base attributes */ + tarval *tv; /**< the tarval representing the FP const */ +} arm_fpaConst_attr_t; + /** * Returns the shift modifier string. */ const char *arm_shf_mod_name(arm_shift_modifier mod); +/** + * Return the fpa immediate from the encoding. + */ +const char *arm_get_fpa_imm_name(long imm_value); + +#define CAST_ARM_ATTR(type,ptr) ((type *)(ptr)) +#define CONST_CAST_ARM_ATTR(type,ptr) ((const type *)(ptr)) + #endif diff --git a/ir/be/arm/arm_spec.pl b/ir/be/arm/arm_spec.pl index a9170a55e..10d956d18 100644 --- a/ir/be/arm/arm_spec.pl +++ b/ir/be/arm/arm_spec.pl @@ -183,6 +183,7 @@ $default_copy_attr = "arm_copy_attr"; arm_SymConst_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", arm_CondJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", + arm_fpaConst_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", ); %compare_attr = ( @@ -190,6 +191,7 @@ $default_copy_attr = "arm_copy_attr"; arm_SymConst_attr_t => "cmp_attr_arm_SymConst", arm_CondJmp_attr_t => "cmp_attr_arm_CondJmp", arm_SwitchJmp_attr_t => "cmp_attr_arm_SwitchJmp", + arm_fpaConst_attr_t => "cmp_attr_arm_fpaConst", ); #%operands = ( @@ -258,9 +260,9 @@ Add => { op_flags => "C", irn_flags => "R", comment => "construct Add: Add(a, b) = Add(b, a) = a + b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. add %D0, %S0, %S1%X' }, @@ -268,9 +270,9 @@ Add => { Add_i => { irn_flags => "R", comment => "construct Add: Add(a, const) = Add(const, a) = a + const", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. add %D0, %S0, %C' }, @@ -313,9 +315,9 @@ And => { op_flags => "C", irn_flags => "R", comment => "construct And: And(a, b) = And(b, a) = a AND b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. and %D0, %S0, %S1%X' }, @@ -323,20 +325,20 @@ And => { And_i => { irn_flags => "R", comment => "construct And: And(a, const) = And(const, a) = a AND const", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. and %D0, %S0, %C', - cmp_attr => 'return attr_a->value != attr_b->value;' + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;' }, Or => { op_flags => "C", irn_flags => "R", comment => "construct Or: Or(a, b) = Or(b, a) = a OR b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. orr %D0, %S0, %S1%X' }, @@ -344,10 +346,10 @@ Or => { Or_i => { irn_flags => "R", comment => "construct Or: Or(a, const) = Or(const, a) = a OR const", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, - cmp_attr => 'return attr_a->value != attr_b->value;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', emit => '. orr %D0, %S0, %C' }, @@ -355,9 +357,9 @@ Eor => { op_flags => "C", irn_flags => "R", comment => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. eor %D0, %S0, %S1%X' }, @@ -365,10 +367,10 @@ Eor => { Eor_i => { irn_flags => "R", comment => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, - cmp_attr => 'return attr_a->value != attr_b->value;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', emit => '. eor %D0, %S0, %C' }, @@ -377,9 +379,9 @@ Eor_i => { Bic => { irn_flags => "R", comment => "construct Bic: Bic(a, b) = a AND ~b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. bic %D0, %S0, %S1%X' }, @@ -387,19 +389,19 @@ Bic => { Bic_i => { irn_flags => "R", comment => "construct Bic: Bic(a, const) = a AND ~const", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. bic %D0, %S0, %C', - cmp_attr => 'return attr_a->value != attr_b->value;' + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;' }, Sub => { irn_flags => "R", comment => "construct Sub: Sub(a, b) = a - b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. sub %D0, %S0, %S1%X' }, @@ -407,9 +409,9 @@ Sub => { Sub_i => { irn_flags => "R", comment => "construct Sub: Sub(a, const) = a - const", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. sub %D0, %S0, %C', }, @@ -417,9 +419,9 @@ Sub_i => { Rsb => { irn_flags => "R", comment => "construct Rsb: Rsb(a, b) = b - a", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, emit => '. rsb %D0, %S0, %S1%X' }, @@ -427,11 +429,11 @@ Rsb => { Rsb_i => { irn_flags => "R", comment => "construct Rsb: Rsb(a, const) = const - a", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. rsb %D0, %S0, %C', - cmp_attr => 'return attr_a->value != attr_b->value;' + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;' }, Shl => { @@ -480,9 +482,9 @@ Shrs => { Mov => { irn_flags => "R", comment => "construct Mov: a = b", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. mov %D0, %S0%X' }, @@ -490,19 +492,19 @@ Mov => { Mov_i => { irn_flags => "R", comment => "represents an integer constant", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', reg_req => { "out" => [ "gp" ] }, emit => '. mov %D0, %C', - cmp_attr => 'return attr_a->value != attr_b->value;' + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;' }, Mvn => { irn_flags => "R", comment => "construct Not: Not(a) = !a", - attr => "arm_shift_modifier mod, tarval *shf", - init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;', - cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);', + attr => "arm_shift_modifier mod, long shf", + init_attr => 'ARM_SET_SHF_MOD(attr, mod); attr->imm_value = shf;', + cmp_attr => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->imm_value != attr_b->imm_value);', reg_req => { "in" => [ "gp" ], "out" => [ "gp" ] }, emit => '. mvn %D0, %S0%X' }, @@ -510,9 +512,9 @@ Mvn => { Mvn_i => { irn_flags => "R", comment => "represents a negated integer constant", - attr => "tarval *tv", - init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "out" => [ "gp" ] }, emit => '. mvn %D0, %C', }, @@ -549,8 +551,9 @@ CopyB => { op_flags => "F|H", state => "pinned", comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)", - attr => "tarval *tv", - init_attr => 'attr->value = tv;', + attr => "long imm", + init_attr => 'attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "!sp", "!sp", "gp", "gp", "gp", "none" ], "out" => [ "none" ] }, outs => [ "M" ], }, @@ -716,9 +719,9 @@ fpaAdf_i => { op_flags => "C", irn_flags => "R", comment => "construct FPA Add: Add(a, b) = Add(b, a) = a + b", - attr => "tarval *tv", - init_attr => 'ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa" ] }, emit => '. adf%M %D0, %S0, %C', }, @@ -735,9 +738,9 @@ fpaMuf_i => { op_flags => "C", irn_flags => "R", comment => "construct FPA Mul: Mul(a, b) = Mul(b, a) = a * b", - attr => "tarval *tv", - init_attr => 'ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa" ] }, emit => '. muf%M %D0, %S0, %C', }, @@ -778,9 +781,9 @@ fpaSuf => { fpaSuf_i => { irn_flags => "R", comment => "construct FPA Sub: Sub(a, b) = a - b", - attr => "tarval *tv", - init_attr => 'ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa" ] }, emit => '. suf%M %D0, %S0, %C' }, @@ -795,9 +798,9 @@ fpaRsf => { fpaRsf_i => { irn_flags => "R", comment => "construct FPA reverse Sub: Sub(a, b) = b - a", - attr => "tarval *tv", - init_attr => 'ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "long imm", + init_attr => 'ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa" ] }, emit => '. rsf%M %D0, %S0, %C' }, @@ -813,9 +816,9 @@ fpaDvf => { fpaDvf_i => { comment => "construct FPA Div: Div(a, b) = a / b", - attr => "ir_mode *op_mode, tarval *tv", - init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "ir_mode *op_mode, long imm", + init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa", "none" ] }, emit =>'. dvf%M %D0, %S0, %C', outs => [ "res", "M" ], @@ -832,9 +835,9 @@ fpaRdf => { fpaRdf_i => { comment => "construct FPA reverse Div: Div(a, b) = b / a", - attr => "ir_mode *op_mode, tarval *tv", - init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "ir_mode *op_mode, long imm", + init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa", "none" ] }, emit =>'. rdf%M %D0, %S0, %S1', outs => [ "res", "M" ], @@ -851,9 +854,9 @@ fpaFdv => { fpaFdv_i => { comment => "construct FPA Fast Div: Div(a, b) = a / b", - attr => "ir_mode *op_mode, tarval *tv", - init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "ir_mode *op_mode, long imm", + init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa", "none" ] }, emit =>'. fdv%M %D0, %S0, %C', outs => [ "res", "M" ], @@ -870,9 +873,9 @@ fpaFrd => { fpaFrd_i => { comment => "construct FPA Fast reverse Div: Div(a, b) = b / a", - attr => "ir_mode *op_mode, tarval *tv", - init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->value = tv;', - cmp_attr => 'return attr_a->value != attr_b->value;', + attr => "ir_mode *op_mode, long imm", + init_attr => 'attr->op_mode = op_mode; ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;', reg_req => { "in" => [ "fpa" ], "out" => [ "fpa", "none" ] }, emit =>'. frd%M %D0, %S0, %C', outs => [ "res", "M" ], @@ -888,12 +891,11 @@ fpaMvf => { fpaMvf_i => { irn_flags => "R", comment => "represents a float constant", - attr => "tarval *tv", - init_attr => 'ARM_SET_FPA_IMM(attr); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', reg_req => { "out" => [ "fpa" ] }, - mode => "get_tarval_mode(tv)", emit => '. mvf %D0, %C', - cmp_attr => 'return attr_a->value != attr_b->value;' + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;' }, fpaMnf => { @@ -906,12 +908,11 @@ fpaMnf => { fpaMnf_i => { irn_flags => "R", comment => "represents a float constant", - attr => "tarval *tv", - init_attr => 'ARM_SET_FPA_IMM(attr); attr->value = tv;', + attr => "long imm", + init_attr => 'ARM_SET_FPA_IMM(attr); attr->imm_value = imm;', reg_req => { "out" => [ "fpa" ] }, - mode => "get_tarval_mode(tv)", emit => '. mnf %D0, %C', - cmp_attr => 'return attr_a->value != attr_b->value;' + cmp_attr => 'return attr_a->imm_value != attr_b->imm_value;' }, fpaAbs => { @@ -1048,9 +1049,10 @@ fpaConst => { irn_flags => "R", comment => "construct a floating point constant", attr => "tarval *tv", - init_attr => "attr->value = tv;", + init_attr => "attr->tv = tv;", mode => "get_tarval_mode(tv)", reg_req => { "out" => [ "fpa" ] }, + attr_type => "arm_fpaConst_attr_t", } #---------------------------------------------------# diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c index b3f4e29af..2ef801958 100644 --- a/ir/be/arm/arm_transform.c +++ b/ir/be/arm/arm_transform.c @@ -134,13 +134,12 @@ static void gen_vals_from_word(unsigned int value, vals *result) */ static ir_node *create_const_node(dbg_info *dbg, ir_node *block, long value) { ir_mode *mode = mode_Iu; - tarval *tv = new_tarval_from_long(value, mode); ir_graph *irg = current_ir_graph; ir_node *res; if (mode_needs_gp_reg(mode)) mode = mode_Iu; - res = new_rd_arm_Mov_i(dbg, irg, block, mode, tv); + res = new_rd_arm_Mov_i(dbg, irg, block, mode, value); /* ensure the const is scheduled AFTER the stack frame */ add_irn_dep(res, get_irg_frame(irg)); return res; @@ -151,13 +150,12 @@ static ir_node *create_const_node(dbg_info *dbg, ir_node *block, long value) { */ static ir_node *create_const_neg_node(dbg_info *dbg, ir_node *block, long value) { ir_mode *mode = mode_Iu; - tarval *tv = new_tarval_from_long(value, mode); - ir_graph *irg = current_ir_graph; + ir_graph *irg = current_ir_graph; ir_node *res; if (mode_needs_gp_reg(mode)) mode = mode_Iu; - res = new_rd_arm_Mvn_i(dbg, irg, block, mode, tv); + res = new_rd_arm_Mvn_i(dbg, irg, block, mode, value); /* ensure the const is scheduled AFTER the stack frame */ add_irn_dep(res, get_irg_frame(irg)); return res; @@ -175,8 +173,8 @@ static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int imme /** * Decode an immediate with shifter operand */ -unsigned int arm_decode_imm_w_shift(tarval *tv) { - unsigned l = get_tarval_long(tv); +unsigned int arm_decode_imm_w_shift(long imm_value) { + unsigned l = (unsigned)imm_value; unsigned rol = (l & ~0xFF) >> 7; return do_rol(l & 0xFF, rol); @@ -199,8 +197,8 @@ static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned result = create_const_neg_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0])); for (cnt = 1; cnt < vn.ops; ++cnt) { - tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode); - ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv); + long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]); + ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, value); result = bic_i_node; } } @@ -209,8 +207,8 @@ static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned result = create_const_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0])); for (cnt = 1; cnt < v.ops; ++cnt) { - tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode); - ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv); + long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]); + ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, value); result = orr_i_node; } } @@ -242,7 +240,7 @@ static ir_node *create_const_graph(ir_node *irn, ir_node *block) { static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) { unsigned mask_bits = (1 << result_bits) - 1; ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits); - return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, NULL); + return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0); } /** @@ -352,7 +350,7 @@ static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) { *pmod = mod; if (mod != ARM_SHF_NONE) { - long v = get_tarval_long(get_arm_value(n)); + long v = get_arm_imm_value(n); if (v < 32) return (int)v; } @@ -381,9 +379,9 @@ static ir_node *gen_Add(ir_node *node) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { if (is_arm_fpaMvf_i(new_op1)) - return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); + return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_fpaMvf_i(new_op2)) - return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); + return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); @@ -399,9 +397,9 @@ static ir_node *gen_Add(ir_node *node) { mode = mode_Iu; if (is_arm_Mov_i(new_op1)) - return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); + return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); + return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); /* check for MLA */ if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) { @@ -423,17 +421,17 @@ static ir_node *gen_Add(ir_node *node) { v = is_shifter_operand(new_op1, &mod); if (v) { new_op1 = get_irn_n(new_op1, 0); - return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu)); + return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, v); } /* is the second a shifter */ v = is_shifter_operand(new_op2, &mod); if (v) { new_op2 = get_irn_n(new_op2, 0); - return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu)); + return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, v); } /* normal ADD */ - return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL); + return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0); } } @@ -456,9 +454,9 @@ static ir_node *gen_Mul(ir_node *node) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { if (is_arm_Mov_i(new_op1)) - return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); + return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); + return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); return new_rd_arm_fpaMuf(dbg, irg, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { @@ -496,9 +494,9 @@ static ir_node *gen_Quot(ir_node *node) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { if (is_arm_Mov_i(new_op1)) - return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_value(new_op1)); + return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_value(new_op2)); + return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_imm_value(new_op2)); return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); @@ -523,23 +521,23 @@ static ir_node *gen_Quot(ir_node *node) { arm_shift_modifier mod; \ \ if (is_arm_Mov_i(new_op1)) \ - return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); \ + return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); \ if (is_arm_Mov_i(new_op2)) \ - return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); \ + return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); \ /* is the first a shifter */ \ v = is_shifter_operand(new_op1, &mod); \ if (v) { \ new_op1 = get_irn_n(new_op1, 0); \ - return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \ + return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, v); \ } \ /* is the second a shifter */ \ v = is_shifter_operand(new_op2, &mod); \ if (v) { \ new_op2 = get_irn_n(new_op2, 0); \ - return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \ + return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, v); \ } \ /* Normal op */ \ - return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL) \ + return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \ /** * Creates an ARM And. @@ -590,9 +588,9 @@ static ir_node *gen_Sub(ir_node *node) { env_cg->have_fp_insn = 1; if (USE_FPA(env_cg->isa)) { if (is_arm_Mov_i(new_op1)) - return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); + return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); + return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode); } else if (USE_VFP(env_cg->isa)) { assert(mode != mode_E && "IEEE Extended FP not supported"); @@ -609,24 +607,24 @@ static ir_node *gen_Sub(ir_node *node) { mode = mode_Iu; if (is_arm_Mov_i(new_op1)) - return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); + return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); if (is_arm_Mov_i(new_op2)) - return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); + return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); /* is the first a shifter */ v = is_shifter_operand(new_op1, &mod); if (v) { new_op1 = get_irn_n(new_op1, 0); - return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu)); + return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, v); } /* is the second a shifter */ v = is_shifter_operand(new_op2, &mod); if (v) { new_op2 = get_irn_n(new_op2, 0); - return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu)); + return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, v); } /* normal sub */ - return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL); + return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0); } } @@ -645,7 +643,7 @@ static ir_node *gen_Shl(ir_node *node) { dbg_info *dbg = get_irn_dbg_info(node); if (is_arm_Mov_i(new_op2)) { - return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_value(new_op2)); + return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2)); } return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode); } @@ -665,7 +663,7 @@ static ir_node *gen_Shr(ir_node *node) { dbg_info *dbg = get_irn_dbg_info(node); if (is_arm_Mov_i(new_op2)) { - return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_value(new_op2)); + return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2)); } return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode); } @@ -685,7 +683,7 @@ static ir_node *gen_Shrs(ir_node *node) { dbg_info *dbg = get_irn_dbg_info(node); if (is_arm_Mov_i(new_op2)) { - return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_value(new_op2)); + return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2)); } return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode); } @@ -700,16 +698,14 @@ static ir_node *gen_Not(ir_node *node) { ir_node *op = get_Not_op(node); ir_node *new_op = be_transform_node(op); dbg_info *dbg = get_irn_dbg_info(node); - tarval *tv = NULL; ir_mode *mode = mode_Iu; arm_shift_modifier mod = ARM_SHF_NONE; int v = is_shifter_operand(new_op, &mod); if (v) { new_op = get_irn_n(new_op, 0); - tv = new_tarval_from_long(v, mode_Iu); } - return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, tv); + return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, v); } /** @@ -768,7 +764,7 @@ static ir_node *gen_Minus(ir_node *node) { } assert(mode_is_data(mode)); mode = mode_Iu; - return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, get_mode_null(mode)); + return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, 0); } /** @@ -958,7 +954,7 @@ static ir_node *gen_Cond(ir_node *node) { } const_graph = create_const_graph_value(dbg, block, translation); - sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, NULL); + sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0); return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation); } } @@ -987,18 +983,6 @@ static ident *get_sc_ident(ir_node *symc) { return NULL; } -enum fpa_immediates { - fpa_null = 0, - fpa_one, - fpa_two, - fpa_three, - fpa_four, - fpa_five, - fpa_ten, - fpa_half, - fpa_max -}; - static tarval *fpa_imm[3][fpa_max]; /** @@ -1027,9 +1011,9 @@ static int is_fpa_immediate(tarval *tv) { for (j = 0; j < fpa_max; ++j) { if (tv == fpa_imm[i][j]) - return res; + return res * j; } - return 0; + return fpa_max; } /** @@ -1049,11 +1033,11 @@ static ir_node *gen_Const(ir_node *node) { tarval *tv = get_Const_tarval(node); int imm = is_fpa_immediate(tv); - if (imm) { + if (imm != fpa_max) { if (imm > 0) - node = new_rd_arm_fpaMvf_i(dbg, irg, block, tv); + node = new_rd_arm_fpaMvf_i(dbg, irg, block, mode, imm); else - node = new_rd_arm_fpaMnf_i(dbg, irg, block, tv); + node = new_rd_arm_fpaMnf_i(dbg, irg, block, mode, -imm); } else { node = new_rd_arm_fpaConst(dbg, irg, block, tv); } @@ -1116,7 +1100,7 @@ static ir_node *gen_CopyB(ir_node *node) { new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), - new_mem, new_tarval_from_long(size, mode_Iu)); + new_mem, size); } @@ -1209,8 +1193,8 @@ static ir_node *gen_be_FrameAddr(ir_node *node) { } cnst = create_const_graph_value(dbg, block, (unsigned)offset); if (is_arm_Mov_i(cnst)) - return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_value(cnst)); - return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, NULL); + return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_imm_value(cnst)); + return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, 0); } #if 0 -- 2.20.1