From ec083e92f9e4154e81e1e6f661ec70ef49601aa6 Mon Sep 17 00:00:00 2001 From: Christoph Mallon Date: Sun, 11 Nov 2012 10:13:23 +0100 Subject: [PATCH] Panic when asked to simulate a vfprem. Simulating it as normal binop does only work in one special case. It lacks the reverse form and selecting the second operand register. So in many cases invalid code was generated silently. --- ir/be/ia32/ia32_spec.pl | 10 ---------- ir/be/ia32/ia32_x87.c | 9 ++++++++- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 402bce62d..7bd6634e7 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -2349,16 +2349,6 @@ fprem => { constructors => {}, }, -# this node is just here, to keep the simulator running -# we can omit this when a fprem simulation function exists -fpremp => { - emit => 'fprem1\n'. - 'fstp %F0', - latency => 20, - attr_type => "ia32_x87_attr_t", - constructors => {}, -}, - fdiv => { state => "exc_pinned", emit => 'fdiv%FM %AF', diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index ccdc7c0b1..6f579622a 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -1118,7 +1118,6 @@ GEN_BINOP(fadd) GEN_BINOPR(fsub) GEN_BINOP(fmul) GEN_BINOPR(fdiv) -GEN_BINOP(fprem) GEN_UNOP(fabs) GEN_UNOP(fchs) @@ -1131,6 +1130,14 @@ GEN_LOAD(fld1) GEN_STORE(fst) GEN_STORE(fist) +static int sim_fprem(x87_state *const state, ir_node *const n) +{ + (void)state; + (void)n; + panic("TODO implement"); + return NO_NODE_ADDED; +} + /** * Simulate a virtual fisttp. * -- 2.20.1