From db6fd292f8fa8e7dc3f4bc3dacd047d832baaaba Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 17 Oct 2007 17:09:19 +0000 Subject: [PATCH] - Add a generic_attribute field to irops - extend backend generator to support custom irop data - cleanup and streamline transform code in ia32 - Improve handling of AddAM vs. Add used in AM expressions [r16254] --- ir/be/TEMPLATE/TEMPLATE_new_nodes.c | 3 +- ir/be/arm/arm_new_nodes.c | 3 +- ir/be/arm/arm_spec.pl | 8 +- ir/be/bespillbelady.c | 6 +- ir/be/betranshlp.c | 4 + ir/be/betranshlp.h | 5 + ir/be/ia32/bearch_ia32.c | 2 +- ir/be/ia32/ia32_address_mode.c | 21 +- ir/be/ia32/ia32_address_mode.h | 9 +- ir/be/ia32/ia32_new_nodes.c | 16 +- ir/be/ia32/ia32_new_nodes.h | 11 +- ir/be/ia32/ia32_nodes_attr.h | 35 +- ir/be/ia32/ia32_simd_spec.pl | 5 +- ir/be/ia32/ia32_spec.pl | 178 ++++- ir/be/ia32/ia32_transform.c | 1049 +++++++++++++------------ ir/be/mips/mips_new_nodes.c | 3 +- ir/be/mips/mips_spec.pl | 6 +- ir/be/ppc32/ppc32_new_nodes.c | 3 +- ir/be/ppc32/ppc32_new_nodes.h | 5 - ir/be/scripts/generate_new_opcodes.pl | 64 +- ir/ir/irop_t.h | 10 + ir/ir/iropt.c | 1 + ir/ir/irtypes.h | 5 +- 23 files changed, 823 insertions(+), 629 deletions(-) diff --git a/ir/be/TEMPLATE/TEMPLATE_new_nodes.c b/ir/be/TEMPLATE/TEMPLATE_new_nodes.c index b0bb78a96..965b866d8 100644 --- a/ir/be/TEMPLATE/TEMPLATE_new_nodes.c +++ b/ir/be/TEMPLATE/TEMPLATE_new_nodes.c @@ -367,13 +367,12 @@ void init_TEMPLATE_attributes(ir_node *node, arch_irn_flags_t flags, const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) + int n_res) { ir_graph *irg = get_irn_irg(node); struct obstack *obst = get_irg_obstack(irg); TEMPLATE_attr_t *attr = get_TEMPLATE_attr(node); (void) execution_units; - (void) latency; attr->flags = flags; attr->out_req = out_reqs; diff --git a/ir/be/arm/arm_new_nodes.c b/ir/be/arm/arm_new_nodes.c index 41051fd06..a221dd2b1 100644 --- a/ir/be/arm/arm_new_nodes.c +++ b/ir/be/arm/arm_new_nodes.c @@ -535,12 +535,11 @@ static void init_arm_attributes(ir_node *node, int flags, const arch_register_req_t ** in_reqs, const arch_register_req_t ** out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) { + int n_res) { ir_graph *irg = get_irn_irg(node); struct obstack *obst = get_irg_obstack(irg); arm_attr_t *attr = get_arm_attr(node); (void) execution_units; - (void) latency; attr->in_req = in_reqs; attr->out_req = out_reqs; diff --git a/ir/be/arm/arm_spec.pl b/ir/be/arm/arm_spec.pl index 4744cae4d..5441e8a35 100644 --- a/ir/be/arm/arm_spec.pl +++ b/ir/be/arm/arm_spec.pl @@ -179,10 +179,10 @@ $default_attr_type = "arm_attr_t"; $default_copy_attr = "arm_copy_attr"; %init_attr = ( - arm_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", - arm_SymConst_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", - arm_CondJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", - arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + arm_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", + arm_SymConst_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", + arm_CondJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", + arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", ); %compare_attr = ( diff --git a/ir/be/bespillbelady.c b/ir/be/bespillbelady.c index 40aa77e86..523e286bc 100644 --- a/ir/be/bespillbelady.c +++ b/ir/be/bespillbelady.c @@ -312,7 +312,7 @@ static void displace(belady_env_t *env, workset_t *new_vals, int is_usage) { assert(is_usage); } } - DBG((dbg, DBG_DECIDE, " demand = %d\n", demand)); + //DBG((dbg, DBG_DECIDE, " demand = %d\n", demand)); /* 2. Make room for at least 'demand' slots @@ -320,10 +320,10 @@ static void displace(belady_env_t *env, workset_t *new_vals, int is_usage) { len = workset_get_length(ws); max_allowed = env->n_regs - demand; - DBG((dbg, DBG_DECIDE, " disposing %d values\n", ws->len - max_allowed)); - /* Only make more free room if we do not have enough */ if (len > max_allowed) { + DBG((dbg, DBG_DECIDE, " disposing %d values\n", ws->len - max_allowed)); + /* get current next-use distance */ for (i = 0; i < ws->len; ++i) { unsigned dist = get_distance(env, env->instr, env->instr_nr, workset_get_val(ws, i), !is_usage); diff --git a/ir/be/betranshlp.c b/ir/be/betranshlp.c index ddc9a0413..fabd05261 100644 --- a/ir/be/betranshlp.c +++ b/ir/be/betranshlp.c @@ -60,6 +60,10 @@ void be_set_transformed_node(ir_node *old_node, ir_node *new_node) { set_irn_link(old_node, new_node); } +int be_is_transformed(const ir_node *node) { + return irn_visited(node); +} + static INLINE ir_node *be_get_transformed_node(ir_node *old_node) { assert(irn_visited(old_node)); return (ir_node*) get_irn_link(old_node); diff --git a/ir/be/betranshlp.h b/ir/be/betranshlp.h index 3869c7bb9..ed31199db 100644 --- a/ir/be/betranshlp.h +++ b/ir/be/betranshlp.h @@ -68,6 +68,11 @@ ir_node *be_duplicate_node(ir_node *node); */ void be_set_transformed_node(ir_node *old_node, ir_node *new_node); +/** + * returns 1 if the node is already transformed + */ +int be_is_transformed(const ir_node *node); + /** * enqueue all inputs into the transform queue. */ diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 22475e042..6c884179a 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -1346,7 +1346,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { } in[0] = sp; - keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); sched_add_before(node, keep); // exchange memprojs diff --git a/ir/be/ia32/ia32_address_mode.c b/ir/be/ia32/ia32_address_mode.c index 42b31a197..1f065899a 100644 --- a/ir/be/ia32/ia32_address_mode.c +++ b/ir/be/ia32/ia32_address_mode.c @@ -420,6 +420,10 @@ void ia32_create_address_mode(ia32_address_t *addr, ir_node *node, int force) addr->base = node; } +void ia32_mark_non_am(ir_node *node) +{ + bitset_set(non_address_mode_nodes, get_irn_idx(node)); +} /** * Walker: mark those nodes that cannot be part of an address mode because @@ -433,8 +437,13 @@ static void mark_non_address_nodes(ir_node *node, void *env) ir_node *val; ir_node *left; ir_node *right; + ir_mode *mode; (void) env; + mode = get_irn_mode(node); + if(!mode_is_int(mode) && !mode_is_reference(mode) && mode != mode_b) + return; + switch(get_irn_opcode(node)) { case iro_Load: ptr = get_Load_ptr(node); @@ -455,15 +464,19 @@ static void mark_non_address_nodes(ir_node *node, void *env) case iro_Add: left = get_Add_left(node); right = get_Add_right(node); +#if 0 /* if we can do source address mode then we will never fold the add * into address mode */ - if(!mode_is_float(get_irn_mode(node)) && (is_immediate_simple(right) || + if((is_immediate_simple(right)) || (!ia32_use_source_address_mode(get_nodes_block(node), left, right) - && !ia32_use_source_address_mode(get_nodes_block(node), right, left)))) + && !ia32_use_source_address_mode(get_nodes_block(node), right, left))) { break; } bitset_set(non_address_mode_nodes, get_irn_idx(node)); +#else + break; +#endif /* fallthrough */ default: @@ -477,14 +490,14 @@ static void mark_non_address_nodes(ir_node *node, void *env) } } -void calculate_non_address_mode_nodes(ir_graph *irg) +void ia32_calculate_non_address_mode_nodes(ir_graph *irg) { non_address_mode_nodes = bitset_malloc(get_irg_last_idx(irg)); irg_walk_graph(irg, NULL, mark_non_address_nodes, NULL); } -void free_non_address_mode_nodes(void) +void ia32_free_non_address_mode_nodes(void) { bitset_free(non_address_mode_nodes); } diff --git a/ir/be/ia32/ia32_address_mode.h b/ir/be/ia32/ia32_address_mode.h index 949621eb7..2c2fac829 100644 --- a/ir/be/ia32/ia32_address_mode.h +++ b/ir/be/ia32/ia32_address_mode.h @@ -54,11 +54,16 @@ void ia32_create_address_mode(ia32_address_t *addr, ir_node *node, int force); * Mark those nodes of the given graph that cannot be used inside an * address mode because there values must be materialized in registers. */ -void calculate_non_address_mode_nodes(ir_graph *irg); +void ia32_calculate_non_address_mode_nodes(ir_graph *irg); /** * Free the non_address_mode information. */ -void free_non_address_mode_nodes(void); +void ia32_free_non_address_mode_nodes(void); + +/** + * mark a node so it will not be used as part of address modes + */ +void ia32_mark_non_am(ir_node *node); #endif diff --git a/ir/be/ia32/ia32_new_nodes.c b/ir/be/ia32/ia32_new_nodes.c index b584178a5..9d0360985 100644 --- a/ir/be/ia32/ia32_new_nodes.c +++ b/ir/be/ia32/ia32_new_nodes.c @@ -684,16 +684,9 @@ void set_ia32_frame_ent(ir_node *node, ir_entity *ent) { * Gets the instruction latency. */ unsigned get_ia32_latency(const ir_node *node) { - const ia32_attr_t *attr = get_ia32_attr_const(node); - return attr->latency; -} - -/** -* Sets the instruction latency. -*/ -void set_ia32_latency(ir_node *node, unsigned latency) { - ia32_attr_t *attr = get_ia32_attr(node); - attr->latency = latency; + const ir_op *op = get_irn_op(node); + const ia32_op_attr_t *op_attr = (ia32_op_attr_t*) get_op_attr(op); + return op_attr->latency; } /** @@ -993,7 +986,7 @@ void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) + int n_res) { ir_graph *irg = get_irn_irg(node); struct obstack *obst = get_irg_obstack(irg); @@ -1002,7 +995,6 @@ void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, set_ia32_flags(node, flags); set_ia32_in_req_all(node, in_reqs); set_ia32_out_req_all(node, out_reqs); - set_ia32_latency(node, latency); attr->exec_units = execution_units; #ifndef NDEBUG diff --git a/ir/be/ia32/ia32_new_nodes.h b/ir/be/ia32/ia32_new_nodes.h index 7624e6a04..2fc4ed939 100644 --- a/ir/be/ia32/ia32_new_nodes.h +++ b/ir/be/ia32/ia32_new_nodes.h @@ -47,7 +47,9 @@ enum { enum { pn_ia32_res = 0, pn_ia32_mem = 1, - pn_ia32_flags = 2 + pn_ia32_flags = 2, + pn_ia32_add1 = 3, + pn_ia32_add2 = 4 }; /*************************************************************************************************** @@ -324,11 +326,6 @@ unsigned get_ia32_copyb_size(const ir_node *node); */ unsigned get_ia32_latency(const ir_node *node); -/** - * Sets the instruction latency. - */ -void set_ia32_latency(ir_node *node, unsigned latency); - /** * Sets the flags for the n'th out. @@ -432,7 +429,7 @@ void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency); + int n_res); void init_ia32_x87_attributes(ir_node *node); void init_ia32_asm_attributes(ir_node *node); diff --git a/ir/be/ia32/ia32_nodes_attr.h b/ir/be/ia32/ia32_nodes_attr.h index bc7f84654..5b9893e09 100644 --- a/ir/be/ia32/ia32_nodes_attr.h +++ b/ir/be/ia32/ia32_nodes_attr.h @@ -53,18 +53,27 @@ typedef enum { ia32_am_ternary = 3, } ia32_am_arity_t; -/** - * Different Address Mode properties: - * O - Offset is set - * B - Base is set - * I - Index is set - * S - Scale is set - */ -enum { - ia32_O = (1 << 0), /**< O - Offset is set */ - ia32_B = (1 << 1), /**< B - Base is set */ - ia32_I = (1 << 2), /**< I - Index is set */ - ia32_S = (1 << 3) /**< S - Scale is set */ +typedef enum { + match_commutative = 1 << 0, /**< inputs are commutative */ + match_am_and_immediates = 1 << 1, /**< mode support AM and immediate at + the same time */ + match_am = 1 << 2, /**< node supports (32bit) source AM */ + match_8bit_am = 1 << 3, /**< node supports 8bit source AM */ + match_16bit_am = 1 << 4, /**< node supports 16bit source AM */ + match_immediate = 1 << 5, /**< node supports immediates */ + match_8bit = 1 << 6, /**< supports 8 bit modes natively */ + match_16bit = 1 << 7, /**< supports 16bit modes natively */ + match_mode_neutral = 1 << 8, /**< 16 and 8 bit modes can be emulated + by 32 bit operations */ + match_dest_am = 1 << 9, + match_try_am = 1 << 10, /**< only try to produce AM node, don't + do anything if AM isn't possible */ +} match_flags_t; + +typedef struct ia32_op_attr_t ia32_op_attr_t; +struct ia32_op_attr_t { + match_flags_t flags; + unsigned latency; }; #ifndef NDEBUG @@ -116,8 +125,6 @@ struct ia32_attr_t { ir_entity *frame_ent; /**< the frame entity attached to this node */ - unsigned latency; /**< the latency of the instruction in clock cycles */ - const be_execution_unit_t ***exec_units; /**< list of units this operation can be executed on */ const arch_register_req_t **in_req; /**< register requirements for arguments */ diff --git a/ir/be/ia32/ia32_simd_spec.pl b/ir/be/ia32/ia32_simd_spec.pl index b05035278..07778a22d 100644 --- a/ir/be/ia32/ia32_simd_spec.pl +++ b/ir/be/ia32/ia32_simd_spec.pl @@ -6,6 +6,7 @@ # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ $nodes{"mov_gp_variant0"} = { - "reg_req" => { "in" => [ "xmm", ], "out" => [ "gp", ] }, - "emit" => ". shl %S2, 15; .movd %S1, %S2", + reg_req => { "in" => [ "xmm", ], "out" => [ "gp", ] }, + emit => ". shl %S2, 15; .movd %S1, %S2", + latency => 3, }; diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 01cef5c94..f3c82084b 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -32,7 +32,6 @@ $arch = "ia32"; # attr => "attitional attribute arguments for constructor" # init_attr => "emit attribute initialization template" # rd_constructor => "c source code which constructs an ir_node" -# latency => "latency of this operation (can be float)" # attr_type => "name of the attribute struct", # }, # @@ -96,8 +95,6 @@ $arch = "ia32"; # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 # -# latency: the latency of the operation, default is 1 -# # register types: # 0 - no special type @@ -217,7 +214,7 @@ $arch = "ia32"; unop3 => "${arch}_emit_unop(node, 3);", unop4 => "${arch}_emit_unop(node, 4);", unop5 => "${arch}_emit_unop(node, 5);", - DAM1 => "${arch}_emit_am_or_dest_register(node, 1);", + DAM0 => "${arch}_emit_am_or_dest_register(node, 0);", binop => "${arch}_emit_binop(node);", x87_binop => "${arch}_emit_x87_binop(node);", CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);", @@ -234,13 +231,15 @@ $arch = "ia32"; # |_| # #--------------------------------------------------# -$default_attr_type = "ia32_attr_t"; -$default_copy_attr = "ia32_copy_attr"; +$default_op_attr_type = "ia32_op_attr_t"; +$default_attr_type = "ia32_attr_t"; +$default_copy_attr = "ia32_copy_attr"; sub ia32_custom_init_attr { my $node = shift; my $name = shift; my $res = ""; + if(defined($node->{modified_flags})) { $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n"; } @@ -279,22 +278,22 @@ sub ia32_custom_init_attr { $custom_init_attr_func = \&ia32_custom_init_attr; %init_attr = ( - ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", ia32_x87_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);", ia32_asm_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);". "\tinit_ia32_asm_attributes(res);", ia32_immediate_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);", ia32_copyb_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_copyb_attributes(res, size);", ia32_condcode_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_condcode_attributes(res, pnc);", ); @@ -375,6 +374,7 @@ Add => { emit => '. add%M %binop', am => "full,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -386,6 +386,7 @@ AddMem => { ins => [ "base", "index", "mem", "val" ], emit => ". add%M %SI3, %AM", units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -397,6 +398,7 @@ AddMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => ". add%M %SB3, %AM", units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -408,6 +410,7 @@ Adc => { emit => '. adc%M %binop', am => "full,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -486,9 +489,11 @@ And => { state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], + op_modes => "commutative | am | immediate | mode_neutral", am => "full,binary", emit => '. and%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -500,6 +505,7 @@ AndMem => { ins => [ "base", "index", "mem", "val" ], emit => '. and%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -511,6 +517,7 @@ AndMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. and%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -523,6 +530,7 @@ Or => { am => "full,binary", emit => '. or%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -534,6 +542,7 @@ OrMem => { ins => [ "base", "index", "mem", "val" ], emit => '. or%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -545,6 +554,7 @@ OrMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. or%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -557,6 +567,7 @@ Xor => { am => "full,binary", emit => '. xor%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -568,6 +579,7 @@ XorMem => { ins => [ "base", "index", "mem", "val" ], emit => '. xor%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -579,6 +591,7 @@ XorMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. xor%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -593,6 +606,7 @@ Sub => { am => "full,binary", emit => '. sub%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -604,6 +618,7 @@ SubMem => { ins => [ "base", "index", "mem", "val" ], emit => '. sub%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => 'mode_M', modified_flags => $status_flags }, @@ -615,6 +630,7 @@ SubMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. sub%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => 'mode_M', modified_flags => $status_flags }, @@ -626,6 +642,7 @@ Sbb => { am => "full,binary", emit => '. sbb%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -643,9 +660,9 @@ l_Sbb => { IDiv => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "none", "none", "edx" ] }, ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], - outs => [ "div_res", "mod_res", "M" ], + outs => [ "div_res", "M", "unused", "mod_res" ], am => "source,ternary", emit => ". idiv%M %unop5", latency => 25, @@ -656,9 +673,9 @@ IDiv => { Div => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "none", "none", "edx" ] }, ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], - outs => [ "div_res", "mod_res", "M" ], + outs => [ "div_res", "M", "unused", "mod_res" ], am => "source,ternary", emit => ". div%M %unop5", latency => 25, @@ -672,6 +689,7 @@ Shl => { ins => [ "left", "right" ], emit => '. shl %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -683,12 +701,14 @@ ShlMem => { ins => [ "base", "index", "mem", "count" ], emit => '. shl%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, l_ShlDep => { cmp_attr => "return 1;", + ins => [ "left", "right", "dep" ], # value, cnt, dependency arity => 3 }, @@ -708,6 +728,7 @@ ShlD => { l_ShlD => { cmp_attr => "return 1;", + ins => [ "high", "low", "count" ], arity => 3, }, @@ -718,6 +739,7 @@ Shr => { emit => '. shr %SB1, %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => $status_flags }, @@ -729,11 +751,13 @@ ShrMem => { emit => '. shr%M %SB3, %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => $status_flags }, l_ShrDep => { cmp_attr => "return 1;", + ins => [ "left", "right", "dep" ], # value, cnt, dependency arity => 3 }, @@ -766,7 +790,8 @@ ShrD => { l_ShrD => { cmp_attr => "return 1;", - arity => 3 + arity => 3, + ins => [ "high", "low", "count" ], }, Sar => { @@ -775,6 +800,7 @@ Sar => { ins => [ "val", "count" ], emit => '. sar %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -786,12 +812,14 @@ SarMem => { ins => [ "base", "index", "mem", "count" ], emit => '. sar%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, l_SarDep => { cmp_attr => "return 1;", + ins => [ "left", "right", "dep" ], # value, cnt, dependency arity => 3 }, @@ -802,6 +830,7 @@ Ror => { ins => [ "val", "count" ], emit => '. ror %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -813,6 +842,7 @@ RorMem => { ins => [ "base", "index", "mem", "count" ], emit => '. ror%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -823,6 +853,7 @@ Rol => { ins => [ "val", "count" ], emit => '. rol %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -834,6 +865,7 @@ RolMem => { ins => [ "base", "index", "mem", "count" ], emit => '. rol%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -846,6 +878,7 @@ Neg => { emit => '. neg %S0', ins => [ "val" ], units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -857,6 +890,7 @@ NegMem => { ins => [ "base", "index", "mem" ], emit => '. neg%M %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -866,21 +900,18 @@ Minus64Bit => { reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] }, outs => [ "low_res", "high_res" ], units => [ "GP" ], + latency => 3, modified_flags => $status_flags }, -l_Neg => { - cmp_attr => "return 1;", - arity => 1, -}, - Inc => { irn_flags => "R", reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, emit => '. inc %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, @@ -892,6 +923,7 @@ IncMem => { emit => '. inc%M %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, @@ -901,6 +933,7 @@ Dec => { emit => '. dec %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, @@ -912,6 +945,7 @@ DecMem => { emit => '. dec%M %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, @@ -921,6 +955,7 @@ Not => { ins => [ "val" ], emit => '. not %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, }, @@ -931,6 +966,7 @@ NotMem => { ins => [ "base", "index", "mem" ], emit => '. not%M %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", }, @@ -1065,6 +1101,7 @@ IJmp => { ins => [ "base", "index", "mem", "target" ], am => "source,unary", emit => '. jmp *%unop3', + latency => 1, units => [ "BRANCH" ], mode => "mode_X", }, @@ -1076,9 +1113,8 @@ Const => { units => [ "GP" ], attr => "ir_entity *symconst, int symconst_sign, long offset", attr_type => "ia32_immediate_attr_t", + latency => 1, mode => $mode_gp, -# depends on the const and is set in ia32_transform -# modified_flags => $status_flags }, Unknown_GP => { @@ -1088,6 +1124,7 @@ Unknown_GP => { reg_req => { out => [ "gp_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, @@ -1099,6 +1136,7 @@ Unknown_VFP => { units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, @@ -1109,6 +1147,7 @@ Unknown_XMM => { reg_req => { out => [ "xmm_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -1119,6 +1158,7 @@ NoReg_GP => { reg_req => { out => [ "gp_NOREG" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, @@ -1130,6 +1170,7 @@ NoReg_VFP => { units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, @@ -1140,6 +1181,7 @@ NoReg_XMM => { reg_req => { out => [ "xmm_NOREG" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -1182,6 +1224,7 @@ Cltd => { reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] }, ins => [ "val", "globbered" ], emit => '. cltd', + latency => 1, mode => $mode_gp, units => [ "GP" ], }, @@ -1265,9 +1308,9 @@ Push => { Pop => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "esp", "gp", "none" ] }, - emit => '. pop%M %DAM1', - outs => [ "stack:I|S", "res", "M" ], + reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "gp", "none", "none", "esp" ] }, + emit => '. pop%M %DAM0', + outs => [ "res", "M", "unused", "stack:I|S" ], ins => [ "base", "index", "mem", "stack" ], am => "dest,unary", latency => 3, # Pop is more expensive than Push on Athlon @@ -1297,6 +1340,7 @@ AddSP => { ins => [ "base", "index", "mem", "stack", "size" ], am => "source,binary", emit => '. addl %binop', + latency => 1, outs => [ "stack:S", "M" ], units => [ "GP" ], modified_flags => $status_flags @@ -1310,6 +1354,7 @@ SubSP => { am => "source,binary", emit => ". subl %binop\n". ". movl %%esp, %D1", + latency => 2, outs => [ "stack:I|S", "addr", "M" ], units => [ "GP" ], modified_flags => $status_flags @@ -1319,6 +1364,7 @@ LdTls => { irn_flags => "R", reg_req => { out => [ "gp" ] }, units => [ "GP" ], + latency => 1, }, @@ -1409,6 +1455,7 @@ xOr => { ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. orp%XSD %binop', + latency => 3, units => [ "SSE" ], mode => "mode_E", }, @@ -1565,6 +1612,7 @@ CopyB => { attr_type => "ia32_copyb_attr_t", attr => "unsigned size", units => [ "GP" ], + latency => 3, # we don't care about this flag, so no need to mark this node # modified_flags => [ "DF" ] }, @@ -1577,6 +1625,7 @@ CopyB_i => { attr_type => "ia32_copyb_attr_t", attr => "unsigned size", units => [ "GP" ], + latency => 3, # we don't care about this flag, so no need to mark this node # modified_flags => [ "DF" ] }, @@ -1589,6 +1638,7 @@ Conv_I2I => { ins => [ "base", "index", "mem", "val" ], am => "source,unary", units => [ "GP" ], + latency => 1, attr => "ir_mode *smaller_mode", init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, @@ -1600,6 +1650,7 @@ Conv_I2I8Bit => { ins => [ "base", "index", "mem", "val" ], am => "source,unary", units => [ "GP" ], + latency => 1, attr => "ir_mode *smaller_mode", init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, @@ -1908,6 +1959,7 @@ Sahf => { ins => [ "val" ], outs => [ "flags" ], emit => '. sahf', + latency => 1, units => [ "GP" ], mode => $mode_flags, }, @@ -1928,6 +1980,7 @@ fadd => { rd_constructor => "NONE", reg_req => { }, emit => '. fadd%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1936,6 +1989,7 @@ faddp => { rd_constructor => "NONE", reg_req => { }, emit => '. faddp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1944,6 +1998,7 @@ fmul => { rd_constructor => "NONE", reg_req => { }, emit => '. fmul%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1952,6 +2007,7 @@ fmulp => { rd_constructor => "NONE", reg_req => { }, emit => '. fmulp%XM %x87_binop',, + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1960,6 +2016,7 @@ fsub => { rd_constructor => "NONE", reg_req => { }, emit => '. fsub%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1969,6 +2026,7 @@ fsubp => { reg_req => { }, # see note about gas bugs emit => '. fsubrp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1978,6 +2036,7 @@ fsubr => { irn_flags => "R", reg_req => { }, emit => '. fsubr%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1988,6 +2047,7 @@ fsubrp => { reg_req => { }, # see note about gas bugs emit => '. fsubp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1995,6 +2055,7 @@ fprem => { rd_constructor => "NONE", reg_req => { }, emit => '. fprem1', + latency => 20, attr_type => "ia32_x87_attr_t", }, @@ -2003,7 +2064,9 @@ fprem => { fpremp => { rd_constructor => "NONE", reg_req => { }, - emit => '. fprem1', + emit => '. fprem1\n'. + '. fstp %X0', + latency => 20, attr_type => "ia32_x87_attr_t", }, @@ -2012,6 +2075,7 @@ fdiv => { rd_constructor => "NONE", reg_req => { }, emit => '. fdiv%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, @@ -2021,6 +2085,7 @@ fdivp => { reg_req => { }, # see note about gas bugs emit => '. fdivrp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, @@ -2029,6 +2094,7 @@ fdivr => { rd_constructor => "NONE", reg_req => { }, emit => '. fdivr%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, @@ -2038,6 +2104,7 @@ fdivrp => { reg_req => { }, # see note about gas bugs emit => '. fdivp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, @@ -2045,6 +2112,7 @@ fabs => { rd_constructor => "NONE", reg_req => { }, emit => '. fabs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -2053,6 +2121,7 @@ fchs => { rd_constructor => "NONE", reg_req => { }, emit => '. fchs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -2065,6 +2134,7 @@ fld => { reg_req => { }, emit => '. fld%XM %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fst => { @@ -2075,6 +2145,7 @@ fst => { emit => '. fst%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fstp => { @@ -2085,6 +2156,7 @@ fstp => { emit => '. fstp%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # Conversions @@ -2095,6 +2167,7 @@ fild => { reg_req => { }, emit => '. fild%M %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fist => { @@ -2104,6 +2177,7 @@ fist => { emit => '. fist%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fistp => { @@ -2113,6 +2187,7 @@ fistp => { emit => '. fistp%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # constants @@ -2123,6 +2198,7 @@ fldz => { reg_req => { out => [ "vfp" ] }, emit => '. fldz', attr_type => "ia32_x87_attr_t", + latency => 2, }, fld1 => { @@ -2131,6 +2207,7 @@ fld1 => { reg_req => { out => [ "vfp" ] }, emit => '. fld1', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldpi => { @@ -2139,6 +2216,7 @@ fldpi => { reg_req => { out => [ "vfp" ] }, emit => '. fldpi', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldln2 => { @@ -2147,6 +2225,7 @@ fldln2 => { reg_req => { out => [ "vfp" ] }, emit => '. fldln2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldlg2 => { @@ -2155,6 +2234,7 @@ fldlg2 => { reg_req => { out => [ "vfp" ] }, emit => '. fldlg2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2t => { @@ -2163,6 +2243,7 @@ fldl2t => { reg_req => { out => [ "vfp" ] }, emit => '. fldll2t', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2e => { @@ -2171,6 +2252,7 @@ fldl2e => { reg_req => { out => [ "vfp" ] }, emit => '. fldl2e', attr_type => "ia32_x87_attr_t", + latency => 2, }, # fxch, fpush, fpop @@ -2184,6 +2266,7 @@ fxch => { emit => '. fxch %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, fpush => { @@ -2193,6 +2276,7 @@ fpush => { emit => '. fld %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, fpushCopy => { @@ -2200,6 +2284,7 @@ fpushCopy => { cmp_attr => "return 1;", emit => '. fld %X0', attr_type => "ia32_x87_attr_t", + latency => 1, }, fpop => { @@ -2209,6 +2294,7 @@ fpop => { emit => '. fstp %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, ffreep => { @@ -2218,6 +2304,7 @@ ffreep => { emit => '. ffreep %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, emms => { @@ -2227,6 +2314,7 @@ emms => { emit => '. emms', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 3, }, femms => { @@ -2236,6 +2324,7 @@ femms => { emit => '. femms', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 3, }, # compare @@ -2245,6 +2334,7 @@ FucomFnstsw => { emit => ". fucom %X1\n". ". fnstsw", attr_type => "ia32_x87_attr_t", + latency => 2, }, FucompFnstsw => { @@ -2252,6 +2342,7 @@ FucompFnstsw => { emit => ". fucomp %X1\n". ". fnstsw", attr_type => "ia32_x87_attr_t", + latency => 2, }, FucomppFnstsw => { @@ -2259,18 +2350,21 @@ FucomppFnstsw => { emit => ". fucompp\n". ". fnstsw", attr_type => "ia32_x87_attr_t", + latency => 2, }, Fucomi => { reg_req => { }, emit => '. fucomi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, Fucompi => { reg_req => { }, emit => '. fucompi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, FtstFnstsw => { @@ -2278,6 +2372,7 @@ FtstFnstsw => { emit => ". ftst\n". ". fnstsw", attr_type => "ia32_x87_attr_t", + latency => 2, }, @@ -2300,6 +2395,7 @@ xxLoad => { emit => '. movdqu %D0, %AM', outs => [ "res", "M" ], units => [ "SSE" ], + latency => 1, }, xxStore => { @@ -2309,6 +2405,7 @@ xxStore => { ins => [ "base", "index", "mem", "val" ], emit => '. movdqu %binop', units => [ "SSE" ], + latency => 1, mode => "mode_M", }, @@ -2321,3 +2418,28 @@ unless ($return = do $my_script_name) { warn "couldn't do $my_script_name: $!" unless defined $return; warn "couldn't run $my_script_name" unless $return; } + +# Transform some attributes +foreach my $op (keys(%nodes)) { + my $node = $nodes{$op}; + my $op_attr_init = $node->{op_attr_init}; + + if(defined($op_attr_init)) { + $op_attr_init .= "\n\t"; + } else { + $op_attr_init = ""; + } + + if(!defined($node->{latency})) { + if($op =~ m/^l_/) { + $node->{latency} = 0; + } else { + die("Latency missing for op $op"); + } + } + $op_attr_init .= "attr->latency = ".$node->{latency} . ";"; + + $node->{op_attr_init} = $op_attr_init; +} + +print "ok"; diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 029ac450c..63e5249cc 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -470,8 +470,11 @@ int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other) long pn; /* float constants are always available */ - if(is_Const(node) && mode_is_float(mode) - && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) { + if(is_Const(node) && mode_is_float(mode)) { + if(!is_simple_x87_Const(node)) + return 0; + if(get_irn_n_edges(node) > 1) + return 0; return 1; } @@ -486,6 +489,11 @@ int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other) /* we only use address mode if we're the only user of the load */ if(get_irn_n_edges(node) > 1) return 0; + /* in some edge cases with address mode we might reach the load normally + * and through some AM sequence, if it is already materialized then we + * can't create an AM node from it */ + if(be_is_transformed(node)) + return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ if(other != NULL && get_nodes_block(other) == block @@ -561,7 +569,7 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) addr->mem = new_mem; } -static void set_address(ir_node *node, ia32_address_t *addr) +static void set_address(ir_node *node, const ia32_address_t *addr) { set_ia32_am_scale(node, addr->scale); set_ia32_am_sc(node, addr->symconst_ent); @@ -573,7 +581,7 @@ static void set_address(ir_node *node, ia32_address_t *addr) set_ia32_frame_ent(node, addr->frame_entity); } -static void set_am_attributes(ir_node *node, ia32_address_mode_t *am) +static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am) { set_address(node, &am->addr); @@ -623,17 +631,25 @@ ir_node *ia32_skip_downconv(ir_node *node) { return node; } +#if 0 +static ir_node *create_upconv(ir_node *node, ir_node *orig_node) +{ + ir_mode *mode = get_irn_mode(node); + ir_node *block; + ir_mode *tgt_mode; + dbg_info *dbgi; -typedef enum { - match_commutative = 1 << 0, - match_am_and_immediates = 1 << 1, - match_no_am = 1 << 2, - match_8_bit_am = 1 << 3, - match_16_bit_am = 1 << 4, - match_no_immediate = 1 << 5, - match_force_32bit_op = 1 << 6, - match_skip_input_conv = 1 << 7 -} match_flags_t; + if(mode_is_signed(mode)) { + tgt_mode = mode_Is; + } else { + tgt_mode = mode_Iu; + } + block = get_nodes_block(node); + dbgi = get_irn_dbg_info(node); + + return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node); +} +#endif static void match_arguments(ia32_address_mode_t *am, ir_node *block, ir_node *op1, ir_node *op2, match_flags_t flags) @@ -647,31 +663,43 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, unsigned commutative; int use_am_and_immediates; int use_immediate; - int skip_input_conv; int mode_bits = get_mode_size_bits(mode); memset(am, 0, sizeof(am[0])); commutative = (flags & match_commutative) != 0; use_am_and_immediates = (flags & match_am_and_immediates) != 0; - use_am = ! (flags & match_no_am); - use_immediate = !(flags & match_no_immediate); - skip_input_conv = (flags & match_skip_input_conv) != 0; + use_am = (flags & match_am) != 0; + use_immediate = (flags & match_immediate) != 0; + assert(!use_am_and_immediates || use_immediate); assert(op2 != NULL); assert(!commutative || op1 != NULL); - if(mode_bits == 8 && !(flags & match_8_bit_am)) { - use_am = 0; - } else if(mode_bits == 16 && !(flags & match_16_bit_am)) { - use_am = 0; + if(mode_bits == 8) { + if (! (flags & match_8bit_am)) + use_am = 0; + assert((flags & match_mode_neutral) || (flags & match_8bit)); + } else if(mode_bits == 16) { + if(! (flags & match_16bit_am)) + use_am = 0; + assert((flags & match_mode_neutral) || (flags & match_16bit)); } - op2 = ia32_skip_downconv(op2); - if(op1 != NULL) - op1 = ia32_skip_downconv(op1); + /* we can simply skip downconvs for mode neutral nodes: the upper bits + * can be random for these operations */ + if(flags & match_mode_neutral) { + op2 = ia32_skip_downconv(op2); + if(op1 != NULL) { + op1 = ia32_skip_downconv(op1); + } + } + + if(! (flags & match_try_am) && use_immediate) + new_op2 = try_create_Immediate(op2, 0); + else + new_op2 = NULL; - new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL); if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) { build_address(am, op2); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); @@ -701,15 +729,20 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { + if(flags & match_try_am) { + am->new_op1 = NULL; + am->new_op2 = NULL; + am->op_type = ia32_Normal; + return; + } + new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if(new_op2 == NULL) new_op2 = be_transform_node(op2); am->op_type = ia32_Normal; - if(flags & match_force_32bit_op) { + am->ls_mode = get_irn_mode(op2); + if(flags & match_mode_neutral) am->ls_mode = mode_Iu; - } else { - am->ls_mode = get_irn_mode(op2); - } } if(addr->base == NULL) addr->base = noreg_gp; @@ -766,8 +799,6 @@ static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - flags |= match_force_32bit_op; - match_arguments(&am, block, op1, op2, flags); new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, @@ -833,39 +864,6 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, return new_node; } -/** - * Construct a standard binary operation, set AM and immediate if required. - * - * @param op1 The first operand - * @param op2 The second operand - * @param func The node constructor function - * @return The constructed ia32 node. - */ -static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2, - construct_binop_func *func, - match_flags_t flags) -{ - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *new_node; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - match_arguments(&am, block, op1, op2, flags); - - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2); - set_am_attributes(new_node, &am); - - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - new_node = fix_mem_proj(new_node, &am); - - return new_node; -} - static ir_node *get_fpcw(void) { ir_node *fpcw; @@ -921,19 +919,29 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, * @return The constructed ia32 node. */ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, - construct_shift_func *func) + construct_shift_func *func, + match_flags_t flags) { dbg_info *dbgi = get_irn_dbg_info(node); ir_graph *irg = current_ir_graph; ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *new_op1 = be_transform_node(op1); + ir_mode *mode = get_irn_mode(node); + ir_node *new_op1; ir_node *new_op2; ir_node *new_node; - assert(! mode_is_float(get_irn_mode(node)) - && "Shift/Rotate with float not supported"); + assert(! mode_is_float(mode)); + assert(flags & match_immediate); + assert((flags & ~(match_mode_neutral | match_immediate)) == 0); + + if(flags & match_mode_neutral) { + op1 = ia32_skip_downconv(op1); + } + new_op1 = be_transform_node(op1); + /* the shift amount can be any mode that is bigger than 5 bits, since all + * other bits are ignored anyway */ while (is_Conv(op2) && get_irn_n_edges(op2) == 1) { op2 = get_Conv_op(op2); assert(get_mode_size_bits(get_irn_mode(op2)) >= 5); @@ -961,15 +969,23 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, * @param func The node constructor function * @return The constructed ia32 node. */ -static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func) +static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, + match_flags_t flags) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = be_transform_node(op); - ir_node *new_node = NULL; - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *new_op; + ir_node *new_node; + + assert(flags == 0 || flags == match_mode_neutral); + if(flags & match_mode_neutral) { + op = ia32_skip_downconv(op); + } - new_node = func(dbgi, irg, block, new_op); + new_op = be_transform_node(op); + new_node = func(dbgi, irg, new_block, new_op); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -1028,11 +1044,15 @@ static ir_node *gen_Add(ir_node *node) { if (mode_is_float(mode)) { if (USE_SSE2(env_cg)) - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative); + return gen_binop(node, op1, op2, new_rd_ia32_xAdd, + match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, + match_commutative | match_am); } + ia32_mark_non_am(node); + op2 = ia32_skip_downconv(op2); op1 = ia32_skip_downconv(op1); @@ -1076,8 +1096,8 @@ static ir_node *gen_Add(ir_node *node) { } /* test if we can use source address mode */ - match_arguments(&am, block, op1, op2, - match_commutative | match_force_32bit_op | match_skip_input_conv); + match_arguments(&am, block, op1, op2, match_commutative + | match_mode_neutral | match_am | match_immediate | match_try_am); /* construct an Add with source address mode */ if (am.op_type == ia32_AddrModeS) { @@ -1111,9 +1131,11 @@ static ir_node *gen_Mul(ir_node *node) { if (mode_is_float(mode)) { if (USE_SSE2(env_cg)) - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative); + return gen_binop(node, op1, op2, new_rd_ia32_xMul, + match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, + match_commutative | match_am); } /* @@ -1122,7 +1144,7 @@ static ir_node *gen_Mul(ir_node *node) { constraints */ return gen_binop(node, op1, op2, new_rd_ia32_IMul, - match_commutative | match_skip_input_conv | match_force_32bit_op); + match_commutative | match_am | match_mode_neutral); } /** @@ -1147,9 +1169,10 @@ static ir_node *gen_Mulh(ir_node *node) ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - flags = match_force_32bit_op | match_commutative | match_no_immediate; + flags = match_commutative | match_am; assert(!mode_is_float(mode) && "Mulh with float not supported"); + assert(get_mode_size_bits(mode) == 32); match_arguments(&am, block, op1, op2, flags); @@ -1216,7 +1239,8 @@ static ir_node *gen_And(ir_node *node) { } return gen_binop(node, op1, op2, new_rd_ia32_And, - match_commutative | match_force_32bit_op | match_skip_input_conv); + match_commutative | match_mode_neutral | match_am + | match_immediate); } @@ -1231,8 +1255,8 @@ static ir_node *gen_Or(ir_node *node) { ir_node *op2 = get_Or_right(node); assert (! mode_is_float(get_irn_mode(node))); - return gen_binop(node, op1, op2, new_rd_ia32_Or, - match_commutative | match_skip_input_conv | match_force_32bit_op); + return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative + | match_mode_neutral | match_am | match_immediate); } @@ -1247,8 +1271,8 @@ static ir_node *gen_Eor(ir_node *node) { ir_node *op2 = get_Eor_right(node); assert(! mode_is_float(get_irn_mode(node))); - return gen_binop(node, op1, op2, new_rd_ia32_Xor, - match_commutative | match_skip_input_conv | match_force_32bit_op); + return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative + | match_mode_neutral | match_am | match_immediate); } @@ -1264,9 +1288,10 @@ static ir_node *gen_Sub(ir_node *node) { if (mode_is_float(mode)) { if (USE_SSE2(env_cg)) - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0); + return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, + match_am); } if(is_Const(op2)) { @@ -1274,120 +1299,113 @@ static ir_node *gen_Sub(ir_node *node) { node); } - return gen_binop(node, op1, op2, new_rd_ia32_Sub, - match_force_32bit_op | match_skip_input_conv); + return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral + | match_am | match_immediate); } -typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t; - /** * Generates an ia32 DivMod with additional infrastructure for the * register allocator if needed. - * - * @param dividend -no comment- :) - * @param divisor -no comment- :) - * @param dm_flav flavour_Div/Mod/DivMod - * @return The created ia32 DivMod node */ -static ir_node *generate_DivMod(ir_node *node, ir_node *dividend, - ir_node *divisor, ia32_op_flavour_t dm_flav) +static ir_node *create_Div(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_dividend = be_transform_node(dividend); - ir_node *new_divisor = be_transform_node(divisor); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *res, *proj_div, *proj_mod; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *mem; + ir_node *new_mem; + ir_node *op1; + ir_node *op2; + ir_node *new_node; ir_mode *mode; ir_node *sign_extension; - ir_node *mem, *new_mem; int has_exc; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; /* the upper bits have random contents for smaller modes */ - - proj_div = proj_mod = NULL; - has_exc = 0; - switch (dm_flav) { - case flavour_Div: - mem = get_Div_mem(node); - mode = get_Div_resmode(node); - proj_div = be_get_Proj_for_pn(node, pn_Div_res); - has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL; - break; - case flavour_Mod: - mem = get_Mod_mem(node); - mode = get_Mod_resmode(node); - proj_mod = be_get_Proj_for_pn(node, pn_Mod_res); - has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL; - break; - case flavour_DivMod: - mem = get_DivMod_mem(node); - mode = get_DivMod_resmode(node); - proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div); - proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod); - has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL; - break; - default: - panic("invalid divmod flavour!"); + has_exc = 0; + switch (get_irn_opcode(node)) { + case iro_Div: + op1 = get_Div_left(node); + op2 = get_Div_right(node); + mem = get_Div_mem(node); + mode = get_Div_resmode(node); + has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL; + break; + case iro_Mod: + op1 = get_Mod_left(node); + op2 = get_Mod_right(node); + mem = get_Mod_mem(node); + mode = get_Mod_resmode(node); + has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL; + break; + case iro_DivMod: + op1 = get_DivMod_left(node); + op2 = get_DivMod_right(node); + mem = get_DivMod_mem(node); + mode = get_DivMod_resmode(node); + has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL; + break; + default: + panic("invalid divmod node %+F", node); } - new_mem = be_transform_node(mem); - assert(get_mode_size_bits(mode) == 32); + match_arguments(&am, block, op1, op2, match_am); - if (mode_is_signed(mode)) { - /* in signed mode, we need to sign extend the dividend */ - ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block); - add_irn_dep(produceval, get_irg_frame(irg)); - sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend, - produceval); + if(!is_NoMem(mem)) { + new_mem = be_transform_node(mem); + if(!is_NoMem(addr->mem)) { + ir_node *in[2]; + in[0] = new_mem; + in[1] = addr->mem; + new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in); + } } else { - sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0); - set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags); - add_irn_dep(sign_extension, get_irg_frame(irg)); + new_mem = addr->mem; } if (mode_is_signed(mode)) { - res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem, - new_dividend, sign_extension, new_divisor); + ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); + add_irn_dep(produceval, get_irg_frame(irg)); + sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1, + produceval); + + new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base, + addr->index, new_mem, am.new_op1, + sign_extension, am.new_op2); } else { - res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, - new_dividend, sign_extension, new_divisor); + sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0); + add_irn_dep(sign_extension, get_irg_frame(irg)); + + new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base, + addr->index, new_mem, am.new_op1, + sign_extension, am.new_op2); } - set_ia32_exc_label(res, has_exc); - set_irn_pinned(res, get_irn_pinned(node)); + set_ia32_exc_label(new_node, has_exc); + set_irn_pinned(new_node, get_irn_pinned(node)); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + set_am_attributes(new_node, &am); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + new_node = fix_mem_proj(new_node, &am); + + return new_node; } -/** - * Wrapper for generate_DivMod. Sets flavour_Mod. - * - */ static ir_node *gen_Mod(ir_node *node) { - return generate_DivMod(node, get_Mod_left(node), - get_Mod_right(node), flavour_Mod); + return create_Div(node); } -/** - * Wrapper for generate_DivMod. Sets flavour_Div. - * - */ static ir_node *gen_Div(ir_node *node) { - return generate_DivMod(node, get_Div_left(node), - get_Div_right(node), flavour_Div); + return create_Div(node); } -/** - * Wrapper for generate_DivMod. Sets flavour_DivMod. - */ static ir_node *gen_DivMod(ir_node *node) { - return generate_DivMod(node, get_DivMod_left(node), - get_DivMod_right(node), flavour_DivMod); + return create_Div(node); } @@ -1403,9 +1421,9 @@ static ir_node *gen_Quot(ir_node *node) ir_node *op2 = get_Quot_right(node); if (USE_SSE2(env_cg)) { - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0); + return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am); } else { - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am); } } @@ -1419,21 +1437,20 @@ static ir_node *gen_Shl(ir_node *node) { ir_node *left = get_Shl_left(node); ir_node *right = get_Shl_right(node); - left = ia32_skip_downconv(left); - return gen_shift_binop(node, left, right, new_rd_ia32_Shl); + return gen_shift_binop(node, left, right, new_rd_ia32_Shl, + match_mode_neutral | match_immediate); } - - /** * Creates an ia32 Shr. * * @return The created ia32 Shr node */ static ir_node *gen_Shr(ir_node *node) { - assert(get_mode_size_bits(get_irn_mode(node)) == 32); - return gen_shift_binop(node, get_Shr_left(node), - get_Shr_right(node), new_rd_ia32_Shr); + ir_node *left = get_Shr_left(node); + ir_node *right = get_Shr_right(node); + + return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate); } @@ -1448,8 +1465,6 @@ static ir_node *gen_Shrs(ir_node *node) { ir_node *right = get_Shrs_right(node); ir_mode *mode = get_irn_mode(node); - assert(get_mode_size_bits(mode) == 32); - if(is_Const(right) && mode == mode_Is) { tarval *tv = get_Const_tarval(right); long val = get_tarval_long(tv); @@ -1497,7 +1512,7 @@ static ir_node *gen_Shrs(ir_node *node) { } } - return gen_shift_binop(node, left, right, new_rd_ia32_Sar); + return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate); } @@ -1509,10 +1524,8 @@ static ir_node *gen_Shrs(ir_node *node) { * @param op2 The second operator * @return The created ia32 RotL node */ -static ir_node *gen_RotL(ir_node *node, - ir_node *op1, ir_node *op2) { - assert(get_mode_size_bits(get_irn_mode(node)) == 32); - return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol); +static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { + return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate); } @@ -1526,10 +1539,8 @@ static ir_node *gen_RotL(ir_node *node, * @param op2 The second operator * @return The created ia32 RotR node */ -static ir_node *gen_RotR(ir_node *node, ir_node *op1, - ir_node *op2) { - assert(get_mode_size_bits(get_irn_mode(node)) == 32); - return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror); +static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { + return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate); } @@ -1590,36 +1601,38 @@ static ir_node *gen_Minus(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); ir_entity *ent; - ir_node *res; - int size; + ir_node *new_node; + int size; if (mode_is_float(mode)) { ir_node *new_op = be_transform_node(op); if (USE_SSE2(env_cg)) { + /* TODO: non-optimal... if we have many xXors, then we should + * rather create a load for the const and use that instead of + * several AM nodes... */ ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); ir_node *nomem = new_rd_NoMem(irg); - res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, - new_op, noreg_xmm); + new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, + nomem, new_op, noreg_xmm); size = get_mode_size_bits(mode); ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); - set_ia32_am_sc(res, ent); - set_ia32_op_type(res, ia32_AddrModeS); - set_ia32_ls_mode(res, mode); + set_ia32_am_sc(new_node, ent); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); } else { - res = new_rd_ia32_vfchs(dbgi, irg, block, new_op); + new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op); } } else { - op = ia32_skip_downconv(op); - res = gen_unop(node, op, new_rd_ia32_Neg); + new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } /** @@ -1633,8 +1646,7 @@ static ir_node *gen_Not(ir_node *node) { assert(get_irn_mode(node) != mode_b); /* should be lowered already */ assert (! mode_is_float(get_irn_mode(node))); - node = ia32_skip_downconv(node); - return gen_unop(node, op, new_rd_ia32_Not); + return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral); } @@ -1655,26 +1667,27 @@ static ir_node *gen_Abs(ir_node *node) ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg); ir_node *nomem = new_NoMem(); - ir_node *res; - int size; + ir_node *new_node; + int size; ir_entity *ent; if (mode_is_float(mode)) { if (USE_SSE2(env_cg)) { - res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp); + new_node = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, + nomem, new_op, noreg_fp); size = get_mode_size_bits(mode); ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - set_ia32_am_sc(res, ent); + set_ia32_am_sc(new_node, ent); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - set_ia32_op_type(res, ia32_AddrModeS); - set_ia32_ls_mode(res, mode); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); } else { - res = new_rd_ia32_vfabs(dbgi, irg, block, new_op); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_vfabs(dbgi, irg, block, new_op); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } } else { ir_node *xor; @@ -1682,20 +1695,21 @@ static ir_node *gen_Abs(ir_node *node) ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval); + assert(get_mode_size_bits(mode) == 32); + add_irn_dep(pval, get_irg_frame(irg)); - SET_IA32_ORIG_NODE(sign_extension, - ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node)); - xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op, - sign_extension); + xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, + new_op, sign_extension); SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node)); - res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor, - sign_extension); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, + xor, sign_extension); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } - return res; + return new_node; } /** @@ -1716,7 +1730,7 @@ static ir_node *gen_Load(ir_node *node) { ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_Load_mode(node); ir_mode *res_mode; - ir_node *new_op; + ir_node *new_node; ia32_address_t addr; /* construct load address */ @@ -1739,44 +1753,44 @@ static ir_node *gen_Load(ir_node *node) { if (mode_is_float(mode)) { if (USE_SSE2(env_cg)) { - new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem, - mode); + new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem, + mode); res_mode = mode_xmm; } else { - new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem, + new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem, mode); res_mode = mode_vfp; } } else { - if(mode == mode_b) - mode = mode_Iu; + assert(mode != mode_b); /* create a conv node with address mode for smaller modes */ if(get_mode_size_bits(mode) < 32) { - new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, - new_mem, noreg, mode); + new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, + new_mem, noreg, mode); } else { - new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem); + new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem); } res_mode = mode_Iu; } - set_irn_pinned(new_op, get_irn_pinned(node)); - set_ia32_op_type(new_op, ia32_AddrModeS); - set_ia32_ls_mode(new_op, mode); - set_address(new_op, &addr); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); + set_address(new_node, &addr); /* make sure we are scheduled behind the initial IncSP/Barrier * to avoid spills being placed before it */ if (block == get_irg_start_block(irg)) { - add_irn_dep(new_op, get_irg_frame(irg)); + add_irn_dep(new_node, get_irg_frame(irg)); } - set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + set_ia32_exc_label(new_node, + be_get_Proj_for_pn(node, pn_Load_X_except) != NULL); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return new_op; + return new_node; } static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, @@ -1816,19 +1830,24 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, ir_node *mem, ir_node *ptr, ir_mode *mode, construct_binop_dest_func *func, construct_binop_dest_func *func8bit, - int commutative) + match_flags_t flags) { - ir_node *src_block = get_nodes_block(node); - ir_node *block; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *src_block = get_nodes_block(node); + ir_node *block; + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_graph *irg = current_ir_graph; dbg_info *dbgi; - ir_node *new_node; - ir_node *new_op; + ir_node *new_node; + ir_node *new_op; + int commutative; ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; + ia32_address_t *addr = &am.addr; memset(&am, 0, sizeof(am)); + assert(flags & match_dest_am); + assert(flags & match_immediate); /* there is no destam node without... */ + commutative = (flags & match_commutative) != 0; + if(use_dest_am(src_block, op1, mem, ptr, op2)) { build_address(&am, op1); new_op = create_immediate_or_transform(op2, 0); @@ -1846,8 +1865,8 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, if(addr->mem == NULL) addr->mem = new_NoMem(); - dbgi = get_irn_dbg_info(node); - block = be_transform_node(src_block); + dbgi = get_irn_dbg_info(node); + block = be_transform_node(src_block); if(get_mode_size_bits(mode) == 8) { new_node = func8bit(dbgi, irg, block, addr->base, addr->index, addr->mem, new_op); @@ -1901,10 +1920,10 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, } static ir_node *try_create_dest_am(ir_node *node) { - ir_node *val = get_Store_value(node); - ir_node *mem = get_Store_mem(node); - ir_node *ptr = get_Store_ptr(node); - ir_mode *mode = get_irn_mode(val); + ir_node *val = get_Store_value(node); + ir_node *mem = get_Store_mem(node); + ir_node *ptr = get_Store_ptr(node); + ir_mode *mode = get_irn_mode(val); ir_node *op1; ir_node *op2; ir_node *new_node; @@ -1931,7 +1950,9 @@ static ir_node *try_create_dest_am(ir_node *node) { break; } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1); + new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Sub: op1 = get_Sub_left(val); @@ -1941,49 +1962,61 @@ static ir_node *try_create_dest_am(ir_node *node) { "found\n"); } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0); + new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, + match_dest_am | match_immediate | + match_immediate); break; case iro_And: op1 = get_And_left(val); op2 = get_And_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1); + new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Or: op1 = get_Or_left(val); op2 = get_Or_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1); + new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Eor: op1 = get_Eor_left(val); op2 = get_Eor_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1); + new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Shl: op1 = get_Shl_left(val); op2 = get_Shl_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0); + new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, + match_dest_am | match_immediate); break; case iro_Shr: op1 = get_Shr_left(val); op2 = get_Shr_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0); + new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, + match_dest_am | match_immediate); break; case iro_Shrs: op1 = get_Shrs_left(val); op2 = get_Shrs_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0); + new_rd_ia32_SarMem, new_rd_ia32_SarMem, + match_dest_am | match_immediate); break; case iro_Rot: op1 = get_Rot_left(val); op2 = get_Rot_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0); + new_rd_ia32_RolMem, new_rd_ia32_RolMem, + match_dest_am | match_immediate); break; /* TODO: match ROR patterns... */ case iro_Minus: @@ -2021,13 +2054,13 @@ static ir_node *gen_Store(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_irn_mode(val); - ir_node *new_op; + ir_node *new_node; ia32_address_t addr; /* check for destination address mode */ - new_op = try_create_dest_am(node); - if(new_op != NULL) - return new_op; + new_node = try_create_dest_am(node); + if(new_node != NULL) + return new_node; /* construct store address */ memset(&addr, 0, sizeof(addr)); @@ -2055,11 +2088,11 @@ static ir_node *gen_Store(ir_node *node) { } new_val = be_transform_node(val); if (USE_SSE2(env_cg)) { - new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem, - new_val); + new_node = new_rd_ia32_xStore(dbgi, irg, block, base, index, + new_mem, new_val); } else { - new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val, - mode); + new_node = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, + new_val, mode); } } else { new_val = create_immediate_or_transform(val, 0); @@ -2067,34 +2100,35 @@ static ir_node *gen_Store(ir_node *node) { mode = mode_Iu; if (get_mode_size_bits(mode) == 8) { - new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem, - new_val); + new_node = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, + new_mem, new_val); } else { - new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem, - new_val); + new_node = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem, + new_val); } } - set_irn_pinned(new_op, get_irn_pinned(node)); - set_ia32_op_type(new_op, ia32_AddrModeD); - set_ia32_ls_mode(new_op, mode); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode); - set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL); - set_address(new_op, &addr); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + set_ia32_exc_label(new_node, + be_get_Proj_for_pn(node, pn_Store_X_except) != NULL); + set_address(new_node, &addr); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return new_op; + return new_node; } static ir_node *create_Switch(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sel = get_Cond_selector(node); - ir_node *new_sel = be_transform_node(sel); - ir_node *res; - int switch_min = INT_MAX; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sel = get_Cond_selector(node); + ir_node *new_sel = be_transform_node(sel); + int switch_min = INT_MAX; + ir_node *new_node; const ir_edge_t *edge; assert(get_mode_size_bits(get_irn_mode(sel)) == 32); @@ -2118,11 +2152,11 @@ static ir_node *create_Switch(ir_node *node) SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node)); } - res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, get_Cond_defaultProj(node)); - - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, + get_Cond_defaultProj(node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) @@ -2164,8 +2198,8 @@ static ir_node *gen_Cond(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *sel = get_Cond_selector(node); ir_mode *sel_mode = get_irn_mode(sel); - ir_node *res; ir_node *flags = NULL; + ir_node *new_node; pn_Cmp pnc; if (sel_mode != mode_b) { @@ -2175,10 +2209,10 @@ static ir_node *gen_Cond(ir_node *node) { /* we get flags from a cmp */ flags = get_flags_node(sel, &pnc); - res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } @@ -2227,14 +2261,14 @@ static ir_node *gen_CopyB(ir_node *node) { static ir_node *gen_be_Copy(ir_node *node) { - ir_node *result = be_duplicate_node(node); - ir_mode *mode = get_irn_mode(result); + ir_node *new_node = be_duplicate_node(node); + ir_mode *mode = get_irn_mode(new_node); if (mode_needs_gp_reg(mode)) { - set_irn_mode(result, mode_Iu); + set_irn_mode(new_node, mode_Iu); } - return result; + return new_node; } /** @@ -2267,7 +2301,7 @@ static ir_node *try_create_Test(ir_node *node) ir_mode *mode; ir_node *left; ir_node *right; - ir_node *res; + ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; int cmp_unsigned; @@ -2293,26 +2327,29 @@ static ir_node *try_create_Test(ir_node *node) assert(get_mode_size_bits(mode) <= 32); match_arguments(&am, block, left, right, match_commutative | - match_8_bit_am | match_16_bit_am | match_am_and_immediates); + match_am | match_8bit_am | match_16bit_am | + match_am_and_immediates | match_immediate | + match_8bit | match_16bit); cmp_unsigned = !mode_is_signed(mode); if(get_mode_size_bits(mode) == 8) { - res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, cmp_unsigned); + new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, + cmp_unsigned); } else { - res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, - am.ins_permuted, cmp_unsigned); + new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, cmp_unsigned); } - set_am_attributes(res, &am); + set_am_attributes(new_node, &am); assert(mode != NULL); - set_ia32_ls_mode(res, mode); + set_ia32_ls_mode(new_node, mode); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - res = fix_mem_proj(res, &am); - return res; + new_node = fix_mem_proj(new_node, &am); + return new_node; } static ir_node *create_Fucom(ir_node *node) @@ -2325,31 +2362,33 @@ static ir_node *create_Fucom(ir_node *node) ir_node *new_left = be_transform_node(left); ir_node *right = get_Cmp_right(node); ir_node *new_right; - ir_node *res; + ir_node *new_node; if(transform_config.use_fucomi) { new_right = be_transform_node(right); - res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0); - set_ia32_commutative(res); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, + new_right, 0); + set_ia32_commutative(new_node); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } else { if(transform_config.use_ftst && is_Const_null(right)) { - res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0); + new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, + 0); } else { new_right = be_transform_node(right); - res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, + new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right, 0); } - set_ia32_commutative(res); + set_ia32_commutative(new_node); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - res = new_rd_ia32_Sahf(dbgi, irg, new_block, res); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } - return res; + return new_node; } static ir_node *create_Ucomi(ir_node *node) @@ -2364,7 +2403,7 @@ static ir_node *create_Ucomi(ir_node *node) ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, left, right, match_commutative); + match_arguments(&am, src_block, left, right, match_commutative | match_am); new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, @@ -2387,7 +2426,7 @@ static ir_node *gen_Cmp(ir_node *node) ir_node *left = get_Cmp_left(node); ir_node *right = get_Cmp_right(node); ir_mode *cmp_mode = get_irn_mode(left); - ir_node *res; + ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; int cmp_unsigned; @@ -2406,34 +2445,36 @@ static ir_node *gen_Cmp(ir_node *node) * we can use SourceAM */ if(!ia32_use_source_address_mode(block, left, right) && !ia32_use_source_address_mode(block, right, left)) { - res = try_create_Test(node); - if(res != NULL) - return res; + new_node = try_create_Test(node); + if(new_node != NULL) + return new_node; } - match_arguments(&am, block, left, right, - match_commutative | match_8_bit_am | match_16_bit_am | - match_am_and_immediates); + match_arguments(&am, block, left, right, match_commutative | + match_am | match_8bit_am | match_16bit_am | + match_immediate | match_am_and_immediates | + match_8bit | match_16bit); cmp_unsigned = !mode_is_signed(get_irn_mode(left)); if(get_mode_size_bits(cmp_mode) == 8) { - res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, - am.ins_permuted, cmp_unsigned); + new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, + cmp_unsigned); } else { - res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, - am.ins_permuted, cmp_unsigned); + new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, cmp_unsigned); } - set_am_attributes(res, &am); + set_am_attributes(new_node, &am); assert(cmp_mode != NULL); - set_ia32_ls_mode(res, cmp_mode); + set_ia32_ls_mode(new_node, cmp_mode); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - res = fix_mem_proj(res, &am); + new_node = fix_mem_proj(new_node, &am); - return res; + return new_node; } static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc) @@ -2454,8 +2495,8 @@ static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc) addr = &am.addr; - match_flags = match_commutative | match_no_immediate | match_16_bit_am - | match_force_32bit_op; + match_flags = match_commutative | match_am | match_16bit_am | + match_mode_neutral; match_arguments(&am, block, val_false, val_true, match_flags); @@ -2480,16 +2521,16 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, ir_graph *irg = current_ir_graph; ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *nomem = new_NoMem(); - ir_node *res; + ir_node *new_node; - res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node)); - res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, - nomem, res, mode_Bu); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node)); + new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); + new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, + nomem, new_node, mode_Bu); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); (void) orig_node; - return res; + return new_node; } /** @@ -2506,7 +2547,7 @@ static ir_node *gen_Psi(ir_node *node) ir_node *psi_default = get_Psi_default(node); ir_node *cond = get_Psi_cond(node, 0); ir_node *flags = NULL; - ir_node *res; + ir_node *new_node; pn_Cmp pnc; assert(get_Psi_n_conds(node) == 1); @@ -2516,13 +2557,13 @@ static ir_node *gen_Psi(ir_node *node) flags = get_flags_node(cond, &pnc); if(is_Const_1(psi_true) && is_Const_0(psi_default)) { - res = create_set_32bit(dbgi, new_block, flags, pnc, node, 0); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0); } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { - res = create_set_32bit(dbgi, new_block, flags, pnc, node, 1); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1); } else { - res = create_CMov(node, flags, pnc); + new_node = create_CMov(node, flags, pnc); } - return res; + return new_node; } @@ -2590,7 +2631,7 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) ir_node *nomem = new_NoMem(); ir_node *frame = get_irg_frame(irg); ir_node *store, *load; - ir_node *res; + ir_node *new_node; store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node, tgt_mode); @@ -2604,8 +2645,8 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); - res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); - return res; + new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); + return new_node; } static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) @@ -2623,41 +2664,43 @@ static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long va * Create a conversion from general purpose to x87 register */ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { - ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *op = get_Conv_op(node); - ir_node *new_op; + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *op = get_Conv_op(node); + ir_node *new_op = NULL; ir_node *noreg; ir_node *nomem; ir_mode *mode; ir_mode *store_mode; ir_node *fild; ir_node *store; - ir_node *res; + ir_node *new_node; int src_bits; /* fild can use source AM if the operand is a signed 32bit integer */ if (src_mode == mode_Is) { ia32_address_mode_t am; - match_arguments(&am, src_block, NULL, op, match_no_immediate); + match_arguments(&am, src_block, NULL, op, match_am | match_try_am); if (am.op_type == ia32_AddrModeS) { ia32_address_t *addr = &am.addr; - fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem); - res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, + addr->index, addr->mem); + new_node = new_r_Proj(irg, block, fild, mode_vfp, + pn_ia32_vfild_res); set_am_attributes(fild, &am); SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node)); fix_mem_proj(fild, &am); - return res; + return new_node; } - new_op = am.new_op2; - } else { + } + if(new_op == NULL) { new_op = be_transform_node(op); } @@ -2720,9 +2763,9 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_ls_mode(fild, store_mode); - res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); - return res; + return new_node; } /** @@ -2736,7 +2779,7 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); ir_node *new_block = be_transform_node(block); - ir_node *res; + ir_node *new_node; ir_mode *smaller_mode; int smaller_bits; ia32_address_mode_t am; @@ -2750,21 +2793,31 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, smaller_bits = tgt_bits; } - match_arguments(&am, block, NULL, op, match_8_bit_am | match_16_bit_am); - if (smaller_bits == 8 && am.op_type == ia32_Normal) { - res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - smaller_mode); +#ifdef DEBUG_libfirm + if(is_Const(op)) { + ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n", + op); + } +#endif + + match_arguments(&am, block, NULL, op, + match_8bit | match_16bit | match_8bit_am | match_16bit_am); + if (smaller_bits == 8) { + new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + smaller_mode); } else { - res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - smaller_mode); + new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + smaller_mode); } - set_am_attributes(res, &am); - set_ia32_ls_mode(res, smaller_mode); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - res = fix_mem_proj(res, &am); - return res; + set_am_attributes(new_node, &am); + /* match_arguments assume that out-mode = in-mode, this isn't true here + * so fix it */ + set_ia32_ls_mode(new_node, smaller_mode); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = fix_mem_proj(new_node, &am); + return new_node; } /** @@ -2921,7 +2974,7 @@ static ir_node *try_create_Immediate(ir_node *node, ir_mode *mode; ir_node *cnst = NULL; ir_node *symconst = NULL; - ir_node *res; + ir_node *new_node; mode = get_irn_mode(node); if(!mode_is_int(mode) && !mode_is_reference(mode)) { @@ -3007,9 +3060,9 @@ static ir_node *try_create_Immediate(ir_node *node, offset = tarval_neg(offset); } - res = create_Immediate(symconst_ent, symconst_sign, val); + new_node = create_Immediate(symconst_ent, symconst_sign, val); - return res; + return new_node; } static ir_node *create_immediate_or_transform(ir_node *node, @@ -3327,7 +3380,7 @@ static ir_node *gen_ASM(ir_node *node) ir_node *new_block = be_transform_node(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node **in; - ir_node *res; + ir_node *new_node; int out_arity; int n_out_constraints; int n_clobbers; @@ -3441,15 +3494,15 @@ static ir_node *gen_ASM(ir_node *node) in[i] = transformed; } - res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity, - get_ASM_text(node), register_map); + new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity, + get_ASM_text(node), register_map); - set_ia32_out_req_all(res, out_reg_reqs); - set_ia32_in_req_all(res, in_reg_reqs); + set_ia32_out_req_all(new_node, out_reg_reqs); + set_ia32_in_req_all(new_node, in_reg_reqs); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } /******************************************** @@ -3472,15 +3525,15 @@ static ir_node *gen_be_FrameAddr(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *res; + ir_node *new_node; - res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); - set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node)); - set_ia32_use_frame(res); + new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); + set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node)); + set_ia32_use_frame(new_node); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } /** @@ -3590,30 +3643,10 @@ static ir_node *gen_be_Return(ir_node *node) { */ static ir_node *gen_be_AddSP(ir_node *node) { - ir_node *src_block = get_nodes_block(node); - ir_node *new_block = be_transform_node(src_block); - ir_node *sz = get_irn_n(node, be_pos_AddSP_size); - ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - match_flags_t flags = 0; - - match_arguments(&am, src_block, sp, sz, flags); + ir_node *sz = get_irn_n(node, be_pos_AddSP_size); + ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2); - set_am_attributes(new_node, &am); - /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - new_node = fix_mem_proj(new_node, &am); - - return new_node; + return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am); } /** @@ -3621,30 +3654,10 @@ static ir_node *gen_be_AddSP(ir_node *node) */ static ir_node *gen_be_SubSP(ir_node *node) { - ir_node *src_block = get_nodes_block(node); - ir_node *new_block = be_transform_node(src_block); - ir_node *sz = get_irn_n(node, be_pos_SubSP_size); - ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - match_flags_t flags = 0; - - match_arguments(&am, src_block, sp, sz, flags); - - new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2); - set_am_attributes(new_node, &am); - /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - new_node = fix_mem_proj(new_node, &am); + ir_node *sz = get_irn_n(node, be_pos_SubSP_size); + ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - return new_node; + return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am); } /** @@ -3668,9 +3681,8 @@ static ir_node *gen_Unknown(ir_node *node) { } else if (mode_needs_gp_reg(mode)) { return ia32_new_Unknown_gp(env_cg); } else { - assert(0 && "unsupported Unknown-Mode"); + panic("unsupported Unknown-Mode"); } - return NULL; } @@ -3723,11 +3735,12 @@ static ir_node *gen_IJmp(ir_node *node) ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_flags_t flags; - flags = match_force_32bit_op | match_no_immediate; + assert(get_irn_mode(op) == mode_P); - match_arguments(&am, block, NULL, op, flags); + match_arguments(&am, block, NULL, op, + match_am | match_8bit_am | match_16bit_am | + match_immediate | match_8bit | match_16bit); new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op2); @@ -3827,27 +3840,37 @@ static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func) return new_op; } +static ir_node *gen_ia32_l_ShlDep(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left); + ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right); -/** - * Transforms an ia32_l_XXX into a "real" XXX node - * - * @param node The node to transform - * @return the created ia32 XXX node - */ -#define GEN_LOWERED_SHIFT_OP(l_op, op) \ - static ir_node *gen_ia32_##l_op(ir_node *node) { \ - return gen_shift_binop(node, get_irn_n(node, 0), \ - get_irn_n(node, 1), new_rd_ia32_##op); \ - } + return gen_shift_binop(node, left, right, new_rd_ia32_Shl, + match_immediate | match_mode_neutral); +} -GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl) -GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr) -GEN_LOWERED_SHIFT_OP(l_SarDep, Sar) +static ir_node *gen_ia32_l_ShrDep(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left); + ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right); + return gen_shift_binop(node, left, right, new_rd_ia32_Shr, + match_immediate); +} + +static ir_node *gen_ia32_l_SarDep(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left); + ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right); + return gen_shift_binop(node, left, right, new_rd_ia32_Sar, + match_immediate); +} static ir_node *gen_ia32_l_Add(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_Add_left); ir_node *right = get_irn_n(node, n_ia32_l_Add_right); - ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative); + ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, + match_commutative | match_am | match_immediate | + match_mode_neutral); if(is_Proj(lowered)) { lowered = get_Proj_pred(lowered); @@ -3861,17 +3884,9 @@ static ir_node *gen_ia32_l_Add(ir_node *node) { static ir_node *gen_ia32_l_Adc(ir_node *node) { - return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative); -} - -/** - * Transforms an ia32_l_Neg into a "real" ia32_Neg node - * - * @param node The node to transform - * @return the created ia32 Neg node - */ -static ir_node *gen_ia32_l_Neg(ir_node *node) { - return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg); + return gen_binop_flags(node, new_rd_ia32_Adc, + match_commutative | match_am | match_immediate | + match_mode_neutral); } /** @@ -3952,7 +3967,7 @@ static ir_node *gen_ia32_l_Mul(ir_node *node) { ir_node *right = get_binop_right(node); return gen_binop(node, left, right, new_rd_ia32_Mul, - match_commutative | match_no_immediate); + match_commutative | match_am | match_mode_neutral); } /** @@ -3965,13 +3980,14 @@ static ir_node *gen_ia32_l_IMul(ir_node *node) { ir_node *right = get_binop_right(node); return gen_binop(node, left, right, new_rd_ia32_IMul1OP, - match_commutative | match_no_immediate); + match_commutative | match_am | match_mode_neutral); } static ir_node *gen_ia32_l_Sub(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_Sub_left); ir_node *right = get_irn_n(node, n_ia32_l_Sub_right); - ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0); + ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, + match_am | match_immediate | match_mode_neutral); if(is_Proj(lowered)) { lowered = get_Proj_pred(lowered); @@ -3984,7 +4000,8 @@ static ir_node *gen_ia32_l_Sub(ir_node *node) { } static ir_node *gen_ia32_l_Sbb(ir_node *node) { - return gen_binop_flags(node, new_rd_ia32_Sbb, 0); + return gen_binop_flags(node, new_rd_ia32_Sbb, + match_am | match_immediate | match_mode_neutral); } /** @@ -3994,37 +4011,52 @@ static ir_node *gen_ia32_l_Sbb(ir_node *node) { * op3 - shift count * Only op3 can be an immediate. */ -static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1, - ir_node *op2, ir_node *count) +static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, + ir_node *low, ir_node *count) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = NULL; + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_op1 = be_transform_node(op1); - ir_node *new_op2 = be_transform_node(op2); - ir_node *new_count = create_immediate_or_transform(count, 'I'); - - /* TODO proper AM support */ + ir_node *new_high = be_transform_node(high); + ir_node *new_low = be_transform_node(low); + ir_node *new_count; + ir_node *new_node; - if (is_ia32_l_ShlD(node)) - new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count); - else - new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count); + /* the shift amount can be any mode that is bigger than 5 bits, since all + * other bits are ignored anyway */ + while (is_Conv(count) && get_irn_n_edges(count) == 1) { + assert(get_mode_size_bits(get_irn_mode(count)) >= 5); + count = get_Conv_op(count); + } + new_count = create_immediate_or_transform(count, 0); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + if (is_ia32_l_ShlD(node)) { + new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low, + new_count); + } else { + new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low, + new_count); + } + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return new_op; + return new_node; } -static ir_node *gen_ia32_l_ShlD(ir_node *node) { - return gen_lowered_64bit_shifts(node, get_irn_n(node, 0), - get_irn_n(node, 1), get_irn_n(node, 2)); +static ir_node *gen_ia32_l_ShlD(ir_node *node) +{ + ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high); + ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low); + ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count); + return gen_lowered_64bit_shifts(node, high, low, count); } -static ir_node *gen_ia32_l_ShrD(ir_node *node) { - return gen_lowered_64bit_shifts(node, get_irn_n(node, 0), - get_irn_n(node, 1), get_irn_n(node, 2)); +static ir_node *gen_ia32_l_ShrD(ir_node *node) +{ + ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high); + ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low); + ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count); + return gen_lowered_64bit_shifts(node, high, low, count); } /** @@ -4647,7 +4679,6 @@ static void register_transformers(void) /* transform ops from intrinsic lowering */ GEN(ia32_l_Add); GEN(ia32_l_Adc); - GEN(ia32_l_Neg); GEN(ia32_l_Mul); GEN(ia32_l_IMul); GEN(ia32_l_ShlDep); @@ -4814,7 +4845,7 @@ void ia32_transform_graph(ia32_code_gen_t *cg) { initial_fpcw = NULL; heights = heights_new(irg); - calculate_non_address_mode_nodes(irg); + ia32_calculate_non_address_mode_nodes(irg); /* the transform phase is not safe for CSE (yet) because several nodes get * attributes set after their creation */ @@ -4825,7 +4856,7 @@ void ia32_transform_graph(ia32_code_gen_t *cg) { set_opt_cse(cse_last); - free_non_address_mode_nodes(); + ia32_free_non_address_mode_nodes(); heights_free(heights); heights = NULL; } diff --git a/ir/be/mips/mips_new_nodes.c b/ir/be/mips/mips_new_nodes.c index c390794d7..734efb329 100644 --- a/ir/be/mips/mips_new_nodes.c +++ b/ir/be/mips/mips_new_nodes.c @@ -393,13 +393,12 @@ static void init_mips_attributes(ir_node *node, arch_irn_flags_t flags, const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) + int n_res) { ir_graph *irg = get_irn_irg(node); struct obstack *obst = get_irg_obstack(irg); mips_attr_t *attr = get_mips_attr(node); (void) execution_units; - (void) latency; attr->flags = flags; attr->out_req = out_reqs; diff --git a/ir/be/mips/mips_spec.pl b/ir/be/mips/mips_spec.pl index 18460e173..bbb1e509a 100644 --- a/ir/be/mips/mips_spec.pl +++ b/ir/be/mips/mips_spec.pl @@ -148,12 +148,12 @@ $default_copy_attr = "mips_copy_attr"; $mode_gp = "mode_Iu"; %init_attr = ( - mips_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + mips_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", - mips_immediate_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + mips_immediate_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_mips_immediate_attributes(res, imm_type, entity, val);", - mips_load_store_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + mips_load_store_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_mips_load_store_attributes(res, entity, offset);", ); diff --git a/ir/be/ppc32/ppc32_new_nodes.c b/ir/be/ppc32/ppc32_new_nodes.c index c2235083a..0ea410c15 100644 --- a/ir/be/ppc32/ppc32_new_nodes.c +++ b/ir/be/ppc32/ppc32_new_nodes.c @@ -496,12 +496,11 @@ ppc32_attr_offset_mode get_ppc32_offset_mode(const ir_node *node) { void init_ppc32_attributes(ir_node *node, int flags, const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs, const be_execution_unit_t ***execution_units, - int n_res, unsigned latency) { + int n_res) { ir_graph *irg = get_irn_irg(node); struct obstack *obst = get_irg_obstack(irg); ppc32_attr_t *attr = get_ppc32_attr(node); (void) execution_units; - (void) latency; attr->flags = flags; attr->in_req = in_reqs; diff --git a/ir/be/ppc32/ppc32_new_nodes.h b/ir/be/ppc32/ppc32_new_nodes.h index d57c877aa..affbccc77 100644 --- a/ir/be/ppc32/ppc32_new_nodes.h +++ b/ir/be/ppc32/ppc32_new_nodes.h @@ -132,11 +132,6 @@ int get_ppc32_offset(const ir_node *node); void set_ppc32_offset_mode(const ir_node *node, ppc32_attr_offset_mode mode); ppc32_attr_offset_mode get_ppc32_offset_mode(const ir_node *node); -void init_ppc32_attributes(ir_node *node, int flags, - const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs, - const be_execution_unit_t ***execution_units, - int n_res, unsigned latency); - void ppc32_register_additional_opcodes(int opcode_num); /* Include the generated headers */ diff --git a/ir/be/scripts/generate_new_opcodes.pl b/ir/be/scripts/generate_new_opcodes.pl index a838609b4..54ccdc3c0 100755 --- a/ir/be/scripts/generate_new_opcodes.pl +++ b/ir/be/scripts/generate_new_opcodes.pl @@ -39,6 +39,7 @@ our $additional_opcodes; our %nodes; our %operands; our %cpu; +our $default_op_attr_type; our $default_attr_type; our $default_cmp_attr; our $default_copy_attr; @@ -68,7 +69,7 @@ if(!defined($default_attr_type)) { } if(!defined(%init_attr)) { %init_attr = ( - "$default_attr_type" => "\tinit_${arch}_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + "$default_attr_type" => "\tinit_${arch}_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", ); } if(!defined($default_cmp_attr)) { @@ -376,12 +377,6 @@ foreach my $op (keys(%nodes)) { $temp .= "\tint n_res = ${out_arity};\n"; } - my $latency = $n{"latency"}; - if (!defined($latency)) { - $latency = 1; - } - $temp .= "\tunsigned latency = ${latency};\n"; - if (defined($known_mode)) { $temp .= "\tir_mode *mode = ${known_mode};\n"; } @@ -513,29 +508,32 @@ foreach my $op (keys(%nodes)) { $temp .= "\n"; # set flags for outs - if ($#out_flags >= 0) { - $temp .= "\t/* set flags for outs */\n"; - for (my $idx = 0; $idx <= $#out_flags; $idx++) { - my $flags = ""; - my $prefix = ""; - - foreach my $flag (split(/\|/, $out_flags[$idx])) { - if ($flag eq "I") { - $flags .= $prefix."arch_irn_flags_ignore"; - $prefix = " | "; + if (exists($n{"outs"})) { + undef my @outs; + @outs = @{ $n{"outs"} }; + + for (my $idx = 0; $idx <= $#outs; $idx++) { + # check, if we have additional flags annotated to out + if ($outs[$idx] =~ /:((S|I)(\|(S|I))*)/) { + my $flag_string = $1; + my $prefix = ""; + my $flags = ""; + + foreach my $flag (split(/\|/, $flag_string)) { + if ($flag eq "I") { + $flags .= $prefix."arch_irn_flags_ignore"; + $prefix = " | "; + } elsif ($flag eq "S") { + $flags .= $prefix."arch_irn_flags_modify_sp"; + $prefix = " | "; + } } - elsif ($flag eq "S") { - $flags .= $prefix."arch_irn_flags_modify_sp"; - $prefix = " | "; - } - } - $temp .= "\tset_$arch\_out_flags(res, $flags, $idx);\n"; + $temp .= "\tset_$arch\_out_flags(res, $flags, $idx);\n"; + } } - $temp .= "\n"; } - if (exists($n{"init_attr"})) { $temp .= "\tattr = get_irn_generic_attr(res);\n"; $temp .= "\t".$n{"init_attr"}."\n"; @@ -586,6 +584,15 @@ foreach my $op (keys(%nodes)) { $temp .= "|M, ".translate_arity($arity).", 0, sizeof(${attr_type}), &ops);\n"; push(@obst_new_irop, $temp); push(@obst_new_irop, "\tset_op_tag(op_$op, &$arch\_op_tag);\n"); + if(defined($default_op_attr_type)) { + push(@obst_new_irop, "\tattr = ($default_op_attr_type *) xmalloc(sizeof(attr[0]));\n"); + push(@obst_new_irop, "\tmemset(attr, 0, sizeof(attr[0]));\n"); + if(defined($n{op_attr_init})) { + push(@obst_new_irop, "\t".$n{op_attr_init}."\n"); + } + push(@obst_new_irop, "\tset_op_attr(op_$op, attr);\n"); + } + push(@obst_enum_op, "\tiro_$op,\n"); push(@obst_header, "\n"); @@ -706,6 +713,13 @@ void $arch\_create_opcodes(void) { ir_op_ops ops; int cur_opcode; static int run_once = 0; +ENDOFMAIN + + if(defined($default_op_attr_type)) { + print OUT "\t$default_op_attr_type *attr;\n"; + } + +print OUT<tag; } +static INLINE void _set_op_attr(ir_op *op, void *attr) { + op->attr = attr; +} + +static INLINE void *_get_op_attr(const ir_op *op) { + return op->attr; +} + #define get_op_code(op) _get_op_code(op) #define get_op_ident(op) _get_op_ident(op) #define get_op_pinned(op) _get_op_pinned(op) #define get_op_ops(op) _get_op_ops(op) #define set_op_tag(op, tag) _set_op_tag((op), (tag)) #define get_op_tag(op) _get_op_tag(op) +#define set_op_attr(op, attr) _set_op_attr((op), (attr)) +#define get_op_attr(op) _get_op_attr(op) #endif diff --git a/ir/ir/iropt.c b/ir/ir/iropt.c index e02a230d1..dbc28a136 100644 --- a/ir/ir/iropt.c +++ b/ir/ir/iropt.c @@ -2911,6 +2911,7 @@ static ir_node *transform_bitwise_distributive(ir_node *n, set_irn_n(n, -1, blk); set_binop_left(n, new_n); set_binop_right(n, c); + add_identities(current_ir_graph->value_table, n); } DBG_OPT_ALGSIM1(oldn, a, b, n, FS_OPT_SHIFT_AND); diff --git a/ir/ir/irtypes.h b/ir/ir/irtypes.h index 28b80ae53..cfb741d77 100644 --- a/ir/ir/irtypes.h +++ b/ir/ir/irtypes.h @@ -53,6 +53,7 @@ struct ir_op { int op_index; /**< The index of the first data operand, 0 for most cases, 1 for Div etc. */ unsigned flags; /**< Flags describing the behavior of the ir_op, a bitmasks of irop_flags. */ void *tag; /**< Some custom pointer the op's creator can attach stuff to. */ + void *attr; /**< custom pointer where op's creator can attach attribute stuff to. */ ir_op_ops ops; /**< The operations of the this op. */ }; @@ -345,8 +346,8 @@ struct ir_node { struct dbg_info *dbi; /**< A pointer to information for debug support. */ /* ------- For debugging ------- */ #ifdef DEBUG_libfirm - unsigned flags; - int out_valid; + unsigned out_valid : 1; + unsigned flags : 31; long node_nr; /**< A unique node number for each node to make output readable. */ #endif -- 2.20.1