From 1d49671a1d3947d4403fc065a737149b760056e0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Christian=20W=C3=BCrdig?= Date: Fri, 18 Nov 2005 09:58:14 +0000 Subject: [PATCH] fixed missing files --- ir/be/ia32/Makefile.in | 10 +- ir/be/ia32/emitter.c | 100 ++++++++++ ir/be/ia32/emitter.h | 14 ++ ir/be/ia32/ia32_spec.pl | 426 ++++++++++++++++++++++++++-------------- 4 files changed, 397 insertions(+), 153 deletions(-) create mode 100644 ir/be/ia32/emitter.c create mode 100644 ir/be/ia32/emitter.h diff --git a/ir/be/ia32/Makefile.in b/ir/be/ia32/Makefile.in index ce836060b..585a44aed 100644 --- a/ir/be/ia32/Makefile.in +++ b/ir/be/ia32/Makefile.in @@ -17,7 +17,10 @@ subdir := ir/be/ia32 full_dir = $(top_srcdir)/ir/be full_dirbe = $(full_dir)/$(FIRMBE_ARCH) -SOURCES = Makefile.in new_nodes.c new_nodes.h emitter_gen.c emitter_gen.h transform.c transform.h gen_decls.c gen_decls.h emitter.c emitter.h +SOURCES = Makefile.in new_nodes.c new_nodes.h new_nodes.c.inl new_nodes.h.inl \ + emitter_gen.c emitter_gen.h emitter.c emitter.h \ + regalloc_if.c regalloc_if.h regalloc_if_gen.inl \ + transform.c transform.h gen_decls.c gen_decls.h include $(topdir)/MakeRules @@ -29,10 +32,13 @@ CPPFLAGS += -I$(top_srcdir)/ir/adt -I$(top_srcdir)/ir/ir -I$(top_srcdir)/ir/ include $(top_srcdir)/MakeTargets -$(full_dirbe)/new_nodes.c $(full_dirbe)/new_nodes.h: $(full_dir)/scripts/generate_new_opcodes.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl dump_support.inl +$(full_dirbe)/new_nodes.c.inl $(full_dirbe)/new_nodes.h.inl: $(full_dir)/scripts/generate_new_opcodes.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl $(full_dir)/scripts/generate_new_opcodes.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl $(full_dirbe) $(full_dirbe)/emitter_gen.c $(full_dirbe)/emitter_gen.h: $(full_dir)/scripts/generate_emitter.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl emitter.c emitter.h $(full_dir)/scripts/generate_emitter.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl $(full_dirbe) +$(full_dirbe)/regalloc_if_gen.inl: $(full_dir)/scripts/generate_regalloc_if.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl + $(full_dir)/scripts/generate_regalloc_if.pl $(full_dirbe)/$(FIRMBE_ARCH)_spec.pl $(full_dirbe) + all: subdir.o diff --git a/ir/be/ia32/emitter.c b/ir/be/ia32/emitter.c new file mode 100644 index 000000000..d0040c67f --- /dev/null +++ b/ir/be/ia32/emitter.c @@ -0,0 +1,100 @@ +#include "iredges.h" +#include "emitter.h" + +char *get_dest_reg_name(ir_node *n, int num) { +} + +char *get_source_reg_name(ir_node *n, int num) { +} + +char *node_const_to_str(ir_node *n) { +} + +char *node_offset_to_str(ir_node *n) { +} + +void equalize_dest_src(ir_node *n) { + if (get_dest_reg(n, 1) != get_source_reg(n, 1)) + fprintf("\tmovl %%%s, %%%s\t\t\t/* src -> dest for 2 address code */\n", get_source_reg_name(n, 1), get_dest_reg_name(n, 1)); +} + +/* + * coding of conditions + */ +struct cmp2conditon_t { + const char *name; + pn_Cmp num; +}; + +/* + * positive conditions for signed compares + */ +static const struct cmp2conditon_t cmp2condition_s[] = { + { NULL, pn_Cmp_False }, /* always false */ + { "e", pn_Cmp_Eq }, /* == */ + { "l", pn_Cmp_Lt }, /* < */ + { "le", pn_Cmp_Le }, /* <= */ + { "g", pn_Cmp_Gt }, /* > */ + { "ge", pn_Cmp_Ge }, /* >= */ + { "ne", pn_Cmp_Lg }, /* != */ + { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */ + { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */ + { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */ + { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */ + { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */ + { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */ + { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */ + { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */ + { NULL, pn_Cmp_True }, /* always true */ +}; + +/* + * positive conditions for unsigned compares + */ +static const struct cmp2conditon_t cmp2condition_u[] = { + { NULL, pn_Cmp_False }, /* always false */ + { "e", pn_Cmp_Eq }, /* == */ + { "b", pn_Cmp_Lt }, /* < */ + { "be", pn_Cmp_Le }, /* <= */ + { "a", pn_Cmp_Gt }, /* > */ + { "ae", pn_Cmp_Ge }, /* >= */ + { "ne", pn_Cmp_Lg }, /* != */ + { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */ + { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */ + { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */ + { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */ + { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */ + { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */ + { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */ + { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */ + { NULL, pn_Cmp_True }, /* always true */ +}; + +/* + * returns the condition code + */ +const char *get_cmp_suffix(int cmp_code, int unsigned_cmp) +{ + assert(cmp2condition_s[cmp_code].num == cmp_code); + assert(cmp2condition_u[cmp_code].num == cmp_code); + + return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name; +} + +void emit_ia32_Proj_Cond(FILE *F, ir_node *n, ir_node *cond) { + ir_node *succ_block = get_irn_out_edges_first(n); + ir_node *sel = get_Cond_selector(cond); + ir_mode *sel_mode = get_irn_mode(sel); + + assert(succ_block && "Target block of Proj_Cond missing!"); + + if (sel_mode == mode_b) { // Boolean condition + int label = get_irn_node_nr(succ_block); + int nr = get_Proj_proj(n); + fprintf(F, "j%s%s Label%d\t\t\t/* if (%sCond) goto Label */\n", + nr == pn_Cond_true ? "" : "n", + get_cmp_suffix(get_Proj_proj(sel), mode_is_signed(cmp mode)), + label, + nr == pn_Cond_true ? "" : "!"); + } +} diff --git a/ir/be/ia32/emitter.h b/ir/be/ia32/emitter.h new file mode 100644 index 000000000..afd6220e2 --- /dev/null +++ b/ir/be/ia32/emitter.h @@ -0,0 +1,14 @@ +#ifndef _EMITTER_H_ +#define _EMITTER_H_ + +#include "irnode.h" + +char *get_dest_reg(ir_node *n, int num); + +char *get_source_reg(ir_node *n, int num); + +char *node_const_to_str(ir_node *n); + +char *node_offset_to_str(ir_node *n); + +#endif /* _EMITTER_H_ */ diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index ac451a992..f9065fece 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -72,6 +72,31 @@ $arch = "ia32"; # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 +%reg_classes = ( + "general_purpose" => [ + { "name" => "eax", "type" => 0 }, + { "name" => "ebx", "type" => 0 }, + { "name" => "ecx", "type" => 0 }, + { "name" => "edx", "type" => 0 }, + { "name" => "edi", "type" => 0 }, + { "name" => "esi", "type" => 0 }, + { "name" => "ebp", "type" => 0 } + ], + "floating_point" => [ + { "name" => "xmm0", "type" => 0 }, + { "name" => "xmm1", "type" => 0 }, + { "name" => "xmm2", "type" => 0 }, + { "name" => "xmm3", "type" => 0 }, + { "name" => "xmm4", "type" => 0 }, + { "name" => "xmm5", "type" => 0 }, + { "name" => "xmm6", "type" => 0 }, + { "name" => "xmm7", "type" => 0 }, + ], + "flag_register" => [ + { "name" => "eflags", "type" => 0 } + ] +); # %reg_classes + #--------------------------------------------------# # _ # # (_) # @@ -90,23 +115,30 @@ $arch = "ia32"; # commutative operations "Add" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", - "emit" => '. addl %s2, %d1\t\t\t/* Add(%s1, %s2) -> %d1 */' + "op_flags" => "C", + "arity" => 2, + "remat" => 1, + "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. addl %s2, %d1\t\t\t/* Add(%s1, %s2) -> %d1 */' }, "Add_i" => { - "arity" => 1, - "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const", - "emit" => '. addl %c, %d1\t\t\t/* Add(%c, %s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. addl %c, %d1\t\t\t/* Add(%c, %s1) -> %d1 */' }, "Mul" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", - "emit" => + "op_flags" => "C", + "arity" => 2, + "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", + "reg_req" => { "in" => [ "eax", "general_purpose" ], "out" => [ "eax" ] }, + "emit" => ' if (mode_is_signed(get_irn_mode(n))) { 4. imull %s2\t\t\t/* signed Mul(%s1, %s2) -> %d1 */ } @@ -117,10 +149,12 @@ $arch = "ia32"; }, "Mul_i" => { - "state" => "pinned", - "arity" => 1, - "comment" => "construct Mul: Mul(a, const) = Mul(const, a) = a * const", - "emit" => + "state" => "pinned", + "arity" => 1, + "comment" => "construct Mul: Mul(a, const) = Mul(const, a) = a * const", +# "reg_req" => { "in" => [ "eax" ], "out" => [ "eax" ] }, + "reg_req" => { "in" => [ "!eax" ], "out" => [ "eax" ] }, + "emit" => ' if (mode_is_signed(get_irn_mode(n))) { 4. imull %c\t\t\t/* signed Mul(%c, %s1) -> %d1 */ } @@ -131,10 +165,11 @@ $arch = "ia32"; }, "Mulh" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Mulh: Mulh(a, b) = Mulh(b, a) = get_32_highest_bits(a * b)", - "emit" => + "op_flags" => "C", + "arity" => 2, + "comment" => "construct Mulh: Mulh(a, b) = Mulh(b, a) = get_32_highest_bits(a * b)", + "reg_req" => { "in" => [ "eax", "general_purpose" ], "out" => [ "edx" ] }, + "emit" => ' if (mode_is_signed(get_irn_mode(n))) { 4. imull %s2\t\t\t/* signed Mulh(%s1, %s2) -> %d1 */ } @@ -145,10 +180,11 @@ $arch = "ia32"; }, "Mulh_i" => { - "state" => "pinned", - "arity" => 1, - "comment" => "construct Mulh: Mulh(a, const) = Mulh(const, a) = get_32_highest_bits(a * const)", - "emit" => + "state" => "pinned", + "arity" => 1, + "comment" => "construct Mulh: Mulh(a, const) = Mulh(const, a) = get_32_highest_bits(a * const)", + "reg_req" => { "in" => [ "eax" ], "out" => [ "edx" ] }, + "emit" => ' if (mode_is_signed(get_irn_mode(n))) { 4. imull %c\t\t\t/* signed Mulh(%c, %s1) -> %d1 */ } @@ -159,70 +195,94 @@ $arch = "ia32"; }, "And" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct And: And(a, b) = And(b, a) = a AND b", - "emit" => '. andl %s2, %d1\t\t\t/* And(%s1, %s2) -> %d1 */' + "op_flags" => "C", + "arity" => 2, + "remat" => 1, + "comment" => "construct And: And(a, b) = And(b, a) = a AND b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. andl %s2, %d1\t\t\t/* And(%s1, %s2) -> %d1 */' }, "And_i" => { - "arity" => 1, - "comment" => "construct And: And(a, const) = And(const, a) = a AND const", - "emit" => '. andl %c, %d1\t\t\t/* And(%c, %s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct And: And(a, const) = And(const, a) = a AND const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. andl %c, %d1\t\t\t/* And(%c, %s1) -> %d1 */' }, "Or" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b", - "emit" => '. orl %s2, %d1\t\t\t/* Or(%s1, %s2) -> %d1 */' + "op_flags" => "C", + "arity" => 2, + "remat" => 1, + "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. orl %s2, %d1\t\t\t/* Or(%s1, %s2) -> %d1 */' }, "Or_i" => { - "arity" => 1, - "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const", - "emit" => '. orl %c, %d1\t\t\t/* Or(%c, %s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. orl %c, %d1\t\t\t/* Or(%c, %s1) -> %d1 */' }, "Eor" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", - "emit" => '. xorl %s2, %d1\t\t\t/* Xor(%s1, %s2) -> %d1 */' + "op_flags" => "C", + "arity" => 2, + "remat" => 1, + "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. xorl %s2, %d1\t\t\t/* Xor(%s1, %s2) -> %d1 */' }, "Eor_i" => { - "arity" => 1, - "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const", - "emit" => '. xorl %c, %d1\t\t\t/* Xor(%c, %s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. xorl %c, %d1\t\t\t/* Xor(%c, %s1) -> %d1 */' }, "Max" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b", - "emit" => -'2. cmpl %s2, %s1\t\t\t/* prepare Max */ + "op_flags" => "C", + "arity" => 2, + "remat" => 1, + "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => +'2. cmpl %s2, %s1\t\t\t/* prepare Max (%s1 should be %d1) */ if (mode_is_signed(get_irn_mode(n))) { -2. cmovg %s1, %d1\t\t\t/* Max(%s1, %s2) -> %d1 */ +4. cmovl %s2, %d1\t\t\t/* %s1 is less %s2 */ } else { -2. cmova %s1, %d1\t\t\t/* Max(%s1, %s2) -> %d1 */ +4. cmovb %s2, %d1\t\t\t/* %s1 is below %s2 */ } ' }, "Min" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b", - "emit" => -'2. cmpl %s2, %s1\t\t\t/* prepare Min (%s1 - %s2) */ + "op_flags" => "C", + "arity" => 2, + "remat" => 1, + "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => +'2. cmpl %s2, %s1\t\t\t/* prepare Min (%s1 should be %d1) */ if (mode_is_signed(get_irn_mode(n))) { -2. cmovl %s1, %d1\t\t\t/* Min(%s1, %s2) -> %d1 */ +2. cmovg %s2, %d1\t\t\t/* %s1 is greater %s2 */ } else { -2. cmovb %s1, %d1\t\t\t/* Min(%s1, %s2) -> %d1 */ +2. cmova %s2, %d1\t\t\t/* %s1 is above %s2 */ } ' }, @@ -230,160 +290,194 @@ $arch = "ia32"; # not commutative operations "Sub" => { - "arity" => 2, - "comment" => "construct Sub: Sub(a, b) = a - b", - "emit" => '. subl %s2, %s1\t\t\t/* Sub(%s1, %s2) -> %d1 */' + "arity" => 2, + "remat" => 1, + "comment" => "construct Sub: Sub(a, b) = a - b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. subl %s2, %d1\t\t\t/* Sub(%s1, %s2) -> %d1 */' }, "Sub_i" => { - "arity" => 1, - "comment" => "construct Sub: Sub(a, const) = a - const", - "emit" => '. subl %c, %s1\t\t\t/* Sub(%s1, %c) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Sub: Sub(a, const) = a - const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. subl %c, %d1\t\t\t/* Sub(%s1, %c) -> %d1 */' }, -"Mod" => { - "arity" => 2, - "comment" => "construct Mod: Mod(a, b) = a % b", - "emit" => +"DivMod" => { + "arity" => 3, + "comment" => "construct DivMod: DivMod(a,b) = (a / b, a % b)", + "reg_req" => { "in" => [ "eax", "general_purpose", "edx" ], "out" => [ "eax", "edx" ] }, + "emit" => ' if (mode_is_signed(get_irn_mode(n))) { -4. cltd\t\t\t/* sign extend EAX -> EDX:EAX */\n 4. idivl %s2\t\t\t/* signed Mod(%s1, %s2) -> %d1 */ } else { -4. xorl edx, edx\t\t\t/* EDX = 0 */ 4. divl %s2\t\t\t/* unsigned Mod(%s1, %s2) -> %d1 */ } -' -}, +', + "args" => [ + { "type" => "ir_node *", "name" => "divisor" }, + { "type" => "ir_node *", "name" => "dividend" }, + { "type" => "divmod_flavour_t", "name" => "dm_flav" }, # flavours (flavour_Div, flavour_Mod, flavour_DivMod) + { "type" => "ir_mode *", "name" => "mode" }, + ], + "rd_constructor" => +" ir_node *res; + ir_node *in[3]; -"DivMod" => { - "arity" => 2, - "comment" => "construct DivMod: DivMod(a,b) = (a / b, a % b)", - "emit" => -' if (mode_is_signed(get_irn_mode(n))) { -4. cltd\t\t\t/* sign extend EAX -> EDX:EAX */\n -4. idivl %s2\t\t\t/* signed DivMod(%s1, %s2) -> (%d1:%d2) (Div, Mod) */ - } - else { -4. xorl edx, edx\t\t\t/* EDX = 0 */ -4. divl %s2\t\t\t/* unsigned DivMod(%s1, %s2) -> (%d1:%d2) (Div, Mod) */ - } -' -}, + if (!op_ia32_DivMod) assert(0); -"Div" => { - "arity" => 2, - "comment" => "construct Div: Div(a, b) = a / b", - "emit" => -' if (mode_is_signed(get_irn_mode(n))) { -4. cltd\t\t\t/* sign extend EAX -> EDX:EAX */\n -4. idivl %s2\t\t\t/* signed Div(%s1, %s2) -> %d1 */ + in[1] = dividend; + if (mode_is_signed(mode)) { + ir_node *cltd; + /* in signed mode , we need to sign extend the divisor */ + cltd = new_rd_ia32_Cltd(db, current_ir_graph, block, divisor, mode_T); + in[0] = new_rd_Proj(db, current_ir_graph, block, cltd, mode, pn_EAX); + in[2] = new_rd_Proj(db, current_ir_graph, block, cltd, mode, pn_EDX); } else { -4. xorl edx, edx\t\t\t/* EDX = 0 */ -4. divl %s2\t\t\t/* unsigned Div(%s1, %s2) -> %d1 */ + in[0] = divisor; + in[2] = new_rd_ia32_Const(dbg, current_ir_graph, block, mode); + set_Const_type(in[2], asmop_Const); + set_Immop_tarval(in[2], get_tarval_null(mode_Iu)); } -' + + res = new_ir_node(db, irg, block, op_ia32_DivMod, mode, 1, in); + res = optimize_node(res); + irn_vrfy_irg(res, irg); + + set_DivMod_flavour(dm_flav); + + return res; +" }, "Shl" => { - "arity" => 2, - "comment" => "construct Shl: Shl(a, b) = a << b", - "emit" => '. shll %s2, %d1\t\t\t/* Shl(%s1, %s2) -> %d1 */' + "arity" => 2, + "remat" => 1, + "comment" => "construct Shl: Shl(a, b) = a << b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. shll %s2, %d1\t\t\t/* Shl(%s1, %s2) -> %d1 */' }, "Shl_i" => { - "arity" => 1, - "comment" => "construct Shl: Shl(a, const) = a << const", - "emit" => '. shll %c, %d1\t\t\t/* Shl(%s1, %c) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Shl: Shl(a, const) = a << const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. shll %c, %d1\t\t\t/* Shl(%s1, %c) -> %d1 */' }, "Shr" => { - "arity" => 2, - "comment" => "construct Shr: Shr(a, b) = a >> b", - "emit" => '. shrl %s2, %d1\t\t\t/* Shr(%s1, %s2) -> %d1 */' + "arity" => 2, + "remat" => 1, + "comment" => "construct Shr: Shr(a, b) = a >> b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. shrl %s2, %d1\t\t\t/* Shr(%s1, %s2) -> %d1 */' }, "Shr_i" => { - "arity" => 1, - "comment" => "construct Shr: Shr(a, const) = a >> const", - "emit" => '. shrl %c, %d1\t\t\t/* Shr(%s1, %c) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Shr: Shr(a, const) = a >> const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. shrl %c, %d1\t\t\t/* Shr(%s1, %c) -> %d1 */' }, "Shrs" => { - "arity" => 2, - "comment" => "construct Shrs: Shrs(a, b) = a >> b", - "emit" => '. sarl %s2, %d1\t\t\t/* Shrs(%s1, %s2) -> %d1 */' + "arity" => 2, + "remat" => 1, + "comment" => "construct Shrs: Shrs(a, b) = a >> b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. sarl %s2, %d1\t\t\t/* Shrs(%s1, %s2) -> %d1 */' }, "Shrs_i" => { - "arity" => 1, - "comment" => "construct Shrs: Shrs(a, const) = a >> const", - "emit" => '. sarl %c, %d1\t\t\t/* Shrs(%s1, %c) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Shrs: Shrs(a, const) = a >> const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. sarl %c, %d1\t\t\t/* Shrs(%s1, %c) -> %d1 */' }, "RotR" => { - "arity" => 2, - "comment" => "construct RotR: RotR(a, b) = a ROTR b", - "emit" => '. rorl %s2, %d1\t\t\t/* RotR(%s1, %s2) -> %d1 */' -}, - -"RotR_i" => { - "arity" => 1, - "comment" => "construct RotR: RotR(a, const) = a ROTR const", - "emit" => '. rorl %c, %d1\t\t\t/* RotR(%s1, %c) -> %d1 */' + "arity" => 2, + "remat" => 1, + "comment" => "construct RotR: RotR(a, b) = a ROTR b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. rorl %s2, %d1\t\t\t/* RotR(%s1, %s2) -> %d1 */' }, "RotL" => { - "arity" => 2, - "comment" => "construct RotL: RotL(a, b) = a ROTL b", - "emit" => '. roll %s2, %d1\t\t\t/* RotL(%s1, %s2) -> %d1 */' + "arity" => 2, + "remat" => 1, + "comment" => "construct RotL: RotL(a, b) = a ROTL b", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. roll %s2, %d1\t\t\t/* RotL(%s1, %s2) -> %d1 */' }, "RotL_i" => { - "arity" => 1, - "comment" => "construct RotL: RotL(a, const) = a ROTL const", - "emit" => '. roll %c, %d1\t\t\t/* RotL(%s1, %c) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct RotL: RotL(a, const) = a ROTL const", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. roll %c, %d1\t\t\t/* RotL(%s1, %c) -> %d1 */' }, "Minus" => { - "arity" => 1, - "comment" => "construct Minus: Minus(a) = -a", - "emit" => '. negl %d1\t\t\t/* Neg(%s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Minus: Minus(a) = -a", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. negl %d1\t\t\t/* Neg(%s1) -> %d1 */' }, "Inc" => { - "arity" => 1, - "comment" => "construct Increment: Inc(a) = a++", - "emit" => '. incl %d1\t\t\t/* Inc(%s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Increment: Inc(a) = a++", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. incl %d1\t\t\t/* Inc(%s1) -> %d1 */' }, "Dec" => { - "arity" => 1, - "comment" => "construct Decrement: Dec(a) = a--", - "emit" => '. decl %d1\t\t\t/* Dec(%s1) -> %d1 */' -}, - -"Abs" => { - "arity" => 1, - "comment" => "construct Abs: Abs(a) = |a|", - "emit" => -'2. cdq\t\t\t/* Abs: EAX->EDX:EAX */ -2. xorl %edx, %eax\t\t\t/* Abs: one-completent */ -2. subl %edx, %eax\t\t\t/* Abs: two-complement */ -' + "arity" => 1, + "remat" => 1, + "comment" => "construct Decrement: Dec(a) = a--", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. decl %d1\t\t\t/* Dec(%s1) -> %d1 */' }, "Not" => { - "arity" => 1, - "comment" => "construct Not: Not(a) = !a", - "emit" => '. notl %d1\t\t\t/* Not(%s1) -> %d1 */' + "arity" => 1, + "remat" => 1, + "comment" => "construct Not: Not(a) = !a", + "check_inout" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, + "emit" => '. notl %d1\t\t\t/* Not(%s1) -> %d1 */' }, # other operations "Conv" => { "arity" => 1, + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] }, "comment" => "construct Conv: Conv(a) = (conv)a" }, @@ -391,38 +485,67 @@ $arch = "ia32"; "op_flags" => "C", "arity" => 2, "comment" => "construct Cmp: Cmp(a, b) = a CMP b", + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "flag_register" ] }, "emit" => '. cmpl %s2, %s1\t\t\t/* Cmp(%s1, %s2) -> flags */' }, "Cmp_i" => { "arity" => 1, "comment" => "construct Cmp: Cmp(a, const) = Cmp(const, a) = a CMP const", + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "flag_register" ] }, "emit" => '. cmpl %c, %s1\t\t\t/* Cmp(%s1, %c) -> flags */' }, +"Cond" => { + "arity" => 1, + "comment" => "construct Cond: evaluate Cmp node", + "reg_req" => { "in" => [ "flag_register" ] } +}, + +"Const" => { + "arity" => "0", + "remat" => 1, + "comment" => "represents an integer constant", + "reg_req" => { "out" => [ "general_purpose" ] } +}, + +"Cltd" => { + "arity" => 1, + "remat" => 1, + "comment" => "construct Cltd: sign extend EAX -> EDX:EAX", + "reg_req" => { "in" => [ "eax" ], "out" => [ "eax", "edx" ] }, + "emit" => '. cltd\t\t\t/* sign extend EAX -> EDX:EAX */' +}, + # Load / Store "Load" => { "arity" => 2, + "remat" => 1, "comment" => "construct Load: Load(mem-edge, ptr) = LD ptr", + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] }, "emit" => '. movl (%s1), %d1\t\t\t/* Load((%s1)) -> %d1 */' }, "Store" => { "arity" => 3, + "remat" => 1, "comment" => "construct Store: Store(mem-edge, ptr, val) = ST ptr,val", + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] }, "emit" => '. movl %s1, (%d1)\t\t\t/* Store(%s1) -> (%d1) */' }, "Lea" => { "arity" => 2, "comment" => "construct Lea: Lea(a,b) = lea offs(a,b,const) | res = a + b * const + offs with const = 0,1,2,4,8", + "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] }, "emit" => '. leal %o(%s1, %s2, %c), %d1\t\t\t/* %d1 = %s1 + %s2 << %c + %o */' }, "Lea_i" => { "arity" => 1, "comment" => "construct Lea: Lea(a) = lea offs(a) | res = a + offs", + "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] }, "emit" => '. leal %c(%s1), %d1\t\t\t/* %d1 = %s1 + %c */' }, @@ -430,6 +553,7 @@ $arch = "ia32"; "Call" => { "arity" => 1, + "spill" => 0, "comment" => "construct Call: Call(...)", "args" => [ { "type" => "ir_node *", "name" => "old_call" } ], "rd_constructor" => -- 2.20.1