From: Matthias Braun Date: Thu, 13 Sep 2007 08:11:29 +0000 (+0000) Subject: - first experimental approach of flag modeling in add/adc X-Git-Url: http://nsz.repo.hu/git/?a=commitdiff_plain;h=9539cba0634cc8f125bd802baab7d4dc0f7caeca;p=libfirm - first experimental approach of flag modeling in add/adc - support SourceAM for convs - allow Source/DestAM for 8/16bit modes where this is profitable [r15770] --- diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 1f0779640..c974a6e40 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -66,6 +66,7 @@ #include "../bemodule.h" #include "../begnuas.h" #include "../bestate.h" +#include "../beflags.h" #include "bearch_ia32_t.h" @@ -940,16 +941,102 @@ static void ia32_before_sched(void *self) { (void) self; } +static void turn_back_am(ir_node *node) +{ + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *base = get_irn_n(node, 0); + ir_node *index = get_irn_n(node, 1); + ir_node *mem; + ir_node *load; + ir_node *load_res; + ir_node *mem_proj; + const ir_edge_t *edge; + + ir_fprintf(stderr, "truning back AM in %+F\n", node); + + if(get_ia32_am_arity(node) == ia32_am_unary) { + mem = get_irn_n(node, 3); + } else if(get_ia32_am_arity(node) == ia32_am_binary) { + mem = get_irn_n(node, 4); + } else { + assert(get_ia32_am_arity(node) == ia32_am_ternary); + mem = get_irn_n(node, 5); + } + + load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); + + ia32_copy_am_attrs(load, node); + if(get_ia32_am_arity(node) == ia32_am_unary) { + set_irn_n(node, 2, load_res); + set_irn_n(node, 3, new_NoMem()); + } else if(get_ia32_am_arity(node) == ia32_am_binary) { + set_irn_n(node, 3, load_res); + set_irn_n(node, 4, new_NoMem()); + } else if(get_ia32_am_arity(node) == ia32_am_ternary) { + set_irn_n(node, 3, load_res); + set_irn_n(node, 4, new_NoMem()); + } + + /* rewire mem-proj */ + if(get_irn_mode(node) == mode_T) { + mem_proj = NULL; + foreach_out_edge(node, edge) { + ir_node *out = get_edge_src_irn(edge); + if(get_Proj_proj(out) == pn_ia32_mem) { + mem_proj = out; + break; + } + } + + if(mem_proj != NULL) { + set_Proj_pred(mem_proj, load); + set_Proj_proj(mem_proj, pn_ia32_Load_M); + } + } + + set_ia32_op_type(node, ia32_Normal); + if(sched_is_scheduled(node)) + sched_add_before(node, load); +} + +static ir_node *flags_remat(ir_node *node, ir_node *after) +{ + /* we should turn back source address mode when rematerializing nodes */ + ia32_op_type_t type = get_ia32_op_type(node); + if(type == ia32_AddrModeS) { + turn_back_am(node); + } else if(type == ia32_AddrModeD) { + /* TODO implement this later... */ + panic("found DestAM with flag user %+F this should not happen", node); + } else { + assert(type == ia32_Normal); + } + + ir_node *copy = exact_copy(node); + sched_add_after(after, copy); + + return copy; +} + /** * Called before the register allocator. * Calculate a block schedule here. We need it for the x87 * simulator and the emitter. */ static void ia32_before_ra(void *self) { - ia32_code_gen_t *cg = self; + ia32_code_gen_t *cg = self; /* setup fpu rounding modes */ ia32_setup_fpu_mode(cg); + + /* fixup flags */ + be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags], + &flags_remat); + + ia32_add_missing_keeps(cg); } diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c index 1d9707b09..03d38021c 100644 --- a/ir/be/ia32/ia32_finish.c +++ b/ir/be/ia32/ia32_finish.c @@ -612,16 +612,8 @@ static void fix_am_source(ir_node *irn, void *env) { } /* copy address mode information to load */ - set_ia32_ls_mode(load, get_ia32_ls_mode(irn)); set_ia32_op_type(load, ia32_AddrModeS); - set_ia32_am_scale(load, get_ia32_am_scale(irn)); - set_ia32_am_sc(load, get_ia32_am_sc(irn)); - if(is_ia32_am_sc_sign(irn)) - set_ia32_am_sc_sign(load); - add_ia32_am_offs_int(load, get_ia32_am_offs_int(irn)); - set_ia32_frame_ent(load, get_ia32_frame_ent(irn)); - if (is_ia32_use_frame(irn)) - set_ia32_use_frame(load); + ia32_copy_am_attrs(load, irn); /* insert the load into schedule */ sched_add_before(irn, load); diff --git a/ir/be/ia32/ia32_intrinsics.c b/ir/be/ia32/ia32_intrinsics.c index d639d56df..cc7a60789 100644 --- a/ir/be/ia32/ia32_intrinsics.c +++ b/ir/be/ia32/ia32_intrinsics.c @@ -85,17 +85,20 @@ static void resolve_call(ir_node *call, ir_node *l_res, ir_node *h_res, ir_graph * Map an Add (a_l, a_h, b_l, b_h) */ static int map_Add(ir_node *call, void *ctx) { - ir_graph *irg = current_ir_graph; - dbg_info *dbg = get_irn_dbg_info(call); - ir_node *block = get_nodes_block(call); - ir_node **params = get_Call_param_arr(call); - ir_type *method = get_Call_type(call); - ir_node *a_l = params[BINOP_Left_Low]; - ir_node *a_h = params[BINOP_Left_High]; - ir_node *b_l = params[BINOP_Right_Low]; - ir_node *b_h = params[BINOP_Right_High]; - ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0)); - ir_node *l_res, *h_res, *add; + ir_graph *irg = current_ir_graph; + dbg_info *dbg = get_irn_dbg_info(call); + ir_node *block = get_nodes_block(call); + ir_node **params = get_Call_param_arr(call); + ir_type *method = get_Call_type(call); + ir_node *a_l = params[BINOP_Left_Low]; + ir_node *a_h = params[BINOP_Left_High]; + ir_node *b_l = params[BINOP_Right_Low]; + ir_node *b_h = params[BINOP_Right_High]; + ir_mode *l_mode = get_type_mode(get_method_res_type(method, 0)); + ir_mode *h_mode = get_type_mode(get_method_res_type(method, 1)); + ir_mode *mode_flags = ia32_reg_classes[CLASS_ia32_flags].mode; + ir_node *add_low, *add_high, *flags; + ir_node *l_res, *h_res; (void) ctx; assert(l_mode == get_type_mode(get_method_res_type(method, 1)) && "64bit lowered into different modes"); @@ -103,9 +106,12 @@ static int map_Add(ir_node *call, void *ctx) { /* l_res = a_l + b_l */ /* h_res = a_h + b_h + carry */ - add = new_rd_ia32_Add64Bit(dbg, irg, block, a_l, a_h, b_l, b_h); - l_res = new_r_Proj(irg, block, add, l_mode, pn_ia32_Add64Bit_low_res); - h_res = new_r_Proj(irg, block, add, l_mode, pn_ia32_Add64Bit_high_res); + add_low = new_rd_ia32_l_Add(dbg, irg, block, a_l, b_l, mode_T); + flags = new_r_Proj(irg, block, add_low, mode_flags, pn_ia32_flags); + add_high = new_rd_ia32_l_Adc(dbg, irg, block, a_h, b_h, flags, h_mode); + + l_res = new_r_Proj(irg, block, add_low, l_mode, pn_ia32_res); + h_res = add_high; resolve_call(call, l_res, h_res, irg, block); return 1; diff --git a/ir/be/ia32/ia32_nodes_attr.h b/ir/be/ia32/ia32_nodes_attr.h index 298ff574d..6e41e8b02 100644 --- a/ir/be/ia32/ia32_nodes_attr.h +++ b/ir/be/ia32/ia32_nodes_attr.h @@ -88,6 +88,7 @@ typedef struct ia32_attr_t ia32_attr_t; struct ia32_attr_t { except_attr exc; /**< the exception attribute. MUST be the first one. */ struct ia32_attr_data_bitfield { + unsigned flags:5; /**< Indicating if spillable, rematerializeable, stack modifying and/or ignore. */ unsigned tp:3; /**< ia32 node type. */ unsigned am_support:2; /**< Indicates the address mode type supported by this node. */ unsigned am_arity : 2; @@ -99,8 +100,6 @@ struct ia32_attr_t { ia32_op_flavour_t op_flav:2;/**< Flavour of an op (flavour_Div/Mod/DivMod). */ - unsigned flags:4; /**< Indicating if spillable, rematerializeable, stack modifying and/or ignore. */ - unsigned is_commutative:1; /**< Indicates whether op is commutative or not. */ unsigned got_lea:1; /**< Indicates whether or not this node already consumed a LEA. */ diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 6bd8f8f0d..efea8925b 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -309,7 +309,7 @@ sub ia32_custom_init_attr { my $name = shift; my $res = ""; if(defined($node->{modified_flags})) { - $res .= "\t/*attr->data.flags |= arch_irn_flags_modify_flags;*/\n"; + $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n"; } if(defined($node->{am})) { my $am = $node->{am}; @@ -415,7 +415,7 @@ ProduceVal => { Add => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] }, ins => [ "base", "index", "mem", "left", "right" ], emit => '. add%M %binop', am => "full,binary", @@ -444,6 +444,17 @@ Adc => { modified_flags => $status_flags }, +l_Add => { + op_flags => "C", + reg_req => { in => [ "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right" ], +}, + +l_Adc => { + reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right", "eflags" ], +}, + Add64Bit => { irn_flags => "R", arity => 4, @@ -927,7 +938,6 @@ Not => { emit => '. not %S0', units => [ "GP" ], mode => $mode_gp, - modified_flags => [] }, NotMem => { @@ -937,7 +947,6 @@ NotMem => { emit => '. not%M %AM', units => [ "GP" ], mode => "mode_M", - modified_flags => [], }, # other operations @@ -1010,7 +1019,6 @@ IJmp => { emit => '. jmp *%S0', units => [ "BRANCH" ], mode => "mode_X", - modified_flags => [] }, Const => { @@ -1190,7 +1198,6 @@ Lea => { latency => 2, units => [ "GP" ], mode => $mode_gp, - modified_flags => [], }, Push => { @@ -1201,7 +1208,6 @@ Push => { am => "source,binary", latency => 2, units => [ "GP" ], - modified_flags => [], }, Pop => { @@ -1212,7 +1218,6 @@ Pop => { am => "dest,unary", latency => 3, # Pop is more expensive than Push on Athlon units => [ "GP" ], - modified_flags => [], }, Enter => { @@ -1494,7 +1499,8 @@ CopyB => { reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, outs => [ "DST", "SRC", "CNT", "M" ], units => [ "GP" ], - modified_flags => [ "DF" ] +# we don't care about this flag, so no need to mark this node +# modified_flags => [ "DF" ] }, CopyB_i => { @@ -1503,7 +1509,8 @@ CopyB_i => { reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, outs => [ "DST", "SRC", "M" ], units => [ "GP" ], - modified_flags => [ "DF" ] +# we don't care about this flag, so no need to mark this node +# modified_flags => [ "DF" ] }, # Conversions diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 6fbd0ce21..ee8b3d8ad 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -136,8 +136,8 @@ static ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type); static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, - dbg_info *dbgi, ir_node *new_block, - ir_node *new_op); + dbg_info *dbgi, ir_node *block, + ir_node *op, ir_node *orig_node); /** * Return true if a mode can be stored in the GP register set @@ -482,7 +482,13 @@ static int use_source_address_mode(ir_node *block, ir_node *node, mode = get_irn_mode(node); if(!mode_needs_gp_reg(mode)) return 0; - if(get_mode_size_bits(mode) != 32) + /* + * Matze: the unresolved question here is wether 8/16bit operations + * are a good idea if they define registers (as writing to an 8/16 + * bit reg is bad on modern cpu as it confuses the dependency calculation + * for the full reg) + */ + if(other != NULL && get_Load_mode(load) != get_irn_mode(other)) return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ @@ -564,7 +570,8 @@ static void set_am_attributes(ir_node *node, ia32_address_mode_t *am) static void match_arguments(ia32_address_mode_t *am, ir_node *block, ir_node *op1, ir_node *op2, int commutative, - int use_am_and_immediates, int use_am) + int use_am_and_immediates, int use_am, + int use_8_16_bit_am) { ia32_address_t *addr = &am->addr; ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); @@ -573,6 +580,9 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, memset(am, 0, sizeof(am[0])); + if(!use_8_16_bit_am && get_mode_size_bits(get_irn_mode(op1)) < 32) + use_am = 0; + new_op2 = try_create_Immediate(op2, 0); if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) { build_address(am, op2); @@ -626,7 +636,7 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) if(mode != mode_T) { set_irn_mode(node, mode_T); - return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0); + return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res); } else { return node; } @@ -651,7 +661,7 @@ static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, op1, op2, commutative, 0, 1); + match_arguments(&am, src_block, op1, op2, commutative, 0, 1, 0); new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2); @@ -1010,8 +1020,7 @@ static ir_node *gen_And(ir_node *node) { if (v == 0xFF || v == 0xFFFF) { dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = be_transform_node(op1); + ir_node *block = get_nodes_block(node); ir_mode *src_mode; ir_node *res; @@ -1021,8 +1030,7 @@ static ir_node *gen_And(ir_node *node) { assert(v == 0xFFFF); src_mode = mode_Hu; } - res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node); return res; } @@ -1309,8 +1317,7 @@ static ir_node *gen_Shrs(ir_node *node) { long val = get_tarval_long(tv1); if(val == 16 || val == 24) { dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = be_transform_node(shl_left); + ir_node *block = get_nodes_block(node); ir_mode *src_mode; ir_node *res; @@ -1321,9 +1328,7 @@ static ir_node *gen_Shrs(ir_node *node) { src_mode = mode_Hs; } res = create_I2I_Conv(src_mode, mode_Is, dbgi, block, - new_op); - SET_IA32_ORIG_NODE(res, - ia32_get_old_node_name(env_cg, node)); + shl_left, node); return res; } @@ -1770,8 +1775,6 @@ static ir_node *try_create_dest_am(ir_node *node) { /* handle only GP modes for now... */ if(!mode_needs_gp_reg(mode)) return NULL; - if(get_mode_size_bits(mode) != 32) - return NULL; /* store must be the only user of the val node */ if(get_irn_n_edges(val) > 1) @@ -1967,7 +1970,7 @@ static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc, mode = mode_Iu; assert(get_mode_size_bits(mode) <= 32); - match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am); + match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1); if(am.flipped) pnc = get_inversed_pnc(pnc); @@ -2099,7 +2102,7 @@ static ir_node *gen_Cond(ir_node *node) { } else { ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am); + match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am, 1); if(am.flipped) pnc = get_inversed_pnc(pnc); @@ -2212,7 +2215,7 @@ static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right, assert(get_mode_size_bits(mode) <= 32); - match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am); + match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1); if(am.flipped) pnc = get_inversed_pnc(pnc); @@ -2238,7 +2241,7 @@ static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right, mode = get_irn_mode(cmp_left); assert(get_mode_size_bits(mode) <= 32); - match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am); + match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am, 1); if(am.flipped) pnc = get_inversed_pnc(pnc); @@ -2564,17 +2567,20 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { * Crete a conversion from one integer mode into another one */ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, - dbg_info *dbgi, ir_node *new_block, - ir_node *new_op) + dbg_info *dbgi, ir_node *block, ir_node *op, + ir_node *node) { - ir_graph *irg = current_ir_graph; - int src_bits = get_mode_size_bits(src_mode); - int tgt_bits = get_mode_size_bits(tgt_mode); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_rd_NoMem(irg); + ir_graph *irg = current_ir_graph; + int src_bits = get_mode_size_bits(src_mode); + int tgt_bits = get_mode_size_bits(tgt_mode); + ir_node *new_block = be_transform_node(block); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *new_op; ir_node *res; ir_mode *smaller_mode; int smaller_bits; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; if (src_bits < tgt_bits) { smaller_mode = src_mode; @@ -2584,15 +2590,38 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, smaller_bits = tgt_bits; } + memset(&am, 0, sizeof(am)); + if(use_source_address_mode(block, op, NULL)) { + build_address(&am, op); + new_op = noreg; + am.op_type = ia32_AddrModeS; + } else { + new_op = be_transform_node(op); + am.op_type = ia32_Normal; + } + if(addr->base == NULL) + addr->base = noreg; + if(addr->index == NULL) + addr->index = noreg; + if(addr->mem == NULL) + addr->mem = new_NoMem(); + DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); if (smaller_bits == 8) { - res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, - new_op, smaller_mode); + res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, new_op, + smaller_mode); } else { - res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, nomem, - new_op, smaller_mode); + res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, new_op, + smaller_mode); } + set_am_attributes(res, &am); + set_ia32_ls_mode(res, smaller_mode); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + res = fix_mem_proj(res, &am); + return res; } @@ -2602,40 +2631,42 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, * @return The created ia32 Conv node */ static ir_node *gen_Conv(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Conv_op(node); - ir_node *new_op = be_transform_node(op); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *src_mode = get_irn_mode(op); - ir_mode *tgt_mode = get_irn_mode(node); - int src_bits = get_mode_size_bits(src_mode); - int tgt_bits = get_mode_size_bits(tgt_mode); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_rd_NoMem(irg); - ir_node *res; + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *op = get_Conv_op(node); + ir_node *new_op = NULL; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *src_mode = get_irn_mode(op); + ir_mode *tgt_mode = get_irn_mode(node); + int src_bits = get_mode_size_bits(src_mode); + int tgt_bits = get_mode_size_bits(tgt_mode); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_rd_NoMem(irg); + ir_node *res = NULL; if (src_mode == mode_b) { assert(mode_is_int(tgt_mode)); /* nothing to do, we already model bools as 0/1 ints */ - return new_op; + return be_transform_node(op); } if (src_mode == tgt_mode) { if (get_Conv_strict(node)) { if (USE_SSE2(env_cg)) { /* when we are in SSE mode, we can kill all strict no-op conversion */ - return new_op; + return be_transform_node(op); } } else { /* this should be optimized already, but who knows... */ DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node)); DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); - return new_op; + return be_transform_node(op); } } if (mode_is_float(src_mode)) { + new_op = be_transform_node(op); /* we convert from float ... */ if (mode_is_float(tgt_mode)) { if(src_mode == mode_E && tgt_mode == mode_D @@ -2647,8 +2678,8 @@ static ir_node *gen_Conv(ir_node *node) { /* ... to float */ if (USE_SSE2(env_cg)) { DB((dbg, LEVEL_1, "create Conv(float, float) ...")); - res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, nomem, - new_op); + res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg, + nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { if(get_Conv_strict(node)) { @@ -2663,8 +2694,8 @@ static ir_node *gen_Conv(ir_node *node) { /* ... to int */ DB((dbg, LEVEL_1, "create Conv(float, int) ...")); if (USE_SSE2(env_cg)) { - res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, nomem, - new_op); + res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg, + nomem, new_op); set_ia32_ls_mode(res, src_mode); } else { return gen_x87_fp_to_gp(node); @@ -2676,8 +2707,9 @@ static ir_node *gen_Conv(ir_node *node) { /* ... to float */ DB((dbg, LEVEL_1, "create Conv(int, float) ...")); if (USE_SSE2(env_cg)) { - res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, nomem, - new_op); + new_op = be_transform_node(op); + res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg, + nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { res = gen_x87_gp_to_fp(node, src_mode); @@ -2692,21 +2724,20 @@ static ir_node *gen_Conv(ir_node *node) { /* mode_b lowering already took care that we only have 0/1 values */ DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); - return new_op; + return be_transform_node(op); } else { /* to int */ if (src_bits == tgt_bits) { DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); - return new_op; + return be_transform_node(op); } - res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op); + res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node); + return res; } } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - return res; } @@ -3590,6 +3621,48 @@ GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr) GEN_LOWERED_SHIFT_OP(l_Sar, Sar) GEN_LOWERED_SHIFT_OP(l_SarDep, Sar) +static ir_node *gen_ia32_l_Add(ir_node *node) { + ir_node *left = get_irn_n(node, n_ia32_l_Add_left); + ir_node *right = get_irn_n(node, n_ia32_l_Add_right); + ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1); + + if(is_Proj(lowered)) { + lowered = get_Proj_pred(lowered); + } else { + assert(is_ia32_Add(lowered)); + set_irn_mode(lowered, mode_T); + } + + return lowered; +} + +static ir_node *gen_ia32_l_Adc(ir_node *node) { + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left); + ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right); + ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags); + ir_node *new_flags = be_transform_node(flags); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + + match_arguments(&am, src_block, op1, op2, 1, 0, 1, 0); + + new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index, am.new_op1, + am.new_op2, addr->mem, new_flags); + set_am_attributes(new_node, &am); + /* we can't use source address mode anymore when using immediates */ + if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) + set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + new_node = fix_mem_proj(new_node, &am); + + return new_node; +} /** * Transforms an ia32_l_Neg into a "real" ia32_Neg node @@ -4032,9 +4105,9 @@ static ir_node *gen_Proj_Load(ir_node *node) { } else if(is_ia32_Conv_I2I(new_pred)) { set_irn_mode(new_pred, mode_T); if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem); } } else if (is_ia32_xLoad(new_pred)) { if (proj == pn_Load_res) { @@ -4463,6 +4536,8 @@ static void register_transformers(void) /* transform ops from intrinsic lowering */ GEN(ia32_Add64Bit); GEN(ia32_Sub64Bit); + GEN(ia32_l_Add); + GEN(ia32_l_Adc); GEN(ia32_l_Neg); GEN(ia32_l_Mul); GEN(ia32_l_IMul); @@ -4584,6 +4659,9 @@ void add_missing_keep_walker(ir_node *node, void *data) if(class == NULL) { continue; } + if(class == &ia32_reg_classes[CLASS_ia32_flags]) { + continue; + } block = get_nodes_block(node); in[0] = new_r_Proj(current_ir_graph, block, node, @@ -4592,6 +4670,9 @@ void add_missing_keep_walker(ir_node *node, void *data) be_Keep_add_node(last_keep, class, in[0]); } else { last_keep = be_new_Keep(class, current_ir_graph, block, 1, in); + if(sched_is_scheduled(node)) { + sched_add_after(node, last_keep); + } } } } @@ -4600,8 +4681,7 @@ void add_missing_keep_walker(ir_node *node, void *data) * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs * and keeps them. */ -static -void add_missing_keeps(ia32_code_gen_t *cg) +void ia32_add_missing_keeps(ia32_code_gen_t *cg) { ir_graph *irg = be_get_birg_irg(cg->birg); irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL); @@ -4619,7 +4699,6 @@ void ia32_transform_graph(ia32_code_gen_t *cg) { heights_free(heights); heights = NULL; - add_missing_keeps(cg); } void ia32_init_transform(void) diff --git a/ir/be/ia32/ia32_transform.h b/ir/be/ia32/ia32_transform.h index 58b035c1d..fda2b411e 100644 --- a/ir/be/ia32/ia32_transform.h +++ b/ir/be/ia32/ia32_transform.h @@ -59,4 +59,6 @@ typedef enum { */ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct); +void ia32_add_missing_keeps(ia32_code_gen_t *cg); + #endif /* FIRM_BE_IA32_IA32_TRANSFORM_H */