From: Michael Beck Date: Thu, 11 May 2006 16:21:56 +0000 (+0000) Subject: add the new get_param function X-Git-Url: http://nsz.repo.hu/git/?a=commitdiff_plain;h=2601105986be688124e6023d41304d0e27be4442;p=libfirm add the new get_param function --- diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index 13eda4056..c825bbfae 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -583,7 +583,7 @@ static void *arm_cg_init(const be_irg_t *birg) { * and map all instructions the backend did not support * to runtime calls. */ -static void arm_global_init(void) { +static void arm_handle_intrinsics(void) { ir_type *tp, *int_tp, *uint_tp; i_record records[8]; int n_records = 0; @@ -742,7 +742,7 @@ static void *arm_init(FILE *file_handle) { isa->out = file_handle; arm_create_opcodes(); - arm_global_init(); + arm_handle_intrinsics(); arm_switch_section(NULL, NO_SECTION); inited = 1; @@ -874,8 +874,8 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap * return env->isa->sp; ip = be_new_Copy(gp, irg, block, sp ); - arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]); - be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); + arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]); + be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); // if (r0) regs[n_regs++] = r0; // if (r1) regs[n_regs++] = r1; @@ -1060,6 +1060,29 @@ static int arm_get_reg_class_alignment(const void *self, const arch_register_cla return get_mode_size_bytes(mode); } +/** + * Returns the libFirm configuration parameter for this backend. + */ +static const backend_params *arm_get_libfirm_params(void) { + static arch_dep_params_t ad = { + 1, /* allow subs */ + 0, /* Muls are fast enough on ARM */ + 31, /* shift would be ok */ + 0, /* SMUL is needed, only in Arch M*/ + 0, /* UMUL is needed, only in Arch M */ + 32, /* SMUL & UMUL available for 32 bit */ + }; + static backend_params p = { + NULL, /* no additional opcodes */ + NULL, /* will be set later */ + 1, /* need dword lowering */ + NULL, /* but yet no creator function */ + }; + + p.dep_param = &ad; + return &p; +} + #ifdef WITH_LIBCORE /* fpu set architectures. */ @@ -1109,6 +1132,7 @@ const arch_isa_if_t arm_isa_if = { arm_get_code_generator_if, arm_get_list_sched_selector, arm_get_reg_class_alignment, + arm_get_libfirm_params, #ifdef WITH_LIBCORE arm_register_options #endif diff --git a/ir/be/firm/bearch_firm.c b/ir/be/firm/bearch_firm.c index 266d3b789..a61efbfc1 100644 --- a/ir/be/firm/bearch_firm.c +++ b/ir/be/firm/bearch_firm.c @@ -601,6 +601,29 @@ static int firm_get_reg_class_alignment(const void *self, const arch_register_cl return get_mode_size_bytes(mode); } +/** + * Returns the libFirm configuration parameter for this backend. + */ +static const backend_params *firm_get_libfirm_params(void) { + static arch_dep_params_t ad = { + 1, /* allow subs */ + 0, /* Muls are fast enough on Firm */ + 31, /* shift would be ok */ + 0, /* no Mulhs */ + 0, /* no Mulhu */ + 0, /* no Mulh */ + }; + static backend_params p = { + NULL, /* no additional opcodes */ + NULL, /* will be set later */ + 0, /* no dword lowering */ + NULL, /* no creator function */ + }; + + p.dep_param = &ad; + return &p; +} + #ifdef WITH_LIBCORE static void firm_register_options(lc_opt_entry_t *ent) { @@ -618,6 +641,7 @@ const arch_isa_if_t firm_isa = { firm_get_code_generator_if, firm_get_list_sched_selector, firm_get_reg_class_alignment, + firm_get_libfirm_params, #ifdef WITH_LIBCORE firm_register_options, #endif diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c index 090b533f0..a40fa9924 100644 --- a/ir/be/mips/bearch_mips.c +++ b/ir/be/mips/bearch_mips.c @@ -918,6 +918,29 @@ static int mips_get_reg_class_alignment(const void *self, const arch_register_cl return get_mode_size_bytes(mode); } +/** + * Returns the libFirm configuration parameter for this backend. + */ +static const backend_params *mips_get_libfirm_params(void) { + static arch_dep_params_t ad = { + 1, /* allow subs */ + 0, /* Muls are fast enough on Mips */ + 31, /* shift would be ok */ + 0, /* no Mulhs */ + 0, /* no Mulhu */ + 32, /* Mulhs & Mulhu available for 32 bit */ + }; + static backend_params p = { + NULL, /* no additional opcodes */ + NULL, /* will be set later */ + 1, /* need dword lowering */ + NULL, /* but yet no creator function */ + }; + + p.dep_param = &ad; + return &p; +} + #ifdef WITH_LIBCORE static void mips_register_options(lc_opt_entry_t *ent) { @@ -935,6 +958,7 @@ const arch_isa_if_t mips_isa_if = { mips_get_code_generator_if, mips_get_list_sched_selector, mips_get_reg_class_alignment, + mips_get_libfirm_params, #ifdef WITH_LIBCORE mips_register_options #endif diff --git a/ir/be/ppc32/bearch_ppc32.c b/ir/be/ppc32/bearch_ppc32.c index fbdbccd6e..ec5319ce9 100644 --- a/ir/be/ppc32/bearch_ppc32.c +++ b/ir/be/ppc32/bearch_ppc32.c @@ -849,6 +849,29 @@ static int ppc32_get_reg_class_alignment(const void *self, const arch_register_c return get_mode_size_bytes(mode); } +/** + * Returns the libFirm configuration parameter for this backend. + */ +static const backend_params *ppc32_get_libfirm_params(void) { + static arch_dep_params_t ad = { + 1, /* allow subs */ + 0, /* Muls are fast enough on ARM */ + 31, /* shift would be ok */ + 0, /* SMUL is needed, only in Arch M*/ + 0, /* UMUL is needed, only in Arch M */ + 32, /* SMUL & UMUL available for 32 bit */ + }; + static backend_params p = { + NULL, /* no additional opcodes */ + NULL, /* will be set later */ + 1, /* need dword lowering */ + NULL, /* but yet no creator function */ + }; + + p.dep_param = &ad; + return &p; +} + #ifdef WITH_LIBCORE static void ppc32_register_options(lc_opt_entry_t *ent) { @@ -866,6 +889,7 @@ const arch_isa_if_t ppc32_isa_if = { ppc32_get_code_generator_if, ppc32_get_list_sched_selector, ppc32_get_reg_class_alignment, + ppc32_get_libfirm_params, #ifdef WITH_LIBCORE ppc32_register_options #endif