From: Michael Beck <beck@ipd.info.uni-karlsruhe.de>
Date: Thu, 30 Mar 2006 15:51:51 +0000 (+0000)
Subject: Add get_reg_class_alignment() implementation
X-Git-Url: http://nsz.repo.hu/git/?a=commitdiff_plain;ds=sidebyside;h=c560dd51d60b648a49e532dfb40d9d346a69d465;p=libfirm

Add get_reg_class_alignment() implementation
---

diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c
index f487e9e44..64f0022fa 100644
--- a/ir/be/arm/bearch_arm.c
+++ b/ir/be/arm/bearch_arm.c
@@ -955,6 +955,14 @@ static const list_sched_selector_t *arm_get_list_sched_selector(const void *self
 	return &arm_sched_selector;
 }
 
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+	ir_mode *mode = arch_register_class_mode(cls);
+	return get_mode_size_bytes(mode);
+}
+
 #ifdef WITH_LIBCORE
 static void arm_register_options(lc_opt_entry_t *ent)
 {
@@ -974,4 +982,5 @@ const arch_isa_if_t arm_isa_if = {
 	arm_get_irn_handler,
 	arm_get_code_generator_if,
 	arm_get_list_sched_selector,
+	arm_get_reg_class_alignment
 };
diff --git a/ir/be/firm/bearch_firm.c b/ir/be/firm/bearch_firm.c
index 498417614..77ead41f4 100644
--- a/ir/be/firm/bearch_firm.c
+++ b/ir/be/firm/bearch_firm.c
@@ -597,6 +597,14 @@ static const list_sched_selector_t *firm_get_list_sched_selector(const void *sel
 	return trivial_selector;
 }
 
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int firm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+	ir_mode *mode = arch_register_class_mode(cls);
+	return get_mode_size_bytes(mode);
+}
+
 #ifdef WITH_LIBCORE
 static void firm_register_options(lc_opt_entry_t *ent)
 {
@@ -615,5 +623,6 @@ const arch_isa_if_t firm_isa = {
 	firm_get_call_abi,
 	firm_get_irn_handler,
 	firm_get_code_generator_if,
-	firm_get_list_sched_selector
+	firm_get_list_sched_selector,
+	firm_get_reg_class_alignment
 };
diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index bbf2d5466..159ec35a5 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -1034,6 +1034,18 @@ static const list_sched_selector_t *ia32_get_list_sched_selector(const void *sel
 	return &ia32_sched_selector;
 }
 
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+	ir_mode *mode = arch_register_class_mode(cls);
+	int bytes     = get_mode_size_bytes(mode);
+
+	if (mode_is_float(mode) && bytes > 8)
+		return 16;
+	return bytes;
+}
+
 #ifdef WITH_LIBCORE
 static void ia32_register_options(lc_opt_entry_t *ent)
 {
@@ -1052,5 +1064,6 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_get_call_abi,
 	ia32_get_irn_handler,
 	ia32_get_code_generator_if,
-	ia32_get_list_sched_selector
+	ia32_get_list_sched_selector,
+	ia32_get_reg_class_alignment
 };
diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c
index 0f27cab4b..97b54a0c7 100644
--- a/ir/be/mips/bearch_mips.c
+++ b/ir/be/mips/bearch_mips.c
@@ -906,6 +906,14 @@ static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
 	return &mips_code_gen_if;
 }
 
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+	ir_mode *mode = arch_register_class_mode(cls);
+	return get_mode_size_bytes(mode);
+}
+
 #ifdef WITH_LIBCORE
 static void mips_register_options(lc_opt_entry_t *ent)
 {
@@ -925,4 +933,5 @@ const arch_isa_if_t mips_isa_if = {
 	mips_get_irn_handler,
 	mips_get_code_generator_if,
 	mips_get_list_sched_selector,
+	mips_get_reg_class_alignment
 };
diff --git a/ir/be/ppc32/bearch_ppc32.c b/ir/be/ppc32/bearch_ppc32.c
index 36e5e38a7..1c02ffa49 100644
--- a/ir/be/ppc32/bearch_ppc32.c
+++ b/ir/be/ppc32/bearch_ppc32.c
@@ -838,6 +838,14 @@ static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *se
 	return &ppc32_sched_selector;
 }
 
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+	ir_mode *mode = arch_register_class_mode(cls);
+	return get_mode_size_bytes(mode);
+}
+
 #ifdef WITH_LIBCORE
 static void ppc32_register_options(lc_opt_entry_t *ent)
 {
@@ -857,4 +865,5 @@ const arch_isa_if_t ppc32_isa_if = {
 	ppc32_get_irn_handler,
 	ppc32_get_code_generator_if,
 	ppc32_get_list_sched_selector,
+	ppc32_get_reg_class_alignment
 };