= sizeof(param_regs)/sizeof(param_regs[0]);
int n_result_regs
= sizeof(result_regs)/sizeof(result_regs[0]);
+ int n_float_result_regs
+ = sizeof(float_result_regs)/sizeof(float_result_regs[0]);
int n_params;
int n_results;
int i;
int regnum;
+ int float_regnum;
calling_convention_t *cconv;
/* determine how parameters are passed */
ir_mode *mode = get_type_mode(param_type);
int bits = get_mode_size_bits(mode);
reg_or_stackslot_t *param = ¶ms[i];
+ param->type = param_type;
if (regnum < n_param_regs) {
const arch_register_t *reg = param_regs[regnum++];
param->reg0 = reg;
} else {
- param->type = param_type;
param->offset = stack_offset;
/* increase offset 4 bytes so everything is aligned */
- stack_offset += 4;
+ stack_offset += bits > 32 ? bits/8 : 4;
continue;
}
ir_type *type = get_type_for_mode(mode);
param->type = type;
param->offset = stack_offset;
+ assert(get_mode_size_bits(mode) == 32);
stack_offset += 4;
}
}
}
- n_results = get_method_n_ress(function_type);
- regnum = 0;
- results = XMALLOCNZ(reg_or_stackslot_t, n_results);
+ n_results = get_method_n_ress(function_type);
+ regnum = 0;
+ float_regnum = 0;
+ results = XMALLOCNZ(reg_or_stackslot_t, n_results);
for (i = 0; i < n_results; ++i) {
ir_type *result_type = get_method_res_type(function_type, i);
ir_mode *result_mode = get_type_mode(result_type);
reg_or_stackslot_t *result = &results[i];
- if (get_mode_size_bits(result_mode) > 32) {
- panic("Results with more than 32bits not supported by arm backend yet");
- }
-
- if (regnum >= n_result_regs) {
- panic("Too many results for arm backend");
+ if (mode_is_float(result_mode)) {
+ if (float_regnum >= n_float_result_regs) {
+ panic("Too many float results for arm backend");
+ } else {
+ const arch_register_t *reg = float_result_regs[float_regnum++];
+ result->reg0 = reg;
+ }
} else {
- const arch_register_t *reg = result_regs[regnum++];
- result->reg0 = reg;
+ if (get_mode_size_bits(result_mode) > 32) {
+ panic("Results with more than 32bits not supported by arm backend yet");
+ }
+
+ if (regnum >= n_result_regs) {
+ panic("Too many results for arm backend");
+ } else {
+ const arch_register_t *reg = result_regs[regnum++];
+ result->reg0 = reg;
+ }
}
}
&arm_gp_regs[REG_R1],
&arm_gp_regs[REG_R2],
&arm_gp_regs[REG_R3],
- &arm_gp_regs[REG_LR]
+ &arm_gp_regs[REG_LR],
+
+ &arm_fpa_regs[REG_F0],
+ &arm_fpa_regs[REG_F1],
+ &arm_fpa_regs[REG_F2],
+ &arm_fpa_regs[REG_F3],
+ &arm_fpa_regs[REG_F4],
+ &arm_fpa_regs[REG_F5],
+ &arm_fpa_regs[REG_F6],
+ &arm_fpa_regs[REG_F7],
};
static const arch_register_t* const param_regs[] = {
&arm_gp_regs[REG_R3]
};
+static const arch_register_t* const float_result_regs[] = {
+ &arm_fpa_regs[REG_F0],
+ &arm_fpa_regs[REG_F1]
+};
+
/** information about a single parameter or result */
typedef struct reg_or_stackslot_t
{
return reg;
}
-/**
- * Emit the name of the source register at given input position.
- */
void arm_emit_source_register(const ir_node *node, int pos)
{
const arch_register_t *reg = get_in_reg(node, pos);
be_emit_string(arch_register_get_name(reg));
}
-/**
- * Emit the name of the destination register at given output position.
- */
void arm_emit_dest_register(const ir_node *node, int pos)
{
const arch_register_t *reg = get_out_reg(node, pos);
be_emit_string(arch_register_get_name(reg));
}
-/**
- * Emit a node's offset.
- */
void arm_emit_offset(const ir_node *node)
{
const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
be_emit_char(c);
}
-/**
- * Emit the instruction suffix depending on the mode.
- */
-void arm_emit_mode(const ir_node *node)
+void arm_emit_float_load_store_mode(const ir_node *node)
{
- ir_mode *mode;
+ const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
+ arm_emit_fpa_postfix(attr->load_store_mode);
+}
- if (is_arm_irn(node)) {
- const arm_attr_t *attr = get_arm_attr_const(node);
- mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
- } else {
- mode = get_irn_mode(node);
- }
- arm_emit_fpa_postfix(mode);
+void arm_emit_float_arithmetic_mode(const ir_node *node)
+{
+ const arm_farith_attr_t *attr = get_arm_farith_attr_const(node);
+ arm_emit_fpa_postfix(attr->mode);
}
void arm_emit_symconst(const ir_node *node)
/**
* Emit a floating point fpa constant.
*/
-static void emit_arm_fpaConst(const ir_node *irn)
+static void emit_arm_fConst(const ir_node *irn)
{
sym_or_tv_t key, *entry;
unsigned label;
ir_mode *mode;
- key.u.tv = get_fpaConst_value(irn);
+ key.u.tv = get_fConst_value(irn);
key.is_entity = false;
key.label = 0;
entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
if (mode_is_float(mode)) {
if (USE_FPA(cg->isa)) {
be_emit_cstring("\tmvf");
- arm_emit_mode(irn);
be_emit_char(' ');
arm_emit_dest_register(irn, 0);
be_emit_cstring(", ");
be_emit_finish_line_gas(node);
}
-static void emit_arm_fpaDbl2GP(const ir_node *irn)
-{
- be_emit_cstring("\tstfd ");
- arm_emit_source_register(irn, 0);
- be_emit_cstring(", [sp, #-8]!");
- be_emit_pad_comment();
- be_emit_cstring("/* Push fp to stack */");
- be_emit_finish_line_gas(NULL);
-
- be_emit_cstring("\tldmfd sp!, {");
- arm_emit_dest_register(irn, 1);
- be_emit_cstring(", ");
- arm_emit_dest_register(irn, 0);
- be_emit_char('}');
- be_emit_pad_comment();
- be_emit_cstring("/* Pop destination */");
- be_emit_finish_line_gas(irn);
-}
-
-static void emit_arm_LdTls(const ir_node *irn)
-{
- (void) irn;
- panic("TLS not supported for this target");
- /* Er... our gcc does not support it... Install a newer toolchain. */
-}
-
static void emit_nothing(const ir_node *irn)
{
(void) irn;
arm_register_spec_emitters();
/* custom emitter */
- set_emitter(op_arm_B, emit_arm_B);
- set_emitter(op_arm_CopyB, emit_arm_CopyB);
- set_emitter(op_arm_fpaConst, emit_arm_fpaConst);
- set_emitter(op_arm_fpaDbl2GP, emit_arm_fpaDbl2GP);
- set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
- set_emitter(op_arm_Jmp, emit_arm_Jmp);
- set_emitter(op_arm_LdTls, emit_arm_LdTls);
- set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
- set_emitter(op_arm_SymConst, emit_arm_SymConst);
- set_emitter(op_be_Call, emit_be_Call);
- set_emitter(op_be_Copy, emit_be_Copy);
- set_emitter(op_be_CopyKeep, emit_be_Copy);
- set_emitter(op_be_IncSP, emit_be_IncSP);
- set_emitter(op_be_MemPerm, emit_be_MemPerm);
- set_emitter(op_be_Perm, emit_be_Perm);
- set_emitter(op_be_Return, emit_be_Return);
+ set_emitter(op_arm_B, emit_arm_B);
+ set_emitter(op_arm_CopyB, emit_arm_CopyB);
+ set_emitter(op_arm_fConst, emit_arm_fConst);
+ set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
+ set_emitter(op_arm_Jmp, emit_arm_Jmp);
+ set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
+ set_emitter(op_arm_SymConst, emit_arm_SymConst);
+ set_emitter(op_be_Call, emit_be_Call);
+ set_emitter(op_be_Copy, emit_be_Copy);
+ set_emitter(op_be_CopyKeep, emit_be_Copy);
+ set_emitter(op_be_IncSP, emit_be_IncSP);
+ set_emitter(op_be_MemPerm, emit_be_MemPerm);
+ set_emitter(op_be_Perm, emit_be_Perm);
+ set_emitter(op_be_Return, emit_be_Return);
/* no need to emit anything for the following nodes */
- set_emitter(op_Phi, emit_nothing);
- set_emitter(op_be_Keep, emit_nothing);
- set_emitter(op_be_Start, emit_nothing);
- set_emitter(op_be_Barrier, emit_nothing);
+ set_emitter(op_Phi, emit_nothing);
+ set_emitter(op_be_Keep, emit_nothing);
+ set_emitter(op_be_Start, emit_nothing);
+ set_emitter(op_be_Barrier, emit_nothing);
}
/**
return p1->u.generic != p2->u.generic;
}
-/**
- * Main driver. Emits the code for one routine.
- */
void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg)
{
ir_node **blk_sched;
#include "bearch_arm_t.h"
-void arm_emit_mode(const ir_node *node);
+void arm_emit_float_load_store_mode(const ir_node *node);
+void arm_emit_float_arithmetic_mode(const ir_node *node);
void arm_emit_symconst(const ir_node *node);
void arm_emit_source_register(const ir_node *node, int pos);
void arm_emit_dest_register(const ir_node *node, int pos);
static bool has_load_store_attr(const ir_node *node)
{
- return is_arm_Ldr(node) || is_arm_Str(node) || is_arm_LinkLdrPC(node);
+ return is_arm_Ldr(node) || is_arm_Str(node) || is_arm_LinkLdrPC(node)
+ || is_arm_Ldf(node) || is_arm_Stf(node);
}
static bool has_shifter_operand(const ir_node *node)
return is_arm_Cmp(node) || is_arm_Tst(node);
}
+static bool has_farith_attr(const ir_node *node)
+{
+ return is_arm_Dvf(node) || is_arm_Adf(node);
+}
+
/**
* Dumper interface for dumping arm nodes in vcg.
* @param F the output file
fputc('\n', F);
fprintf(F, "frame offset = %d\n", attr->fp_offset);
}
+ if (has_farith_attr(n)) {
+ const arm_farith_attr_t *attr = get_arm_farith_attr_const(n);
+ ir_fprintf(F, "arithmetic mode = %+F\n", attr->mode);
+ }
break;
}
}
return get_irn_generic_attr_const(node);
}
-static const arm_fpaConst_attr_t *get_arm_fpaConst_attr_const(
- const ir_node *node)
+static const arm_fConst_attr_t *get_arm_fConst_attr_const(const ir_node *node)
{
- const arm_attr_t *attr = get_arm_attr_const(node);
- const arm_fpaConst_attr_t *fpa_attr = CONST_CAST_ARM_ATTR(arm_fpaConst_attr_t, attr);
+ assert(is_arm_fConst(node));
+ return get_irn_generic_attr_const(node);
+}
- return fpa_attr;
+static arm_fConst_attr_t *get_arm_fConst_attr(ir_node *node)
+{
+ assert(is_arm_fConst(node));
+ return get_irn_generic_attr(node);
}
-static arm_fpaConst_attr_t *get_arm_fpaConst_attr(ir_node *node)
+arm_farith_attr_t *get_arm_farith_attr(ir_node *node)
{
- arm_attr_t *attr = get_arm_attr(node);
- arm_fpaConst_attr_t *fpa_attr = CAST_ARM_ATTR(arm_fpaConst_attr_t, attr);
+ assert(has_farith_attr(node));
+ return get_irn_generic_attr(node);
+}
- return fpa_attr;
+const arm_farith_attr_t *get_arm_farith_attr_const(const ir_node *node)
+{
+ assert(has_farith_attr(node));
+ return get_irn_generic_attr_const(node);
}
arm_CondJmp_attr_t *get_arm_CondJmp_attr(ir_node *node)
attr->in_req[pos] = req;
}
-tarval *get_fpaConst_value(const ir_node *node)
+tarval *get_fConst_value(const ir_node *node)
{
- const arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr_const(node);
+ const arm_fConst_attr_t *attr = get_arm_fConst_attr_const(node);
return attr->tv;
}
-void set_fpaConst_value(ir_node *node, tarval *tv)
+void set_fConst_value(ir_node *node, tarval *tv)
{
- arm_fpaConst_attr_t *attr = get_arm_fpaConst_attr(node);
+ arm_fConst_attr_t *attr = get_arm_fConst_attr(node);
attr->tv = tv;
}
arch_irn_set_flags(node, flags);
attr->in_req = in_reqs;
- attr->instr_fl = 0;
info = be_get_info(node);
info->out_infos = NEW_ARR_D(reg_out_info_t, obst, n_res);
attr->fp_offset = symconst_offset;
}
+static void init_arm_farith_attributes(ir_node *res, ir_mode *mode)
+{
+ arm_farith_attr_t *attr = get_irn_generic_attr(res);
+ attr->mode = mode;
+}
+
static void init_arm_CopyB_attributes(ir_node *res, unsigned size)
{
arm_CopyB_attr_t *attr = get_irn_generic_attr(res);
static int cmp_attr_arm(ir_node *a, ir_node *b)
{
- arm_attr_t *attr_a = get_irn_generic_attr(a);
- arm_attr_t *attr_b = get_irn_generic_attr(b);
- return attr_a->instr_fl != attr_b->instr_fl;
+ (void) a;
+ (void) b;
+ return 0;
}
static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b)
return 1;
}
-static int cmp_attr_arm_fpaConst(ir_node *a, ir_node *b)
+static int cmp_attr_arm_fConst(ir_node *a, ir_node *b)
{
- const arm_fpaConst_attr_t *attr_a;
- const arm_fpaConst_attr_t *attr_b;
+ const arm_fConst_attr_t *attr_a;
+ const arm_fConst_attr_t *attr_b;
if (cmp_attr_arm(a, b))
return 1;
- attr_a = get_arm_fpaConst_attr_const(a);
- attr_b = get_arm_fpaConst_attr_const(b);
+ attr_a = get_arm_fConst_attr_const(a);
+ attr_b = get_arm_fConst_attr_const(b);
return attr_a->tv != attr_b->tv;
}
return 0;
}
+static int cmp_attr_arm_farith(ir_node *a, ir_node *b)
+{
+ const arm_farith_attr_t *attr_a;
+ const arm_farith_attr_t *attr_b;
+
+ if (cmp_attr_arm(a, b))
+ return 1;
+
+ attr_a = get_arm_farith_attr_const(a);
+ attr_b = get_arm_farith_attr_const(b);
+ return attr_a->mode != attr_b->mode;
+}
+
/** copies the ARM attributes of a node. */
static void arm_copy_attr(ir_graph *irg, const ir_node *old_node,
ir_node *new_node)
arm_cmp_attr_t *get_arm_cmp_attr(ir_node *node);
const arm_cmp_attr_t *get_arm_cmp_attr_const(const ir_node *node);
+arm_farith_attr_t *get_arm_farith_attr(ir_node *node);
+const arm_farith_attr_t *get_arm_farith_attr_const(const ir_node *node);
+
void set_arm_in_req_all(ir_node *node, const arch_register_req_t **reqs);
/**
void set_arm_req_in(ir_node *node, const arch_register_req_t *req, int pos);
/**
-* Return the tarval of a fpaConst
+* Return the tarval of a fConst
*/
-tarval *get_fpaConst_value(const ir_node *node);
+tarval *get_fConst_value(const ir_node *node);
/**
- * Sets the tarval of a fpaConst
+ * Sets the tarval of a fConst
*/
-void set_fpaConst_value(ir_node *node, tarval *tv);
+void set_fConst_value(ir_node *node, tarval *tv);
/**
* Returns the compare kind
ARM_SHF_RRX, /**< rotate right through carry bits */
} arm_shift_modifier_t;
-/** fpa immediate bit */
-#define ARM_FPA_IMM (1 << 3) /**< fpa floating point immediate */
-
-#define ARM_GET_FPA_IMM(attr) ((attr)->instr_fl & ARM_FPA_IMM)
-#define ARM_SET_FPA_IMM(attr) ((attr)->instr_fl |= ARM_FPA_IMM)
-#define ARM_CLR_FPA_IMM(attr) ((attr)->instr_fl &= ~ARM_FPA_IMM)
-
/** Encoding for fpa immediates */
enum fpa_immediates {
fpa_null = 0,
/** Generic ARM node attributes. */
typedef struct arm_attr_t {
- except_attr exc; /**< the exception attribute. MUST be the first one. */
-
+ except_attr exc; /**< the exception attribute. MUST be the first one. */
const arch_register_req_t **in_req; /**< register requirements for arguments */
-
- ir_mode *op_mode; /**< operation mode if different from node's mode (used for fpa nodes) */
- unsigned instr_fl; /**< deprecated (was sometimes used for shift modifiers) */
- bool is_load_store : 1;
+ bool is_load_store : 1;
} arm_attr_t;
/**
} arm_SwitchJmp_attr_t;
/** CopyB attributes */
-typedef struct {
+typedef struct arm_CopyB_attr_t {
arm_attr_t base;
unsigned size;
} arm_CopyB_attr_t;
-/** Attributes for a fpaConst */
-typedef struct arm_fpaConst_attr_t {
+/** Attributes for a fConst */
+typedef struct arm_fConst_attr_t {
arm_attr_t base;
tarval *tv; /**< the tarval representing the FP const */
-} arm_fpaConst_attr_t;
+} arm_fConst_attr_t;
+
+/** attributes for floatingpoint arithmetic operations */
+typedef struct arm_farith_attr_t {
+ arm_attr_t base;
+ ir_mode *mode; /* operation mode */
+} arm_farith_attr_t;
/**
* Return the fpa immediate from the encoding.
# Creation: 2006/02/13
+# Arm Architecure Specification
+# Author: Matthias Braun, Michael Beck, Oliver Richter, Tobias Gneist
# $Id$
-# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
-
$arch = "arm";
#
# Modes
#
-$mode_gp = "mode_Iu";
-$mode_flags = "mode_Bu";
-$mode_fpa = "mode_E";
+$mode_gp = "mode_Iu";
+$mode_flags = "mode_Bu";
+$mode_fp = "mode_E";
# register types:
$normal = 0; # no special type
{ name => "pc", type => $ignore }, # this is our program counter
{ mode => $mode_gp }
],
- fpa => [
+ fpa => [
{ name => "f0", type => $caller_save },
{ name => "f1", type => $caller_save },
{ name => "f2", type => $caller_save },
{ name => "f5", type => $caller_save },
{ name => "f6", type => $caller_save },
{ name => "f7", type => $caller_save },
- { mode => $mode_fpa }
+ { mode => $mode_fp }
],
flags => [
{ name => "fl", type => 0 },
);
%emit_templates = (
- M => "${arch}_emit_mode(node);",
+ FM => "${arch}_emit_float_load_store_mode(node);",
+ AM => "${arch}_emit_float_arithmetic_mode(node);",
LM => "${arch}_emit_load_mode(node);",
SM => "${arch}_emit_store_mode(node);",
SO => "${arch}_emit_shifter_operand(node);",
"\tinit_arm_SymConst_attributes(res, entity, symconst_offset);",
arm_CondJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
- arm_fpaConst_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
+ arm_fConst_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
arm_load_store_attr_t =>
"\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_arm_load_store_attributes(res, ls_mode, entity, entity_sign, offset, is_frame_entity);",
"\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n",
arm_cmp_attr_t =>
"\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n",
+ arm_farith_attr_t =>
+ "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
+ "\tinit_arm_farith_attributes(res, op_mode);",
arm_CopyB_attr_t =>
"\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_arm_CopyB_attributes(res, size);",
arm_SymConst_attr_t => "cmp_attr_arm_SymConst",
arm_CondJmp_attr_t => "cmp_attr_arm_CondJmp",
arm_SwitchJmp_attr_t => "cmp_attr_arm_SwitchJmp",
- arm_fpaConst_attr_t => "cmp_attr_arm_fpaConst",
+ arm_fConst_attr_t => "cmp_attr_arm_fConst",
arm_load_store_attr_t => "cmp_attr_arm_load_store",
arm_shifter_operand_t => "cmp_attr_arm_shifter_operand",
arm_CopyB_attr_t => "cmp_attr_arm_CopyB",
arm_cmp_attr_t => "cmp_attr_arm_cmp",
+ arm_farith_attr_t => "cmp_attr_arm_farith",
);
my %unop_shifter_operand_constructors = (
constructors => \%unop_shifter_operand_constructors,
},
-# Deprecated - we should construct the movs and rsbmi directly...
-Abs => {
- irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "gp" ] },
- emit =>
-'. movs %S0, %S0, #0
-. rsbmi %D0, %S0, #0',
- mode => $mode_gp,
-},
-
# mov lr, pc\n mov pc, XXX -- This combination is used for calls to function
# pointers
LinkMovPC => {
-fpaAdf => {
- irn_flags => "R",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit => '. adf%M %D0, %S0, %S1',
-},
-
-fpaMuf => {
- irn_flags => "R",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit =>'. muf%M %D0, %S0, %S1',
-},
-
-fpaFml => {
- irn_flags => "R",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit =>'. fml%M %D0, %S0, %S1',
-},
-
-fpaMax => {
- irn_flags => "R",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit =>'. fmax %S0, %S1, %D0',
-},
-
-fpaMin => {
+Adf => {
irn_flags => "R",
reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit =>'. fmin %S0, %S1, %D0',
+ emit => '. adf%AM %D0, %S0, %S1',
+ attr_type => "arm_farith_attr_t",
+ attr => "ir_mode *op_mode",
+ mode => $mode_fp,
},
-fpaSuf => {
+Muf => {
irn_flags => "R",
reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit => '. suf%M %D0, %S0, %S1'
+ emit =>'. muf%AM %D0, %S0, %S1',
+ attr_type => "arm_farith_attr_t",
+ attr => "ir_mode *op_mode",
+ mode => $mode_fp,
},
-fpaRsf => {
+Suf => {
irn_flags => "R",
reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa" ] },
- emit => '. rsf%M %D0, %S0, %S1'
-},
-
-fpaDvf => {
+ emit => '. suf%AM %D0, %S0, %S1',
+ attr_type => "arm_farith_attr_t",
attr => "ir_mode *op_mode",
- init_attr => "attr->op_mode = op_mode;",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa", "none" ] },
- emit =>'. dvf%M %D0, %S0, %S1',
- outs => [ "res", "M" ],
+ mode => $mode_fp,
},
-fpaRdf => {
- attr => "ir_mode *op_mode",
- init_attr => "attr->op_mode = op_mode;",
+Dvf => {
reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa", "none" ] },
- emit =>'. rdf%M %D0, %S0, %S1',
+ emit =>'. dvf%AM %D0, %S0, %S1',
outs => [ "res", "M" ],
-},
-
-fpaFdv => {
+ attr_type => "arm_farith_attr_t",
attr => "ir_mode *op_mode",
- init_attr => "attr->op_mode = op_mode;",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa", "none" ] },
- emit =>'. fdv%M %D0, %S0, %S1',
- outs => [ "res", "M" ],
+ mode => $mode_fp,
},
-fpaFrd => {
- attr => "ir_mode *op_mode",
- init_attr => "attr->op_mode = op_mode;",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "fpa", "none" ] },
- emit =>'. frd%M %D0, %S0, %S1',
- outs => [ "res", "M" ],
-},
-
-fpaMvf => {
+Mvf => {
irn_flags => "R",
reg_req => { in => [ "fpa" ], out => [ "fpa" ] },
- emit => '. mvf%M %S0, %D0',
-},
-
-fpaMnf => {
- irn_flags => "R",
- reg_req => { in => [ "fpa" ], out => [ "fpa" ] },
- emit => '. mnf%M %S0, %D0',
-},
-
-fpaAbs => {
- irn_flags => "R",
- reg_req => { in => [ "fpa" ], out => [ "fpa" ] },
- emit => '. abs%M %D0, %S0',
-},
-
-fpaFlt => {
- irn_flags => "R",
- reg_req => { in => ["gp"], out => [ "fpa" ] },
- emit => '. flt%M %D0, %S0',
-},
-
-fpaFix => {
- irn_flags => "R",
- reg_req => { in => ["fpa"], out => [ "gp" ] },
- emit => '. fix %D0, %S0',
-},
-
-Cmf => {
- irn_flags => "R|F",
- mode => $mode_flags,
- attr_type => "arm_cmp_attr_t",
- attr => "bool ins_permuted",
- init_attr => "init_arm_cmp_attr(res, ins_permuted, false);",
- reg_req => { in => [ "fpa", "fpa" ], out => [ "flags" ] },
- emit => '. cmf %S0, %S1',
+ emit => '. mvf%AM %S0, %D0',
+ attr_type => "arm_farith_attr_t",
+ attr => "ir_mode *op_mode",
+ mode => $mode_fp,
},
Cmfe => {
emit => '. cmfe %S0, %S1',
},
-fpaLdf => {
+Ldf => {
op_flags => "L|F",
- irn_flags => "R",
state => "exc_pinned",
- attr => "ir_mode *op_mode",
- init_attr => "attr->op_mode = op_mode;",
- reg_req => { in => [ "gp", "none" ], out => [ "fpa", "none" ] },
- emit => '. ldf%M %D0, [%S0]',
+ ins => [ "ptr", "mem" ],
outs => [ "res", "M" ],
+ reg_req => { in => [ "gp", "none" ], out => [ "fpa", "none" ] },
+ emit => '. ldf%FM %D0, [%S0, #%O]',
+ attr_type => "arm_load_store_attr_t",
+ attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity",
},
-fpaStf => {
+Stf => {
op_flags => "L|F",
- irn_flags => "R",
state => "exc_pinned",
- attr => "ir_mode *op_mode",
- init_attr => "attr->op_mode = op_mode;",
- reg_req => { in => [ "gp", "fpa", "none" ], out => [ "none" ] },
- emit => '. stf%M %S1, [%S0]',
+ ins => [ "ptr", "val", "mem" ],
+ outs => [ "M" ],
mode => "mode_M",
+ reg_req => { in => [ "gp", "fpa", "none" ], out => [ "none" ] },
+ emit => '. stf%FM %S1, [%S0, #%O]',
+ attr_type => "arm_load_store_attr_t",
+ attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity",
},
-fpaDbl2GP => {
- op_flags => "L|F",
- irn_flags => "R",
- reg_req => { in => [ "fpa", "none" ], out => [ "gp", "gp", "none" ] },
- outs => [ "low", "high", "M" ],
-},
-
-AddSP => {
- reg_req => { in => [ "sp", "gp", "none" ], out => [ "sp:I|S", "none" ] },
- emit => '. add %D0, %S0, %S1',
- outs => [ "stack", "M" ],
-},
-
-SubSPandCopy => {
- reg_req => { in => [ "sp", "gp", "none" ], out => [ "sp:I|S", "gp", "none" ] },
- ins => [ "stack", "size", "mem" ],
- emit => ". sub %D0, %S0, %S1\n".
- ". mov sp, %D1",
- outs => [ "stack", "addr", "M" ],
-},
-
-LdTls => {
- irn_flags => "R",
- reg_req => { out => [ "gp" ] },
- mode => $mode_gp,
-},
-
-
#
# floating point constants
#
-fpaConst => {
+fConst => {
op_flags => "c",
irn_flags => "R",
attr => "tarval *tv",
init_attr => "attr->tv = tv;",
mode => "get_tarval_mode(tv)",
reg_req => { out => [ "fpa" ] },
- attr_type => "arm_fpaConst_attr_t",
+ attr_type => "arm_fConst_attr_t",
}
); # end of %nodes
static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
static ir_mode *mode_gp;
+static ir_mode *mode_fp;
static beabi_helper_env_t *abihelper;
static calling_convention_t *cconv = NULL;
if (mode_is_float(src_mode)) {
if (mode_is_float(dst_mode)) {
/* from float to float */
- return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
+ return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
} else {
/* from float to int */
- return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
+ panic("TODO");
}
} else {
/* from int to float */
- return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
+ panic("TODO");
}
} else if (USE_VFP(env_cg->isa)) {
panic("VFP not supported yet");
ir_node *new_op1 = be_transform_node(op1);
ir_node *new_op2 = be_transform_node(op2);
if (USE_FPA(env_cg->isa)) {
-#if 0
- if (is_arm_fpaMvf_i(new_op1))
- return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
- if (is_arm_fpaMvf_i(new_op2))
- return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
-#endif
- return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode);
+ return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
if (mode_is_float(mode)) {
if (USE_FPA(env_cg->isa)) {
-#if 0
- if (is_arm_Mov_i(new_op1))
- return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
- if (is_arm_Mov_i(new_op2))
- return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
-#endif
- return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
+ return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
assert(mode != mode_E && "IEEE Extended FP not supported");
if (USE_FPA(env_cg->isa)) {
-#if 0
- if (is_arm_Mov_i(new_op1))
- return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
- if (is_arm_Mov_i(new_op2))
- return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
-#endif
- return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
+ return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
if (mode_is_float(mode)) {
if (USE_FPA(env_cg->isa)) {
-#if 0
- if (is_arm_Mov_i(new_op1))
- return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
- if (is_arm_Mov_i(new_op2))
- return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
-#endif
- return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode);
+ return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
return new_bd_arm_Mvn_reg(dbgi, block, new_op);
}
-static ir_node *gen_Abs(ir_node *node)
-{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = get_Abs_op(node);
- ir_node *new_op = be_transform_node(op);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
-
- if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
- return new_bd_arm_fpaAbs(dbgi, block, new_op, mode);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
- panic("VFP not supported yet");
- } else {
- panic("Softfloat not supported yet");
- }
- }
- assert(mode_is_data(mode));
- return new_bd_arm_Abs(dbgi, block, new_op);
-}
-
static ir_node *gen_Minus(ir_node *node)
{
ir_node *block = be_transform_node(get_nodes_block(node));
if (mode_is_float(mode)) {
if (USE_FPA(env_cg->isa)) {
- return new_bd_arm_fpaMvf(dbgi, block, op, mode);
+ return new_bd_arm_Mvf(dbgi, block, op, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
if (mode_is_float(mode)) {
if (USE_FPA(env_cg->isa)) {
- new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode);
+ new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
+ NULL, 0, 0, false);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
if (mode_is_float(mode)) {
if (USE_FPA(env_cg->isa)) {
- new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val,
- new_mem, mode);
+ new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
+ new_mem, mode, NULL, 0, 0, false);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet");
if (pnc & pn_Cmp_Uo) {
/* check for unordered, need cmf */
- return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc);
+ return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
}
/* Hmm: use need cmfe */
- return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc);
+ return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
#endif
}
if (mode_is_float(mode)) {
if (USE_FPA(env_cg->isa)) {
tarval *tv = get_Const_tarval(node);
-#if 0
- int imm = is_fpa_immediate(tv);
-
- if (imm != fpa_max) {
- if (imm > 0) {
- node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
- } else {
- node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
- }
- } else
-#endif
- {
- node = new_bd_arm_fpaConst(dbg, block, tv);
- }
+ node = new_bd_arm_fConst(dbg, block, tv);
be_dep_on_frame(node);
return node;
} else if (USE_VFP(env_cg->isa)) {
return new_node;
}
+static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
+ ir_node *node1)
+{
+ /* the good way to do this would be to use the stm (store multiple)
+ * instructions, since our input is nearly always 2 consecutive 32bit
+ * registers... */
+ ir_graph *irg = current_ir_graph;
+ ir_node *stack = get_irg_frame(irg);
+ ir_node *nomem = new_NoMem();
+ ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
+ NULL, 0, 0, true);
+ ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
+ NULL, 0, 4, true);
+ ir_node *in[2] = { str0, str1 };
+ ir_node *sync = new_r_Sync(block, 2, in);
+ ir_node *ldf;
+ set_irn_pinned(str0, op_pin_state_floats);
+ set_irn_pinned(str1, op_pin_state_floats);
+
+ ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
+ set_irn_pinned(ldf, op_pin_state_floats);
+
+ return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
+}
+
+static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *stack = get_irg_frame(irg);
+ ir_node *nomem = new_NoMem();
+ ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
+ NULL, 0, 0, true);
+ ir_node *ldf;
+ set_irn_pinned(str, op_pin_state_floats);
+
+ ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
+ set_irn_pinned(ldf, op_pin_state_floats);
+
+ return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
+}
+
+static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *stack = get_irg_frame(irg);
+ ir_node *nomem = new_NoMem();
+ ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
+ NULL, 0, 0, true);
+ ir_node *ldr;
+ set_irn_pinned(stf, op_pin_state_floats);
+
+ ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
+ set_irn_pinned(ldr, op_pin_state_floats);
+
+ return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
+}
+
+static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
+ ir_node **out_value0, ir_node **out_value1)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *stack = get_irg_frame(irg);
+ ir_node *nomem = new_NoMem();
+ ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
+ NULL, 0, 0, true);
+ ir_node *ldr0, *ldr1;
+ set_irn_pinned(stf, op_pin_state_floats);
+
+ ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
+ set_irn_pinned(ldr0, op_pin_state_floats);
+ ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
+ set_irn_pinned(ldr1, op_pin_state_floats);
+
+ *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
+ *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
+}
+
static ir_node *gen_CopyB(ir_node *node)
{
ir_node *block = be_transform_node(get_nodes_block(node));
return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
}
break;
- case iro_arm_fpaLdf:
+ case iro_arm_Ldf:
if (proj == pn_Load_res) {
ir_mode *mode = get_Load_mode(load);
- return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res);
+ return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M);
+ return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
}
break;
default:
switch (proj) {
case pn_Quot_M:
- if (is_arm_fpaDvf(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M);
- } else if (is_arm_fpaRdf(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M);
- } else if (is_arm_fpaFdv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M);
- } else if (is_arm_fpaFrd(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M);
+ if (is_arm_Dvf(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
}
break;
case pn_Quot_res:
- if (is_arm_fpaDvf(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res);
- } else if (is_arm_fpaRdf(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res);
- } else if (is_arm_fpaFdv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res);
- } else if (is_arm_fpaFrd(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res);
+ if (is_arm_Dvf(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
}
break;
default:
return be_prolog_get_reg_value(abihelper, sp_reg);
case pn_Start_P_tls:
- return new_bd_arm_LdTls(NULL, new_block);
+ return new_Bad();
case pn_Start_max:
break;
static ir_node *gen_Proj_Proj_Start(ir_node *node)
{
- long pn = get_Proj_proj(node);
+ long pn = get_Proj_proj(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_entity *entity = get_irg_entity(current_ir_graph);
+ ir_type *method_type = get_entity_type(entity);
+ ir_type *param_type = get_method_param_type(method_type, pn);
const reg_or_stackslot_t *param;
/* Proj->Proj->Start must be a method argument */
if (param->reg0 != NULL) {
/* argument transmitted in register */
- return be_prolog_get_reg_value(abihelper, param->reg0);
+ ir_mode *mode = get_type_mode(param_type);
+ ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
+
+ if (mode_is_float(mode)) {
+ ir_node *value1 = NULL;
+
+ if (param->reg1 != NULL) {
+ value1 = be_prolog_get_reg_value(abihelper, param->reg1);
+ } else if (param->entity != NULL) {
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *fp = get_irg_frame(irg);
+ ir_node *mem = be_prolog_get_memory(abihelper);
+ ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
+ mode_gp, param->entity,
+ 0, 0, true);
+ value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
+ }
+
+ /* convert integer value to float */
+ if (value1 == NULL) {
+ value = int_to_float(NULL, new_block, value);
+ } else {
+ value = ints_to_double(NULL, new_block, value, value1);
+ }
+ }
+ return value;
} else {
/* argument transmitted on stack */
- ir_graph *irg = get_irn_irg(node);
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- ir_node *fp = get_irg_frame(irg);
- ir_node *mem = be_prolog_get_memory(abihelper);
- ir_mode *mode = get_type_mode(param->type);
- ir_node *load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
- param->entity, 0, 0, true);
- ir_node *value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *fp = get_irg_frame(irg);
+ ir_node *mem = be_prolog_get_memory(abihelper);
+ ir_mode *mode = get_type_mode(param->type);
+ ir_node *load;
+ ir_node *value;
+
+ if (mode_is_float(mode)) {
+ load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
+ param->entity, 0, 0, true);
+ value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
+ } else {
+ load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
+ param->entity, 0, 0, true);
+ value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
+ }
set_irn_pinned(load, op_pin_state_floats);
return value;
ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
tarval *tv = get_mode_null(mode);
- ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv);
+ ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
be_dep_on_frame(node);
return node;
} else if (mode_needs_gp_reg(mode)) {
ir_node *new_mem = be_transform_node(mem);
int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
ir_node *sp_proj = get_stack_pointer_for(node);
+ int n_res = get_Return_n_ress(node);
ir_node *bereturn;
ir_node *incsp;
int i;
- int n_res;
- const arch_register_t *const result_regs[] = {
- &arm_gp_regs[REG_R0],
- &arm_gp_regs[REG_R1]
- };
be_epilog_begin(abihelper);
be_epilog_set_memory(abihelper, new_mem);
sp_proj);
/* result values */
- n_res = get_Return_n_ress(node);
- if (n_res > (int) (sizeof(result_regs)/sizeof(result_regs[0]))) {
- panic("Too many return values for arm backend (%+F)", node);
- }
for (i = 0; i < n_res; ++i) {
- ir_node *res_value = get_Return_res(node, i);
- ir_node *new_res_value = be_transform_node(res_value);
- const arch_register_t *reg = result_regs[i];
+ ir_node *res_value = get_Return_res(node, i);
+ ir_node *new_res_value = be_transform_node(res_value);
+ const reg_or_stackslot_t *slot = &cconv->results[i];
+ const arch_register_t *reg = slot->reg0;
+ assert(slot->reg1 == NULL);
be_epilog_add_reg(abihelper, reg, 0, new_res_value);
}
++in_arity;
/* parameters */
for (p = 0; p < n_params; ++p) {
- ir_node *value = get_Call_param(node, p);
- ir_node *new_value = be_transform_node(value);
- const reg_or_stackslot_t *param = &cconv->parameters[p];
- const arch_register_t *reg = param->reg0;
-
- /* double not implemented yet */
- assert(get_mode_size_bits(get_irn_mode(value)) <= 32);
- assert(param->reg1 == NULL);
-
- if (reg != NULL) {
- in[in_arity] = new_value;
- /* this should not happen, LR cannot be a parameter register ... */
- assert(reg != &arm_gp_regs[REG_LR]);
- in_req[in_arity] = reg->single_req;
- ++in_arity;
- } else {
- ir_mode *mode;
- ir_node *str;
- if (incsp == NULL) {
- /* create a parameter frame */
- ir_node *new_frame = get_stack_pointer_for(node);
- incsp = be_new_IncSP(sp_reg, new_block, new_frame, cconv->param_stack_size, 1);
+ ir_node *value = get_Call_param(node, p);
+ ir_node *new_value = be_transform_node(value);
+ ir_node *new_value1 = NULL;
+ const reg_or_stackslot_t *param = &cconv->parameters[p];
+ ir_type *param_type = get_method_param_type(type, p);
+ ir_mode *mode = get_type_mode(param_type);
+ ir_node *str;
+
+ if (mode_is_float(mode) && param->reg0 != NULL) {
+ unsigned size_bits = get_mode_size_bits(mode);
+ if (size_bits == 64) {
+ double_to_ints(dbgi, new_block, new_value, &new_value,
+ &new_value1);
+ } else {
+ assert(size_bits == 32);
+ new_value = float_to_int(dbgi, new_block, new_value);
}
- mode = get_irn_mode(value);
- str = new_bd_arm_Str(dbgi, new_block, incsp, value, new_mem, mode,
- NULL, 0, param->offset, true);
+ }
- sync_ins[sync_arity++] = str;
+ /* put value into registers */
+ if (param->reg0 != NULL) {
+ in[in_arity] = new_value;
+ in_req[in_arity] = param->reg0->single_req;
+ ++in_arity;
+ if (new_value1 == NULL)
+ continue;
+ }
+ if (param->reg1 != NULL) {
+ assert(new_value1 != NULL);
+ in[in_arity] = new_value1;
+ in_req[in_arity] = param->reg1->single_req;
+ ++in_arity;
+ continue;
+ }
+
+ /* we need a store if we're here */
+ if (new_value1 != NULL) {
+ new_value = new_value1;
+ mode = mode_gp;
+ }
+
+ /* create a parameter frame if necessary */
+ if (incsp == NULL) {
+ ir_node *new_frame = get_stack_pointer_for(node);
+ incsp = be_new_IncSP(sp_reg, new_block, new_frame,
+ cconv->param_stack_size, 1);
+ }
+ if (mode_is_float(mode)) {
+ str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
+ mode, NULL, 0, param->offset, true);
+ } else {
+ str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
+ mode, NULL, 0, param->offset, true);
}
+ sync_ins[sync_arity++] = str;
}
assert(in_arity <= max_inputs);
{
be_start_transform_setup();
- be_set_transform_function(op_Abs, gen_Abs);
be_set_transform_function(op_Add, gen_Add);
be_set_transform_function(op_And, gen_And);
be_set_transform_function(op_Call, gen_Call);
ir_type *frame_type;
mode_gp = mode_Iu;
+ mode_fp = mode_E;
if (! imm_initialized) {
arm_init_fpa_immediate();
}
}
+static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
+{
+ be_fec_env_t *env = data;
+ const ir_mode *mode;
+ int align;
+ ir_entity *entity;
+ const arm_load_store_attr_t *attr;
+
+ if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
+ mode = get_irn_mode(node);
+ align = get_mode_size_bytes(mode);
+ be_node_needs_frame_entity(env, node, mode, align);
+ return;
+ }
+
+ switch (get_arm_irn_opcode(node)) {
+ case iro_arm_Ldf:
+ case iro_arm_Ldr:
+ break;
+ default:
+ return;
+ }
+
+ attr = get_arm_load_store_attr_const(node);
+ entity = attr->entity;
+ mode = attr->load_store_mode;
+ align = get_mode_size_bytes(mode);
+ if (entity != NULL)
+ return;
+ if (!attr->is_frame_entity)
+ return;
+ be_node_needs_frame_entity(env, node, mode, align);
+}
+
+static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
+{
+ if (is_be_node(node)) {
+ be_node_set_frame_entity(node, entity);
+ } else {
+ arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
+ attr->entity = entity;
+ }
+}
+
static void arm_after_ra(void *self)
{
- arm_code_gen_t *cg = self;
- be_coalesce_spillslots(cg->irg);
+ arm_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
+
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
+
+ irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
+ be_assign_entities(fec_env, arm_set_frame_entity);
+ be_free_frame_entity_coalescer(fec_env);
irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
}
assert(n_outs < (int) sizeof(unsigned) * 8);
foreach_out_edge(node, edge) {
- ir_node *node = get_edge_src_irn(edge);
+ ir_node *succ = get_edge_src_irn(edge);
int pn;
/* The node could be kept */
- if (is_End(node) || is_Anchor(node))
+ if (is_End(succ) || is_Anchor(succ))
continue;
- if (get_irn_mode(node) == mode_M)
+ if (get_irn_mode(succ) == mode_M)
continue;
- pn = get_Proj_proj(node);
+ pn = get_Proj_proj(succ);
assert(pn < n_outs);
found_projs |= 1 << pn;
}
break;
}
if (i >= n_regs) {
+ /* the common reason to hit this panic is when 1 of your nodes is not
+ * register pressure faithful */
panic("No register left for %+F\n", node);
}
projects / libfirm / commitdiff