return NULL;
}
+/**
+ * Called by the frontend to encode a register name into a backend specific way
+ */
+static unsigned arm_register_from_name(const char *regname) {
+ /* NYI */
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inlien assembler yet */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ arm_register_from_name, /* register names */
};
p.dep_param = &ad;
#define LC_STOP_AND_RESET_TIMER(timer) do { lc_timer_stop(timer); lc_timer_reset(timer); } while(0)
+/** For inline assembler: get a register from a name and encode it into a backend specific value. */
+typedef unsigned (get_register_fkt)(const char *reg);
+
/**
* This structure contains parameters that should be
* propagated to the libFirm parameter set.
*/
typedef struct backend_params {
+ /** if set, the backend cannot handle DWORD access */
+ unsigned do_dw_lowering:1;
+ /** if set, the backend supports inline assembly */
+ unsigned support_inline_asm:1;
+
/** Additional opcodes settings. */
const arch_ops_info *arch_op_settings;
/** Settings for architecture dependent optimizations */
const arch_dep_params_t *dep_param;
- /** if set, the backend cannot handle DWORD access */
- unsigned do_dw_lowering;
-
/** the architecture specific intrinsic function creator */
create_intrinsic_fkt *arch_create_intrinsic_fkt;
/** backend settings for if-conversion */
const opt_if_conv_info_t *if_conv_info;
+
+ /** get the backend specific register encoding for a register name */
+ get_register_fkt *get_register_from_name;
} backend_params;
/**
/** The be parameters returned by default, all off. */
const static backend_params be_params = {
+ 0,
+ 0,
+ NULL,
+ NULL,
NULL,
NULL,
- 0,
NULL,
+ NULL
};
/* Perform schedule verification if requested. */
0, /* no Mulh */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inlien assembler yet */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 0, /* no dword lowering */
NULL, /* no creator function */
NULL, /* context for create_intrinsic_fkt */
+ NULL, /* no inline assembler: no register names */
};
p.dep_param = &ad;
return 1;
}
+/**
+ * Called by the frontend to encode a register name into a backend specific way
+ */
+static unsigned ia32_register_from_name(const char *regname) {
+ /* NYI */
+ return 0;
+}
+
static ia32_intrinsic_env_t intrinsic_env = {
NULL, /**< the irg, these entities belong to */
NULL, /**< entity for first div operand (move into FPU) */
32 /* Mulh allowed up to 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 1, /* support inline assembly */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
ia32_create_intrinsic_fkt,
&intrinsic_env, /* context for ia32_create_intrinsic_fkt */
NULL, /* will be set later */
+ ia32_register_from_name, /* register names */
};
p.dep_param = &ad;
return NULL;
}
+/**
+ * Called by the frontend to encode a register name into a backend specific way
+ */
+static unsigned mips_register_from_name(const char *regname) {
+ /* NYI */
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
32, /* Mulhs & Mulhu available for 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inlien assembler yet */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ mips_register_from_name, /* register names */
};
p.dep_param = &ad;
return NULL;
}
+/**
+ * Called by the frontend to encode a register name into a backend specific way
+ */
+static unsigned ppc32_register_from_name(const char *regname) {
+ /* NYI */
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inlien assembler yet */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ ppc32_register_from_name, /* register names */
};
p.dep_param = &ad;
-#include <stdio.h>
+//#include <stdio.h>
/* Demonstrates a bug where constant folding ignores width of bitfields */
-struct __attribute__((packed)) A
+#ifdef __GNUC__
+#define PACKED __attribute__((packed))
+#else
+#define PACKED
+#endif
+
+struct PACKED A
{
unsigned int i:1, l:1, j:3, k:11;
};