added additional latencies for Load/Store

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 9b48148..bc2a721 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -648,6 +648,7 @@ else {
   "comment"   => "construct Load: Load(ptr, mem) = LD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
+  "latency"   => 3,
   "emit"      =>
 '  if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
 4.   mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
@@ -684,6 +685,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ] },
   "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
   "outs"      => [ "M" ],
+  "latency"   => 3,
 },
 
 "Store8Bit" => {
@@ -694,6 +696,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
   "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
   "outs"      => [ "M" ],
+  "latency"   => 3,
 },
 
 "Lea" => {