ir_node *op, ir_node *orig_node);
/** Return non-zero is a node represents the 0 constant. */
-static bool is_Const_0(ir_node *node) {
+static bool is_Const_0(ir_node *node)
+{
return is_Const(node) && is_Const_null(node);
}
/** Return non-zero is a node represents the 1 constant. */
-static bool is_Const_1(ir_node *node) {
+static bool is_Const_1(ir_node *node)
+{
return is_Const(node) && is_Const_one(node);
}
/** Return non-zero is a node represents the -1 constant. */
-static bool is_Const_Minus_1(ir_node *node) {
+static bool is_Const_Minus_1(ir_node *node)
+{
return is_Const(node) && is_Const_all_one(node);
}
/**
* Transforms a Const.
*/
-static ir_node *gen_Const(ir_node *node) {
+static ir_node *gen_Const(ir_node *node)
+{
ir_graph *irg = current_ir_graph;
ir_node *old_block = get_nodes_block(node);
ir_node *block = be_transform_node(old_block);
/**
* Transforms a SymConst.
*/
-static ir_node *gen_SymConst(ir_node *node) {
+static ir_node *gen_SymConst(ir_node *node)
+{
ir_graph *irg = current_ir_graph;
ir_node *old_block = get_nodes_block(node);
ir_node *block = be_transform_node(old_block);
} else {
ir_entity *entity;
- if(get_SymConst_kind(node) != symconst_addr_ent) {
+ if (get_SymConst_kind(node) != symconst_addr_ent) {
panic("backend only support symconst_addr_ent (at %+F)", node);
}
entity = get_SymConst_entity(node);
}
/* Generates an entity for a known FP const (used for FP Neg + Abs) */
-ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
+ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
+{
static const struct {
const char *tp_name;
const char *ent_name;
set_ia32_am_scale(node, addr->scale);
set_ia32_am_sc(node, addr->symconst_ent);
set_ia32_am_offs_int(node, addr->offset);
- if(addr->symconst_sign)
+ if (addr->symconst_sign)
set_ia32_am_sc_sign(node);
- if(addr->use_frame)
+ if (addr->use_frame)
set_ia32_use_frame(node);
set_ia32_frame_ent(node, addr->frame_entity);
}
ir_mode *src_mode;
ir_mode *dest_mode;
- if(!is_Conv(node))
+ if (!is_Conv(node))
return 0;
/* we only want to skip the conv when we're the only user
* (not optimal but for now...)
*/
- if(get_irn_n_edges(node) > 1)
+ if (get_irn_n_edges(node) > 1)
return 0;
src_mode = get_irn_mode(get_Conv_op(node));
}
/* Skip all Down-Conv's on a given node and return the resulting node. */
-ir_node *ia32_skip_downconv(ir_node *node) {
+ir_node *ia32_skip_downconv(ir_node *node)
+{
while (is_downconv(node))
node = get_Conv_op(node);
ir_mode *tgt_mode;
dbg_info *dbgi;
- if(mode_is_signed(mode)) {
+ if (mode_is_signed(mode)) {
tgt_mode = mode_Is;
} else {
tgt_mode = mode_Iu;
*
* @return the created ia32 Add node
*/
-static ir_node *gen_Add(ir_node *node) {
+static ir_node *gen_Add(ir_node *node)
+{
ir_mode *mode = get_irn_mode(node);
ir_node *op1 = get_Add_left(node);
ir_node *op2 = get_Add_right(node);
new_block = be_transform_node(block);
/* a constant? */
- if(addr.base == NULL && addr.index == NULL) {
+ if (addr.base == NULL && addr.index == NULL) {
ir_graph *irg = current_ir_graph;
new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
addr.symconst_sign, addr.offset);
return new_node;
}
/* add with immediate? */
- if(addr.index == NULL) {
+ if (addr.index == NULL) {
add_immediate_op = addr.base;
- } else if(addr.base == NULL && addr.scale == 0) {
+ } else if (addr.base == NULL && addr.scale == 0) {
add_immediate_op = addr.index;
}
- if(add_immediate_op != NULL) {
- if(!am_has_immediates(&addr)) {
+ if (add_immediate_op != NULL) {
+ if (!am_has_immediates(&addr)) {
#ifdef DEBUG_libfirm
ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
node);
*
* @return the created ia32 Mul node
*/
-static ir_node *gen_Mul(ir_node *node) {
+static ir_node *gen_Mul(ir_node *node)
+{
ir_node *op1 = get_Mul_left(node);
ir_node *op2 = get_Mul_right(node);
ir_mode *mode = get_irn_mode(node);
*
* @return the created ia32 Mulh node
*/
-static ir_node *gen_Mulh(ir_node *node) {
+static ir_node *gen_Mulh(ir_node *node)
+{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
*
* @return The created ia32 And node
*/
-static ir_node *gen_And(ir_node *node) {
+static ir_node *gen_And(ir_node *node)
+{
ir_node *op1 = get_And_left(node);
ir_node *op2 = get_And_right(node);
assert(! mode_is_float(get_irn_mode(node)));
ir_mode *src_mode;
ir_node *res;
- if(v == 0xFF) {
+ if (v == 0xFF) {
src_mode = mode_Bu;
} else {
assert(v == 0xFFFF);
*
* @return The created ia32 Or node
*/
-static ir_node *gen_Or(ir_node *node) {
+static ir_node *gen_Or(ir_node *node)
+{
ir_node *op1 = get_Or_left(node);
ir_node *op2 = get_Or_right(node);
*
* @return The created ia32 Eor node
*/
-static ir_node *gen_Eor(ir_node *node) {
+static ir_node *gen_Eor(ir_node *node)
+{
ir_node *op1 = get_Eor_left(node);
ir_node *op2 = get_Eor_right(node);
*
* @return The created ia32 Sub node
*/
-static ir_node *gen_Sub(ir_node *node) {
+static ir_node *gen_Sub(ir_node *node)
+{
ir_node *op1 = get_Sub_left(node);
ir_node *op2 = get_Sub_right(node);
ir_mode *mode = get_irn_mode(node);
}
-static ir_node *gen_Mod(ir_node *node) {
+static ir_node *gen_Mod(ir_node *node)
+{
return create_Div(node);
}
-static ir_node *gen_Div(ir_node *node) {
+static ir_node *gen_Div(ir_node *node)
+{
return create_Div(node);
}
-static ir_node *gen_DivMod(ir_node *node) {
+static ir_node *gen_DivMod(ir_node *node)
+{
return create_Div(node);
}
*
* @return The created ia32 Shl node
*/
-static ir_node *gen_Shl(ir_node *node) {
+static ir_node *gen_Shl(ir_node *node)
+{
ir_node *left = get_Shl_left(node);
ir_node *right = get_Shl_right(node);
*
* @return The created ia32 Shr node
*/
-static ir_node *gen_Shr(ir_node *node) {
+static ir_node *gen_Shr(ir_node *node)
+{
ir_node *left = get_Shr_left(node);
ir_node *right = get_Shr_right(node);
*
* @return The created ia32 Shrs node
*/
-static ir_node *gen_Shrs(ir_node *node) {
+static ir_node *gen_Shrs(ir_node *node)
+{
ir_node *left = get_Shrs_left(node);
ir_node *right = get_Shrs_right(node);
ir_mode *mode = get_irn_mode(node);
- if(is_Const(right) && mode == mode_Is) {
+ if (is_Const(right) && mode == mode_Is) {
tarval *tv = get_Const_tarval(right);
long val = get_tarval_long(tv);
- if(val == 31) {
+ if (val == 31) {
/* this is a sign extension */
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
}
/* 8 or 16 bit sign extension? */
- if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
+ if (is_Const(right) && is_Shl(left) && mode == mode_Is) {
ir_node *shl_left = get_Shl_left(left);
ir_node *shl_right = get_Shl_right(left);
- if(is_Const(shl_right)) {
+ if (is_Const(shl_right)) {
tarval *tv1 = get_Const_tarval(right);
tarval *tv2 = get_Const_tarval(shl_right);
- if(tv1 == tv2 && tarval_is_long(tv1)) {
+ if (tv1 == tv2 && tarval_is_long(tv1)) {
long val = get_tarval_long(tv1);
- if(val == 16 || val == 24) {
+ if (val == 16 || val == 24) {
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_mode *src_mode;
ir_node *res;
- if(val == 24) {
+ if (val == 24) {
src_mode = mode_Bs;
} else {
assert(val == 16);
* @param op2 The second operator
* @return The created ia32 RotL node
*/
-static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
+{
return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
}
* @param op2 The second operator
* @return The created ia32 RotR node
*/
-static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
+{
return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
}
*
* @return The created ia32 RotL or RotR node
*/
-static ir_node *gen_Rotl(ir_node *node) {
+static ir_node *gen_Rotl(ir_node *node)
+{
ir_node *rotate = NULL;
ir_node *op1 = get_Rotl_left(node);
ir_node *op2 = get_Rotl_right(node);
*
* @return The created ia32 Not node
*/
-static ir_node *gen_Not(ir_node *node) {
+static ir_node *gen_Not(ir_node *node)
+{
ir_node *op = get_Not_op(node);
assert(get_irn_mode(node) != mode_b); /* should be lowered already */
/**
* Create a bt instruction for x & (1 << n) and place it into the block of cmp.
*/
-static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) {
+static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
+{
dbg_info *dbgi = get_irn_dbg_info(cmp);
ir_node *block = get_nodes_block(cmp);
ir_node *new_block = be_transform_node(block);
*
* @return the created ia32 Load node
*/
-static ir_node *gen_Load(ir_node *node) {
+static ir_node *gen_Load(ir_node *node)
+{
ir_node *old_block = get_nodes_block(node);
ir_node *block = be_transform_node(old_block);
ir_node *ptr = get_Load_ptr(node);
base = addr.base;
index = addr.index;
- if(base == NULL) {
+ if (base == NULL) {
base = noreg;
} else {
base = be_transform_node(base);
}
- if(index == NULL) {
+ if (index == NULL) {
index = noreg;
} else {
index = be_transform_node(index);
assert(mode != mode_b);
/* create a conv node with address mode for smaller modes */
- if(get_mode_size_bits(mode) < 32) {
+ if (get_mode_size_bits(mode) < 32) {
new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
new_mem, noreg, mode);
} else {
set_ia32_ls_mode(new_node, mode);
set_address(new_node, &addr);
- if(get_irn_pinned(node) == op_pin_state_floats) {
+ if (get_irn_pinned(node) == op_pin_state_floats) {
add_ia32_flags(new_node, arch_irn_flags_rematerializable);
}
assert(flags & match_immediate); /* there is no destam node without... */
commutative = (flags & match_commutative) != 0;
- if(use_dest_am(src_block, op1, mem, ptr, op2)) {
+ if (use_dest_am(src_block, op1, mem, ptr, op2)) {
build_address(&am, op1);
new_op = create_immediate_or_transform(op2, 0);
- } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
+ } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
build_address(&am, op2);
new_op = create_immediate_or_transform(op1, 0);
} else {
return NULL;
}
- if(addr->base == NULL)
+ if (addr->base == NULL)
addr->base = noreg_gp;
- if(addr->index == NULL)
+ if (addr->index == NULL)
addr->index = noreg_gp;
- if(addr->mem == NULL)
+ if (addr->mem == NULL)
addr->mem = new_NoMem();
dbgi = get_irn_dbg_info(node);
block = be_transform_node(src_block);
new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem);
- if(get_mode_size_bits(mode) == 8) {
+ if (get_mode_size_bits(mode) == 8) {
new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
new_mem, new_op);
} else {
ia32_address_t *addr = &am.addr;
memset(&am, 0, sizeof(am));
- if(!use_dest_am(src_block, op, mem, ptr, NULL))
+ if (!use_dest_am(src_block, op, mem, ptr, NULL))
return NULL;
build_address(&am, op);
return new_node;
}
-static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
+static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
+{
ir_mode *mode = get_irn_mode(node);
ir_node *mux_true = get_Mux_true(node);
ir_node *mux_false = get_Mux_false(node);
pn_Cmp pnc;
ia32_address_t addr;
- if(get_mode_size_bits(mode) != 8)
+ if (get_mode_size_bits(mode) != 8)
return NULL;
- if(is_Const_1(mux_true) && is_Const_0(mux_false)) {
+ if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
negated = 0;
- } else if(is_Const_0(mux_true) && is_Const_1(mux_false)) {
+ } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
negated = 1;
} else {
return NULL;
return new_node;
}
-static ir_node *try_create_dest_am(ir_node *node) {
+static ir_node *try_create_dest_am(ir_node *node)
+{
ir_node *val = get_Store_value(node);
ir_node *mem = get_Store_mem(node);
ir_node *ptr = get_Store_ptr(node);
ir_node *new_node;
/* handle only GP modes for now... */
- if(!ia32_mode_needs_gp_reg(mode))
+ if (!ia32_mode_needs_gp_reg(mode))
return NULL;
- while(1) {
+ for (;;) {
/* store must be the only user of the val node */
- if(get_irn_n_edges(val) > 1)
+ if (get_irn_n_edges(val) > 1)
return NULL;
/* skip pointless convs */
- if(is_Conv(val)) {
+ if (is_Conv(val)) {
ir_node *conv_op = get_Conv_op(val);
ir_mode *pred_mode = get_irn_mode(conv_op);
if (!ia32_mode_needs_gp_reg(pred_mode))
break;
- if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
+ if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
val = conv_op;
continue;
}
}
/* value must be in the same block */
- if(get_nodes_block(node) != get_nodes_block(val))
+ if (get_nodes_block(node) != get_nodes_block(val))
return NULL;
switch (get_irn_opcode(val)) {
case iro_Add:
op1 = get_Add_left(val);
op2 = get_Add_right(val);
- if(is_Const_1(op2)) {
+ if (is_Const_1(op2)) {
new_node = dest_am_unop(val, op1, mem, ptr, mode,
new_rd_ia32_IncMem);
break;
- } else if(is_Const_Minus_1(op2)) {
+ } else if (is_Const_Minus_1(op2)) {
new_node = dest_am_unop(val, op1, mem, ptr, mode,
new_rd_ia32_DecMem);
break;
return NULL;
}
- if(new_node != NULL) {
- if(get_irn_pinned(new_node) != op_pin_state_pinned &&
+ if (new_node != NULL) {
+ if (get_irn_pinned(new_node) != op_pin_state_pinned &&
get_irn_pinned(node) == op_pin_state_pinned) {
set_irn_pinned(new_node, op_pin_state_pinned);
}
if (mode != mode_Is && mode != mode_Hs)
return 0;
- if(!is_Conv(node))
+ if (!is_Conv(node))
return 0;
conv_op = get_Conv_op(node);
conv_mode = get_irn_mode(conv_op);
- if(!mode_is_float(conv_mode))
+ if (!mode_is_float(conv_mode))
return 0;
return 1;
foreach_out_edge(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
- if(pn == default_pn)
+ if (pn == default_pn)
continue;
- if(pn < switch_min)
+ if (pn < switch_min)
switch_min = pn;
- if(pn > switch_max)
+ if (pn > switch_max)
switch_max = pn;
}
- if((unsigned) (switch_max - switch_min) > 256000) {
+ if ((unsigned) (switch_max - switch_min) > 256000) {
panic("Size of switch %+F bigger than 256000", node);
}
/**
* Transform a Cond node.
*/
-static ir_node *gen_Cond(ir_node *node) {
+static ir_node *gen_Cond(ir_node *node)
+{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_graph *irg = current_ir_graph;
ir_node *new_right;
ir_node *new_node;
- if(ia32_cg_config.use_fucomi) {
+ if (ia32_cg_config.use_fucomi) {
new_right = be_transform_node(right);
new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
new_right, 0);
set_ia32_commutative(new_node);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
} else {
- if(ia32_cg_config.use_ftst && is_Const_0(right)) {
+ if (ia32_cg_config.use_ftst && is_Const_0(right)) {
new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
0);
} else {
foreach_out_edge(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
pn_Cmp pnc = get_Proj_proj(proj);
- if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
+ if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
return false;
}
ia32_address_t *addr = &am.addr;
int cmp_unsigned;
- if(mode_is_float(cmp_mode)) {
+ if (mode_is_float(cmp_mode)) {
if (ia32_cg_config.use_sse2) {
return create_Ucomi(node);
} else {
/**
* Create instruction for an unsigned Difference or Zero.
*/
-static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) {
+static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b)
+{
ir_graph *irg = current_ir_graph;
ir_mode *mode = get_irn_mode(psi);
ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem;
/**
* Create a conversion from x87 state register to general purpose.
*/
-static ir_node *gen_x87_fp_to_gp(ir_node *node) {
+static ir_node *gen_x87_fp_to_gp(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *op = get_Conv_op(node);
ir_node *new_op = be_transform_node(op);
assert(get_mode_size_bits(mode) <= 32);
/* exception we can only store signed 32 bit integers, so for unsigned
we store a 64bit (signed) integer and load the lower bits */
- if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
+ if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
set_ia32_ls_mode(fist, mode_Ls);
} else {
set_ia32_ls_mode(fist, mode_Is);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_ls_mode(load, mode_Is);
- if(get_ia32_ls_mode(fist) == mode_Ls) {
+ if (get_ia32_ls_mode(fist) == mode_Ls) {
ia32_attr_t *attr = get_ia32_attr(load);
attr->data.need_64bit_stackent = 1;
} else {
/**
* Create a conversion from general purpose to x87 register
*/
-static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
+static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
+{
ir_node *src_block = get_nodes_block(node);
ir_node *block = be_transform_node(src_block);
ir_graph *irg = current_ir_graph;
return new_node;
}
}
- if(new_op == NULL) {
+ if (new_op == NULL) {
new_op = be_transform_node(op);
}
set_ia32_ls_mode(store, mode_Iu);
/* exception for 32bit unsigned, do a 64bit spill+load */
- if(!mode_is_signed(mode)) {
+ if (!mode_is_signed(mode)) {
ir_node *in[2];
/* store a zero */
ir_node *zero_const = create_Immediate(NULL, 0, 0);
}
#ifdef DEBUG_libfirm
- if(is_Const(op)) {
+ if (is_Const(op)) {
ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
op);
}
*
* @return The created ia32 Conv node
*/
-static ir_node *gen_Conv(ir_node *node) {
+static ir_node *gen_Conv(ir_node *node)
+{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_node *op = get_Conv_op(node);
new_op = be_transform_node(op);
/* we convert from float ... */
if (mode_is_float(tgt_mode)) {
- if(src_mode == mode_E && tgt_mode == mode_D
+ if (src_mode == mode_E && tgt_mode == mode_D
&& !get_Conv_strict(node)) {
DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
return new_op;
nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
- if(get_Conv_strict(node)) {
+ if (get_Conv_strict(node)) {
res = gen_x87_strict_conv(tgt_mode, new_op);
SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
return res;
set_ia32_ls_mode(res, tgt_mode);
} else {
res = gen_x87_gp_to_fp(node, src_mode);
- if(get_Conv_strict(node)) {
+ if (get_Conv_strict(node)) {
/* The strict-Conv is only necessary, if the int mode has more bits
* than the float mantissa */
size_t int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
}
return res;
}
- } else if(tgt_mode == mode_b) {
+ } else if (tgt_mode == mode_b) {
/* mode_b lowering already took care that we only have 0/1 values */
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
/**
* Transforms a FrameAddr into an ia32 Add.
*/
-static ir_node *gen_be_FrameAddr(ir_node *node) {
+static ir_node *gen_be_FrameAddr(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *op = be_get_FrameAddr_frame(node);
ir_node *new_op = be_transform_node(op);
/**
* In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
*/
-static ir_node *gen_be_Return(ir_node *node) {
+static ir_node *gen_be_Return(ir_node *node)
+{
ir_graph *irg = current_ir_graph;
ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
/**
* Change some phi modes
*/
-static ir_node *gen_Phi(ir_node *node) {
+static ir_node *gen_Phi(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_irn_mode(node);
ir_node *phi;
- if(ia32_mode_needs_gp_reg(mode)) {
+ if (ia32_mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
/* all integer operations are on 32bit registers now */
mode = mode_Iu;
- } else if(mode_is_float(mode)) {
+ } else if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2) {
mode = mode_xmm;
} else {
match_immediate);
}
-static ir_node *gen_ia32_l_Add(ir_node *node) {
+static ir_node *gen_ia32_l_Add(ir_node *node)
+{
ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
match_commutative | match_am | match_immediate |
match_mode_neutral);
- if(is_Proj(lowered)) {
+ if (is_Proj(lowered)) {
lowered = get_Proj_pred(lowered);
} else {
assert(is_ia32_Add(lowered));
*
* @return the created ia32 Mul node
*/
-static ir_node *gen_ia32_l_Mul(ir_node *node) {
+static ir_node *gen_ia32_l_Mul(ir_node *node)
+{
ir_node *left = get_binop_left(node);
ir_node *right = get_binop_right(node);
*
* @return the created ia32 IMul1OP node
*/
-static ir_node *gen_ia32_l_IMul(ir_node *node) {
+static ir_node *gen_ia32_l_IMul(ir_node *node)
+{
ir_node *left = get_binop_left(node);
ir_node *right = get_binop_right(node);
match_commutative | match_am | match_mode_neutral);
}
-static ir_node *gen_ia32_l_Sub(ir_node *node) {
+static ir_node *gen_ia32_l_Sub(ir_node *node)
+{
ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
match_am | match_immediate | match_mode_neutral);
- if(is_Proj(lowered)) {
+ if (is_Proj(lowered)) {
lowered = get_Proj_pred(lowered);
} else {
assert(is_ia32_Sub(lowered));
return lowered;
}
-static ir_node *gen_ia32_l_Sbb(ir_node *node) {
+static ir_node *gen_ia32_l_Sbb(ir_node *node)
+{
return gen_binop_flags(node, new_rd_ia32_Sbb,
match_am | match_immediate | match_mode_neutral);
}
return gen_lowered_64bit_shifts(node, high, low, count);
}
-static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) {
+static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
+{
ir_node *src_block = get_nodes_block(node);
ir_node *block = be_transform_node(src_block);
ir_graph *irg = current_ir_graph;
ir_node *store_low;
ir_node *store_high;
- if(!mode_is_signed(get_irn_mode(val_high))) {
+ if (!mode_is_signed(get_irn_mode(val_high))) {
panic("unsigned long long -> float not supported yet (%+F)", node);
}
return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
}
-static ir_node *gen_ia32_l_FloattoLL(ir_node *node) {
+static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
+{
ir_node *src_block = get_nodes_block(node);
ir_node *block = be_transform_node(src_block);
ir_graph *irg = current_ir_graph;
/**
* the BAD transformer.
*/
-static ir_node *bad_transform(ir_node *node) {
+static ir_node *bad_transform(ir_node *node)
+{
panic("No transform function for %+F available.", node);
return NULL;
}
-static ir_node *gen_Proj_l_FloattoLL(ir_node *node) {
+static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
+{
ir_graph *irg = current_ir_graph;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
/**
* Transform the Projs of an AddSP.
*/
-static ir_node *gen_Proj_be_AddSP(ir_node *node) {
+static ir_node *gen_Proj_be_AddSP(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
pn_ia32_SubSP_stack);
arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
return res;
- } else if(proj == pn_be_AddSP_res) {
+ } else if (proj == pn_be_AddSP_res) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
pn_ia32_SubSP_addr);
} else if (proj == pn_be_AddSP_M) {
/**
* Transform the Projs of a SubSP.
*/
-static ir_node *gen_Proj_be_SubSP(ir_node *node) {
+static ir_node *gen_Proj_be_SubSP(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
/**
* Transform and renumber the Projs from a Load.
*/
-static ir_node *gen_Proj_Load(ir_node *node) {
+static ir_node *gen_Proj_Load(ir_node *node)
+{
ir_node *new_pred;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
/**
* Transform and renumber the Projs from a DivMod like instruction.
*/
-static ir_node *gen_Proj_DivMod(ir_node *node) {
+static ir_node *gen_Proj_DivMod(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
/**
* Transform and renumber the Projs from a CopyB.
*/
-static ir_node *gen_Proj_CopyB(ir_node *node) {
+static ir_node *gen_Proj_CopyB(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
- switch(proj) {
+ switch (proj) {
case pn_CopyB_M_regular:
if (is_ia32_CopyB_i(new_pred)) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
/**
* Transform and renumber the Projs from a Quot.
*/
-static ir_node *gen_Proj_Quot(ir_node *node) {
+static ir_node *gen_Proj_Quot(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
- switch(proj) {
+ switch (proj) {
case pn_Quot_M:
if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
return call;
}
-static ir_node *gen_be_IncSP(ir_node *node) {
+static ir_node *gen_be_IncSP(ir_node *node)
+{
ir_node *res = be_duplicate_node(node);
be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
/**
* Transform and potentially renumber Proj nodes.
*/
-static ir_node *gen_Proj(ir_node *node) {
+static ir_node *gen_Proj(ir_node *node)
+{
ir_node *pred = get_Proj_pred(node);
long proj;
ir_mode *mode = get_irn_mode(node);
ir_node *last_keep;
(void) data;
- if(mode != mode_T)
+ if (mode != mode_T)
return;
- if(!is_ia32_irn(node))
+ if (!is_ia32_irn(node))
return;
n_outs = get_ia32_n_res(node);
- if(n_outs <= 0)
+ if (n_outs <= 0)
return;
- if(is_ia32_SwitchJmp(node))
+ if (is_ia32_SwitchJmp(node))
return;
assert(n_outs < (int) sizeof(unsigned) * 8);
/* are keeps missing? */
last_keep = NULL;
- for(i = 0; i < n_outs; ++i) {
+ for (i = 0; i < n_outs; ++i) {
ir_node *block;
ir_node *in[1];
const arch_register_req_t *req;
const arch_register_class_t *cls;
- if(found_projs & (1 << i)) {
+ if (found_projs & (1 << i)) {
continue;
}
req = get_ia32_out_req(node, i);
cls = req->cls;
- if(cls == NULL) {
+ if (cls == NULL) {
continue;
}
- if(cls == &ia32_reg_classes[CLASS_ia32_flags]) {
+ if (cls == &ia32_reg_classes[CLASS_ia32_flags]) {
continue;
}
block = get_nodes_block(node);
in[0] = new_r_Proj(current_ir_graph, block, node,
arch_register_class_mode(cls), i);
- if(last_keep != NULL) {
+ if (last_keep != NULL) {
be_Keep_add_node(last_keep, cls, in[0]);
} else {
last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in);
- if(sched_is_scheduled(node)) {
+ if (sched_is_scheduled(node)) {
sched_add_after(node, last_keep);
}
}
*
* @return the x87 stack depth
*/
-static int x87_get_depth(const x87_state *state) {
+static int x87_get_depth(const x87_state *state)
+{
return state->depth;
} /* x87_get_depth */
*
* @return the vfp register index that produced the value at st(pos)
*/
-static int x87_get_st_reg(const x87_state *state, int pos) {
+static int x87_get_st_reg(const x87_state *state, int pos)
+{
assert(pos < state->depth);
return state->st[MASK_TOS(state->tos + pos)].reg_idx;
} /* x87_get_st_reg */
*
* @return the IR node that produced the value at st(pos)
*/
-static ir_node *x87_get_st_node(const x87_state *state, int pos) {
+static ir_node *x87_get_st_node(const x87_state *state, int pos)
+{
assert(pos < state->depth);
return state->st[MASK_TOS(state->tos + pos)].node;
} /* x87_get_st_node */
*
* @param state the x87 state
*/
-static void x87_dump_stack(const x87_state *state) {
+static void x87_dump_stack(const x87_state *state)
+{
int i;
for (i = state->depth - 1; i >= 0; --i) {
* @param node the IR node that produces the value of the vfp register
* @param pos the stack position where the new value should be entered
*/
-static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
+static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
+{
assert(0 < state->depth);
state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
state->st[MASK_TOS(state->tos + pos)].node = node;
* @param reg_idx the vfp register index that should be set
* @param node the IR node that produces the value of the vfp register
*/
-static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
+{
x87_set_st(state, reg_idx, node, 0);
} /* x87_set_tos */
* @param state the x87 state
* @param pos the stack position to change the tos with
*/
-static void x87_fxch(x87_state *state, int pos) {
+static void x87_fxch(x87_state *state, int pos)
+{
st_entry entry;
assert(pos < state->depth);
* @return the stack position where the register is stacked
* or -1 if the virtual register was not found
*/
-static int x87_on_stack(const x87_state *state, int reg_idx) {
+static int x87_on_stack(const x87_state *state, int reg_idx)
+{
int i, tos = state->tos;
for (i = 0; i < state->depth; ++i)
* @param reg_idx the register vfp index
* @param node the node that produces the value of the vfp register
*/
-static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
+{
assert(state->depth < N_x87_REGS && "stack overrun");
++state->depth;
* @param node the node that produces the value of the vfp register
* @param dbl_push if != 0 double pushes are allowed
*/
-static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_push(x87_state *state, int reg_idx, ir_node *node)
+{
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
x87_push_dbl(state, reg_idx, node);
*
* @param state the x87 state
*/
-static void x87_pop(x87_state *state) {
+static void x87_pop(x87_state *state)
+{
assert(state->depth > 0 && "stack underrun");
--state->depth;
*
* @param state the x87 state
*/
-static void x87_emms(x87_state *state) {
+static void x87_emms(x87_state *state)
+{
state->depth = 0;
state->tos = 0;
}
*
* @return the block state
*/
-static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
+static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
+{
pmap_entry *entry = pmap_find(sim->blk_states, block);
if (! entry) {
*
* @return a new x87 state
*/
-static x87_state *x87_alloc_state(x87_simulator *sim) {
+static x87_state *x87_alloc_state(x87_simulator *sim)
+{
x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
res->sim = sim;
*
* @return a cloned copy of the src state
*/
-static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
+static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
+{
x87_state *res = x87_alloc_state(sim);
memcpy(res, src, sizeof(*res));
* @param n the IR node to patch
* @param op the x87 opcode to patch in
*/
-static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
+static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
+{
ir_mode *mode = get_irn_mode(n);
ir_node *res = n;
* @param m the desired mode of the Proj
* @return The first Proj of mode @p m found or NULL.
*/
-static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
+static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
+{
const ir_edge_t *edge;
assert(get_irn_mode(n) == mode_T && "Need mode_T node");
/**
* Wrap the arch_* function here so we can check for errors.
*/
-static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
+static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn)
+{
const arch_register_t *res;
res = arch_get_irn_register(sim->arch_env, irn);
*
* @return the fxch node
*/
-static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
+static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
+{
ir_node *fxch;
ia32_x87_attr_t *attr;
* @param pos push st(pos) on stack
* @param op_idx replace input op_idx of n with the fpush result
*/
-static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
+static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
+{
ir_node *fpush, *pred = get_irn_n(n, op_idx);
ia32_x87_attr_t *attr;
const arch_register_t *out = x87_get_irn_register(state->sim, pred);
*
* @return the fldz node
*/
-static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
+static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx)
+{
ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
ir_node *fldz;
* @param lv the liveness handle
* @param block the block
*/
-static void update_liveness(x87_simulator *sim, ir_node *block) {
+static void update_liveness(x87_simulator *sim, ir_node *block)
+{
vfp_liveness live = vfp_liveness_end_of_block(sim, block);
unsigned idx;
ir_node *irn;
*
* @param live the live bitset
*/
-static void vfp_dump_live(vfp_liveness live) {
+static void vfp_dump_live(vfp_liveness live)
+{
int i;
DB((dbg, LEVEL_2, "Live after: "));
*
* @return NO_NODE_ADDED
*/
-static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
+static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
+{
int op2_idx = 0, op1_idx;
int out_idx, do_pop = 0;
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state));
- if(reg_index_1 == REG_VFP_UKNWN) {
+ if (reg_index_1 == REG_VFP_UKNWN) {
op1_idx = 0;
op1_live_after = 1;
} else {
if (reg_index_2 != REG_VFP_NOREG) {
assert(!permuted);
- if(reg_index_2 == REG_VFP_UKNWN) {
+ if (reg_index_2 == REG_VFP_UKNWN) {
op2_idx = 0;
op2_live_after = 1;
} else {
*
* @return NO_NODE_ADDED
*/
-static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
+static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
+{
int op1_idx, out_idx;
x87_simulator *sim = state->sim;
const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
*
* @return NO_NODE_ADDED
*/
-static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
+static int sim_load(x87_state *state, ir_node *n, ir_op *op)
+{
const arch_register_t *out = x87_get_irn_register(state->sim, n);
ia32_x87_attr_t *attr;
* @param old_val The former value
* @param new_val The new value
*/
-static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) {
+static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
+{
const ir_edge_t *edge, *ne;
foreach_out_edge_safe(old_val, edge, ne) {
* @param op the x87 store opcode
* @param op_p the x87 store and pop opcode
*/
-static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
+static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
+{
x87_simulator *sim = state->sim;
ir_node *val = get_irn_n(n, n_ia32_vfst_val);
const arch_register_t *op2 = x87_get_irn_register(sim, val);
op2_reg_idx = arch_register_get_index(op2);
if (op2_reg_idx == REG_VFP_UKNWN) {
/* just take any value from stack */
- if(state->depth > 0) {
+ if (state->depth > 0) {
op2_idx = 0;
DEBUG_ONLY(op2 = NULL);
live_after_node = 1;
* @param state the x87 state
* @param n the node that should be simulated (and patched)
*/
-static int sim_fisttp(x87_state *state, ir_node *n) {
+static int sim_fisttp(x87_state *state, ir_node *n)
+{
x87_simulator *sim = state->sim;
ir_node *val = get_irn_n(n, n_ia32_vfst_val);
const arch_register_t *op2 = x87_get_irn_register(sim, val);
return insn;
} /* sim_fisttp */
-static int sim_FtstFnstsw(x87_state *state, ir_node *n) {
+static int sim_FtstFnstsw(x87_state *state, ir_node *n)
+{
x87_simulator *sim = state->sim;
ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
attr->x87[1] = NULL;
attr->x87[2] = NULL;
- if(!is_vfp_live(reg_index_1, live)) {
+ if (!is_vfp_live(reg_index_1, live)) {
x87_create_fpop(state, sched_next(n), 1);
return NODE_ADDED;
}
* @param state the x87 state
* @param n the node that should be simulated (and patched)
*/
-static int sim_Fucom(x87_state *state, ir_node *n) {
+static int sim_Fucom(x87_state *state, ir_node *n)
+{
int op1_idx;
int op2_idx = -1;
ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
if (is_ia32_vFucomFnstsw(n)) {
int i;
- switch(pops) {
- case 0: dst = op_ia32_FucomFnstsw; break;
- case 1: dst = op_ia32_FucompFnstsw; break;
+ switch (pops) {
+ case 0: dst = op_ia32_FucomFnstsw; break;
+ case 1: dst = op_ia32_FucompFnstsw; break;
case 2: dst = op_ia32_FucomppFnstsw; break;
default: panic("invalid popcount in sim_Fucom");
}
- for(i = 0; i < pops; ++i) {
+ for (i = 0; i < pops; ++i) {
x87_pop(state);
}
- } else if(is_ia32_vFucomi(n)) {
- switch(pops) {
- case 0: dst = op_ia32_Fucomi; break;
+ } else if (is_ia32_vFucomi(n)) {
+ switch (pops) {
+ case 0: dst = op_ia32_Fucomi; break;
case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
case 2:
dst = op_ia32_Fucompi;
}
x87_patch_insn(n, dst);
- if(xchg) {
+ if (xchg) {
int tmp = op1_idx;
op1_idx = op2_idx;
op2_idx = tmp;
DB((dbg, LEVEL_1, ">>> %+F\n", node));
arity = get_irn_arity(node);
- for(i = 0; i < arity; ++i) {
+ for (i = 0; i < arity; ++i) {
op = get_irn_n(node, i);
op_reg = arch_get_irn_register(state->sim->arch_env, op);
- if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
+ if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
continue;
reg_id = arch_register_get_index(op_reg);
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
- if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
+ if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
x87_create_fpop(state, sched_next(node), 1);
node_added = NODE_ADDED;
}
*
* @return the copy of n
*/
-static ir_node *create_Copy(x87_state *state, ir_node *n) {
+static ir_node *create_Copy(x87_state *state, ir_node *n)
+{
x87_simulator *sim = state->sim;
ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
*
* @return NO_NODE_ADDED
*/
-static int sim_Copy(x87_state *state, ir_node *n) {
+static int sim_Copy(x87_state *state, ir_node *n)
+{
x87_simulator *sim = state->sim;
ir_node *pred;
const arch_register_t *out;
exchange(n, node);
sched_add_before(next, node);
- if(get_irn_n_edges(pred) == 0) {
+ if (get_irn_n_edges(pred) == 0) {
keep_float_node_alive(state, pred);
}
/**
* Returns the result proj of the call
*/
-static ir_node *get_call_result_proj(ir_node *call) {
+static ir_node *get_call_result_proj(ir_node *call)
+{
const ir_edge_t *edge;
/* search the result proj */
*
* Should not happen, spills are lowered before x87 simulator see them.
*/
-static int sim_Spill(x87_state *state, ir_node *n) {
+static int sim_Spill(x87_state *state, ir_node *n)
+{
assert(0 && "Spill not lowered");
return sim_fst(state, n);
} /* sim_Spill */
*
* Should not happen, reloads are lowered before x87 simulator see them.
*/
-static int sim_Reload(x87_state *state, ir_node *n) {
+static int sim_Reload(x87_state *state, ir_node *n)
+{
assert(0 && "Reload not lowered");
return sim_fld(state, n);
} /* sim_Reload */
*
* @return NO_NODE_ADDED
*/
-static int sim_Return(x87_state *state, ir_node *n) {
+static int sim_Return(x87_state *state, ir_node *n)
+{
int n_res = be_Return_get_n_rets(n);
int i, n_float_res = 0;
- /* only floating point return values must resist on stack */
+ /* only floating point return values must reside on stack */
for (i = 0; i < n_res; ++i) {
ir_node *res = get_irn_n(n, be_pos_Return_val + i);
*
* @return NO_NODE_ADDED
*/
-static int sim_Perm(x87_state *state, ir_node *irn) {
+static int sim_Perm(x87_state *state, ir_node *irn)
+{
int i, n;
x87_simulator *sim = state->sim;
ir_node *pred = get_irn_n(irn, 0);
return NO_NODE_ADDED;
} /* sim_Perm */
-static int sim_Barrier(x87_state *state, ir_node *node) {
+static int sim_Barrier(x87_state *state, ir_node *node)
+{
//const arch_env_t *arch_env = state->sim->arch_env;
int i, arity;
/* materialize unknown if needed */
arity = get_irn_arity(node);
- for(i = 0; i < arity; ++i) {
+ for (i = 0; i < arity; ++i) {
const arch_register_t *reg;
ir_node *zero;
ir_node *block;
ia32_x87_attr_t *attr;
ir_node *in = get_irn_n(node, i);
- if(!is_ia32_Unknown_VFP(in))
+ if (!is_ia32_Unknown_VFP(in))
continue;
/* TODO: not completely correct... */
*
* @return the x87 state after dead register killed
*/
-static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
+static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
+{
x87_state *state = start_state;
ir_node *first_insn = sched_first(block);
ir_node *keep = NULL;
const arch_register_t *reg;
ia32_x87_attr_t *attr;
- if(!is_Phi(node))
+ if (!is_Phi(node))
break;
op = get_Phi_pred(node, pos);
- if(!is_ia32_Unknown_VFP(op))
+ if (!is_ia32_Unknown_VFP(op))
continue;
reg = arch_get_irn_register(state->sim->arch_env, node);
* @param sim the simulator handle
* @param block the current block
*/
-static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
+static void x87_simulate_block(x87_simulator *sim, ir_node *block)
+{
ir_node *n, *next;
blk_state *bl_state = x87_get_bl_state(sim, block);
x87_state *state = bl_state->begin;
*
* @param sim the simulator handle
*/
-static void x87_destroy_simulator(x87_simulator *sim) {
+static void x87_destroy_simulator(x87_simulator *sim)
+{
pmap_destroy(sim->blk_states);
obstack_free(&sim->obst, NULL);
DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
* Pre-block walker: calculate the liveness information for the block
* and store it into the sim->live cache.
*/
-static void update_liveness_walker(ir_node *block, void *data) {
+static void update_liveness_walker(ir_node *block, void *data)
+{
x87_simulator *sim = data;
update_liveness(sim, block);
} /* update_liveness_walker */
*
* Needs a block-schedule.
*/
-void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
+void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg)
+{
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
x87_destroy_simulator(&sim);
} /* x87_simulate_graph */
-void ia32_init_x87(void) {
+void ia32_init_x87(void)
+{
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
} /* ia32_init_x87 */
projects / libfirm / commitdiff