Give some node inputs more meaningful names.

[r19369]

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 921055a..5350e2b 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -606,7 +606,7 @@ Sub => {
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ],
                       out => [ "in_r4", "flags", "none" ] },
-       ins       => [ "base", "index", "mem", "left", "right" ],
+       ins       => [ "base", "index", "mem", "minuend", "subtrahend" ],
        outs      => [ "res", "flags", "M" ],
        am        => "source,binary",
        emit      => '. sub%M %binop',
@@ -620,7 +620,7 @@ SubMem => {
        irn_flags => "R",
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
-       ins       => [ "base", "index", "mem", "val" ],
+       ins       => [ "base", "index", "mem", "subtrahend" ],
        emit      => '. sub%M %SI3, %AM',
        units     => [ "GP" ],
        latency   => 1,
@@ -632,7 +632,7 @@ SubMem8Bit => {
        irn_flags => "R",
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
-       ins       => [ "base", "index", "mem", "val" ],
+       ins       => [ "base", "index", "mem", "subtrahend" ],
        emit      => '. sub%M %SB3, %AM',
        units     => [ "GP" ],
        latency   => 1,
@@ -644,7 +644,7 @@ Sbb => {
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
                       out => [ "in_r4 !in_r5", "flags", "none" ] },
-       ins       => [ "base", "index", "mem", "left", "right", "eflags" ],
+       ins       => [ "base", "index", "mem", "minuend", "subtrahend", "eflags" ],
        outs      => [ "res", "flags", "M" ],
        am        => "source,binary",
        emit      => '. sbb%M %binop',
@@ -656,12 +656,12 @@ Sbb => {
 
 l_Sub => {
        reg_req   => { in => [ "none", "none" ], out => [ "none" ] },
-       ins       => [ "left", "right" ],
+       ins       => [ "minuend", "subtrahend" ],
 },
 
 l_Sbb => {
        reg_req   => { in => [ "none", "none", "none" ], out => [ "none" ] },
-       ins       => [ "left", "right", "eflags" ],
+       ins       => [ "minuend", "subtrahend", "eflags" ],
 },
 
 IDiv => {
@@ -914,6 +914,7 @@ Inc => {
        irn_flags => "R",
        reg_req   => { in => [ "gp" ],
                       out => [ "in_r1", "flags" ] },
+       ins       => [ "val" ],
        outs      => [ "res", "flags" ],
        emit      => '. inc %S0',
        units     => [ "GP" ],
@@ -938,6 +939,7 @@ Dec => {
        irn_flags => "R",
        reg_req   => { in => [ "gp" ],
                       out => [ "in_r1", "flags" ] },
+       ins       => [ "val" ],
        outs      => [ "res", "flags" ],
        emit      => '. dec %S0',
        units     => [ "GP" ],
@@ -1287,7 +1289,7 @@ FnstCWNOP => {
 Cltd => {
        # we should not rematrialize this node. It has very strict constraints.
        reg_req   => { in => [ "eax", "edx" ], out => [ "edx" ] },
-       ins       => [ "val", "globbered" ],
+       ins       => [ "val", "clobbered" ],
        emit      => '. cltd',
        latency   => 1,
        mode      => $mode_gp,
@@ -1625,7 +1627,7 @@ xSub => {
        irn_flags => "R",
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
-       ins       => [ "base", "index", "mem", "left", "right" ],
+       ins       => [ "base", "index", "mem", "minuend", "subtrahend" ],
        am        => "source,binary",
        emit      => '. sub%XXM %binop',
        latency   => 4,
@@ -1637,7 +1639,7 @@ xDiv => {
        irn_flags => "R",
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
-       ins       => [ "base", "index", "mem", "left", "right" ],
+       ins       => [ "base", "index", "mem", "dividend", "divisor" ],
        am        => "source,binary",
        outs      => [ "res", "M" ],
        emit      => '. div%XXM %binop',
@@ -1868,7 +1870,7 @@ vfsub => {
 #      irn_flags => "R",
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
-       ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
+       ins       => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ],
        am        => "source,binary",
        latency   => 4,
        units     => [ "VFP" ],
@@ -1879,7 +1881,7 @@ vfsub => {
 vfdiv => {
        state     => "exc_pinned",
        reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] },
-       ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
+       ins       => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ],
        am        => "source,binary",
        outs      => [ "res", "M" ],
        latency   => 20,

diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c
index 60814e5..e9e940f 100644 (file)
--- a/ir/be/ia32/ia32_transform.c
+++ b/ir/be/ia32/ia32_transform.c
@@ -935,12 +935,12 @@ enum {
        n_ia32_l_binop_right,
        n_ia32_l_binop_eflags
 };
-COMPILETIME_ASSERT(n_ia32_l_binop_left   == n_ia32_l_Adc_left,   n_Adc_left)
-COMPILETIME_ASSERT(n_ia32_l_binop_right  == n_ia32_l_Adc_right,  n_Adc_right)
-COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
-COMPILETIME_ASSERT(n_ia32_l_binop_left   == n_ia32_l_Sbb_left,   n_Sbb_left)
-COMPILETIME_ASSERT(n_ia32_l_binop_right  == n_ia32_l_Sbb_right,  n_Sbb_right)
-COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
+COMPILETIME_ASSERT(n_ia32_l_binop_left   == n_ia32_l_Adc_left,       n_Adc_left)
+COMPILETIME_ASSERT(n_ia32_l_binop_right  == n_ia32_l_Adc_right,      n_Adc_right)
+COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags,     n_Adc_eflags)
+COMPILETIME_ASSERT(n_ia32_l_binop_left   == n_ia32_l_Sbb_minuend,    n_Sbb_minuend)
+COMPILETIME_ASSERT(n_ia32_l_binop_right  == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
+COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags,     n_Sbb_eflags)
 
 /**
  * Construct a binary operation which also consumes the eflags.
@@ -4222,8 +4222,8 @@ static ir_node *gen_ia32_l_IMul(ir_node *node) {
 }
 
 static ir_node *gen_ia32_l_Sub(ir_node *node) {
-       ir_node *left    = get_irn_n(node, n_ia32_l_Sub_left);
-       ir_node *right   = get_irn_n(node, n_ia32_l_Sub_right);
+       ir_node *left    = get_irn_n(node, n_ia32_l_Sub_minuend);
+       ir_node *right   = get_irn_n(node, n_ia32_l_Sub_subtrahend);
        ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
                        match_am | match_immediate | match_mode_neutral);