state => "pinned",
op_flags => "L|X|Y",
reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
outs => [ "false", "true" ],
+ attr => "long pnc",
+ init_attr => "attr->pn_code = pnc;",
latency => 5,
units => [ "SSE" ],
},
vfCondJmp => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
+ reg_req => { in => [ "vfp", "vfp" ], out => [ "none", "none", "eax" ] },
+ ins => [ "left", "right" ],
outs => [ "false", "true", "temp_reg_eax" ],
+ attr => "long pnc",
+ init_attr => "attr->attr.pn_code = pnc;",
latency => 10,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
if (mode_is_float(cmp_mode)) {
FP_USED(env_cg);
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
- set_ia32_pncode(res, pnc);
+ res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
+ cmp_b, nomem, pnc);
+ set_ia32_commutative(res);
+ set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
set_ia32_ls_mode(res, cmp_mode);
} else {
ir_node *proj_eax;
- res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
- set_ia32_pncode(res, pnc);
- proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
- be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
+ res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
+ set_ia32_commutative(res);
+ proj_eax = new_r_Proj(irg, block, res, mode_Iu,
+ pn_ia32_vfCondJmp_temp_reg_eax);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
+ &proj_eax);
}
} else {
assert(get_mode_size_bits(cmp_mode) == 32);
res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
new_cmp_a, new_cmp_b, nomem, pnc);
set_ia32_commutative(res);
+ set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
}
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
-
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
return res;
ia32_x87_attr_t *attr;
ir_op *dst;
x87_simulator *sim = state->sim;
- const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
- const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2));
+ ir_node *op1_node = get_irn_n(n, n_ia32_vfCondJmp_left);
+ ir_node *op2_node = get_irn_n(n, n_ia32_vfCondJmp_right);
+ const arch_register_t *op1 = x87_get_irn_register(sim, op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(sim, op2_node);
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
unsigned live = vfp_live_args_after(sim, n, 0);