- change float nodes to mode_E

- correctly capture spills and reloads in coalescer code

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index c894e2f..5aba4cf 100644 (file)
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -77,6 +77,7 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
 {
        ir_node *block, *res;
        ir_node *startnode;
+       ir_node *in[1];
 
        if(*place != NULL)
                return *place;
@@ -87,10 +88,17 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
        *place = res;
 
        startnode = get_irg_start(cg->irg);
+       /* make sure we get scheduled very early... */
+       add_irn_dep(startnode, res);
+       /* schedule the node if we already have a schedule program */
        if(sched_is_scheduled(startnode)) {
                sched_add_before(startnode, res);
        }
 
+       /* keep the node so it isn't accidently removed when unused ... */
+       in[0] = res;
+       be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
+
        return res;
 }
 
@@ -758,28 +766,21 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
        return inverse;
 }
 
+static ir_mode *get_spill_mode_mode(const ir_mode *mode)
+{
+       if(mode_is_float(mode))
+               return mode_D;
+
+       return mode_Iu;
+}
+
 /**
  * Get the mode that should be used for spilling value node
  */
-static ir_mode *get_spill_mode(ia32_code_gen_t *cg, const ir_node *node)
+static ir_mode *get_spill_mode(const ir_node *node)
 {
        ir_mode *mode = get_irn_mode(node);
-       if (mode_is_float(mode)) {
-#if 0
-               // super exact spilling...
-               if (USE_SSE2(cg))
-                       return mode_D;
-               else
-                       return mode_E;
-#else
-               return mode_D;
-#endif
-       }
-       else
-               return mode_Is;
-
-       assert(0);
-       return mode;
+       return get_spill_mode_mode(mode);
 }
 
 /**
@@ -803,11 +804,9 @@ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spil
  * @return Non-Zero if operand can be loaded
  */
 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
-       const ia32_irn_ops_t *ops = self;
-       ia32_code_gen_t      *cg  = ops->cg;
        ir_node *op = get_irn_n(irn, i);
        const ir_mode *mode = get_irn_mode(op);
-       const ir_mode *spillmode = get_spill_mode(cg, op);
+       const ir_mode *spillmode = get_spill_mode(op);
 
        if (! is_ia32_irn(irn)                            ||  /* must be an ia32 irn */
                get_irn_arity(irn) != 5                       ||  /* must be a binary operation */
@@ -1032,7 +1031,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
        ir_node *block       = get_nodes_block(node);
        ir_entity *ent       = be_get_frame_entity(node);
        ir_mode *mode        = get_irn_mode(node);
-       ir_mode *spillmode   = get_spill_mode(cg, node);
+       ir_mode *spillmode   = get_spill_mode(node);
        ir_node *noreg       = ia32_new_NoReg_gp(cg);
        ir_node *sched_point = NULL;
        ir_node *ptr         = get_irg_frame(irg);
@@ -1089,7 +1088,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
        ir_node *block = get_nodes_block(node);
        ir_entity *ent = be_get_frame_entity(node);
        const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
-       ir_mode *mode  = get_spill_mode(cg, spillval);
+       ir_mode *mode  = get_spill_mode(spillval);
        ir_node *noreg = ia32_new_NoReg_gp(cg);
        ir_node *nomem = new_rd_NoMem(irg);
        ir_node *ptr   = get_irg_frame(irg);
@@ -1302,12 +1301,12 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
        be_fec_env_t *env = data;
 
        if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
-               const ir_mode *mode = get_irn_mode(node);
+               const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
                int align = get_mode_size_bytes(mode);
                be_node_needs_frame_entity(env, node, mode, align);
        } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
                  && is_ia32_use_frame(node)) {
-               if (is_ia32_Load(node)) {
+               if (is_ia32_got_reload(node) || is_ia32_Load(node)) {
                        const ir_mode *mode = get_ia32_ls_mode(node);
                        int align = get_mode_size_bytes(mode);
                        be_node_needs_frame_entity(env, node, mode, align);

diff --git a/ir/be/ia32/ia32_emitter.c b/ir/be/ia32/ia32_emitter.c
index 377fe6b..2e2f348 100644 (file)
--- a/ir/be/ia32/ia32_emitter.c
+++ b/ir/be/ia32/ia32_emitter.c
@@ -375,6 +375,13 @@ void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
        ia32_emit_char(env, get_mode_suffix(mode));
 }
 
+void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
+{
+       ir_mode *mode = get_ia32_ls_mode(node);
+       if(mode != NULL)
+               ia32_emit_mode_suffix(env, mode);
+}
+
 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
 {
        if(get_mode_size_bits(mode) == 32)
@@ -930,7 +937,7 @@ static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
        ia32_emit_cstring(env, "\tsahf");
        ia32_emit_finish_line(env, node);
 
-       finish_CondJmp(env, node, mode_D, pnc);
+       finish_CondJmp(env, node, mode_E, pnc);
 }
 
 static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {

diff --git a/ir/be/ia32/ia32_emitter.h b/ir/be/ia32/ia32_emitter.h
index 68d3157..fcee39d 100644 (file)
--- a/ir/be/ia32/ia32_emitter.h
+++ b/ir/be/ia32/ia32_emitter.h
@@ -49,6 +49,7 @@ void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos)
 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos);
 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node);
 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode);
+void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node);
 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode);
 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node);
 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node);

diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c
index a3cf361..1b6f2dc 100644 (file)
--- a/ir/be/ia32/ia32_finish.c
+++ b/ir/be/ia32/ia32_finish.c
@@ -330,7 +330,7 @@ insert_copy:
                                set_irn_n(irn, idx1, get_irn_n(irn, idx2));
                                set_irn_n(irn, idx2, tmp);
 
-                               set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D));
+                               set_ia32_pncode(irn, get_negated_pnc(pnc, mode_E));
                        }
                }
 

diff --git a/ir/be/ia32/ia32_intrinsics.c b/ir/be/ia32/ia32_intrinsics.c
index 7d492bf..738b667 100644 (file)
--- a/ir/be/ia32/ia32_intrinsics.c
+++ b/ir/be/ia32/ia32_intrinsics.c
@@ -376,7 +376,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
        set_ia32_use_frame(fa);
        set_ia32_ls_mode(fa, mode_D);
        fa_mem = new_r_Proj(irg, block, fa, mode_M, pn_ia32_l_vfild_M);
-       fa     = new_r_Proj(irg, block, fa, mode_D, pn_ia32_l_vfild_res);
+       fa     = new_r_Proj(irg, block, fa, mode_E, pn_ia32_l_vfild_res);
 
        /* store second arg */
        store_l   = new_rd_ia32_l_Store(dbg, irg, block, frame, b_l, get_irg_no_mem(irg));
@@ -400,7 +400,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
        set_ia32_use_frame(fb);
        set_ia32_ls_mode(fb, mode_D);
        fb_mem = new_r_Proj(irg, block, fb, mode_M, pn_ia32_l_vfild_M);
-       fb     = new_r_Proj(irg, block, fb, mode_D, pn_ia32_l_vfild_res);
+       fb     = new_r_Proj(irg, block, fb, mode_E, pn_ia32_l_vfild_res);
 
        op_mem[0] = fa_mem;
        op_mem[1] = fb_mem;
@@ -411,10 +411,10 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
        switch (dmtp) {
                case IA32_INTRINSIC_DIV:
                        fres = new_rd_ia32_l_vfdiv(dbg, irg, block, fa, fb);
-                       fres = new_rd_Proj(dbg, irg, block, fres, mode_D, pn_ia32_l_vfdiv_res);
+                       fres = new_rd_Proj(dbg, irg, block, fres, mode_E, pn_ia32_l_vfdiv_res);
                        break;
                case IA32_INTRINSIC_MOD:
-                       fres = new_rd_ia32_l_vfprem(dbg, irg, block, fa, fb, mode_D);
+                       fres = new_rd_ia32_l_vfprem(dbg, irg, block, fa, fb, mode_E);
                        break;
                default:
                        assert(0);

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index 8a119a2..4636443 100644 (file)
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -289,7 +289,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
        for( ; i >= 0; --i) {
                const arch_register_t *spreg;
                ir_node *push;
-               ir_node *val, *mem;
+               ir_node *val, *mem, *mem_proj;
                ir_node *store = stores[i];
                ir_node *noreg = ia32_new_NoReg_gp(cg);
 
@@ -313,14 +313,14 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
                arch_set_irn_register(cg->arch_env, curr_sp, spreg);
                sched_add_before(irn, curr_sp);
 
-               // rewire users
-               edges_reroute(store, push, irg);
+               // create memory proj
+               mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
+               sched_add_before(irn, mem_proj);
+
+               // use the memproj now
+               exchange(store, mem_proj);
 
                // we can remove the store now
-               set_irn_n(store, 0, new_Bad());
-               set_irn_n(store, 1, new_Bad());
-               set_irn_n(store, 2, new_Bad());
-               set_irn_n(store, 3, new_Bad());
                sched_remove(store);
 
                offset -= 4;

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 227272d..409b1d4 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -113,7 +113,7 @@ $arch = "ia32";
                { "name" => "edi", "type" => 2 },
                { "name" => "ebp", "type" => 2 },
                { "name" => "esp", "type" => 4 },
-               { "name" => "gp_NOREG", "type" => 4 | 16 },     # we need a dummy register for NoReg nodes
+               { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
                { "name" => "gp_UKNWN", "type" => 4 | 8 | 16},  # we need a dummy register for Unknown nodes
                { "mode" => "mode_Iu" }
        ],
@@ -126,9 +126,9 @@ $arch = "ia32";
                { "name" => "xmm5", "type" => 1 },
                { "name" => "xmm6", "type" => 1 },
                { "name" => "xmm7", "type" => 1 },
-               { "name" => "xmm_NOREG", "type" => 4 | 16 },     # we need a dummy register for NoReg nodes
+               { "name" => "xmm_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
                { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16},  # we need a dummy register for Unknown nodes
-               { "mode" => "mode_D" }
+               { "mode" => "mode_E" }
        ],
        "vfp" => [
                { "name" => "vf0", "type" => 1 | 16 },
@@ -139,9 +139,9 @@ $arch = "ia32";
                { "name" => "vf5", "type" => 1 | 16 },
                { "name" => "vf6", "type" => 1 | 16 },
                { "name" => "vf7", "type" => 1 | 16 },
-               { "name" => "vfp_NOREG", "type" => 4 | 16 },     # we need a dummy register for NoReg nodes
+               { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
                { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16},  # we need a dummy register for Unknown nodes
-               { "mode" => "mode_D" }
+               { "mode" => "mode_E" }
        ],
        "st" => [
                { "name" => "st0", "type" => 1 },
@@ -199,6 +199,7 @@ $arch = "ia32";
        "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
        ${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
        "M"  => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
+       "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
        "AM" => "${arch}_emit_am(env, node);",
        "unop" => "${arch}_emit_unop(env, node);",
        "binop" => "${arch}_emit_binop(env, node);",
@@ -717,7 +718,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp_UKNWN" ] },
   "units"     => [],
   "emit"      => "",
-  "mode"      => "mode_D"
+  "mode"      => "mode_E"
 },
 
 "Unknown_XMM" => {
@@ -727,7 +728,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "xmm_UKNWN" ] },
   "units"     => [],
   "emit"      => "",
-  "mode"      => "mode_D"
+  "mode"      => "mode_E"
 },
 
 "NoReg_GP" => {
@@ -747,7 +748,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp_NOREG" ] },
   "units"     => [],
   "emit"      => "",
-  "mode"      => "mode_D"
+  "mode"      => "mode_E"
 },
 
 "NoReg_XMM" => {
@@ -757,7 +758,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "xmm_NOREG" ] },
   "units"     => [],
   "emit"      => "",
-  "mode"      => "mode_D"
+  "mode"      => "mode_E"
 },
 
 "ChangeCW" => {
@@ -944,7 +945,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. adds%M %binop',
   "latency"   => 4,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xMul" => {
@@ -954,7 +955,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. muls%M %binop',
   "latency"   => 4,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xMax" => {
@@ -964,7 +965,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. maxs%M %binop',
   "latency"   => 2,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xMin" => {
@@ -974,7 +975,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. mins%M %binop',
   "latency"   => 2,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xAnd" => {
@@ -984,7 +985,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. andp%M %binop',
   "latency"   => 3,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xOr" => {
@@ -993,7 +994,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. orp%M %binop',
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xXor" => {
@@ -1003,7 +1004,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. xorp%M %binop',
   "latency"   => 3,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 # not commutative operations
@@ -1015,7 +1016,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. andnp%M %binop',
   "latency"   => 3,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xSub" => {
@@ -1025,7 +1026,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. subs%M %binop',
   "latency"   => 4,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xDiv" => {
@@ -1046,7 +1047,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
   "latency"   => 3,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "xCondJmp" => {
@@ -1066,7 +1067,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "emit"      => '. movs%M %D1, $%C',
   "latency"   => 2,
   "units"     => [ "SSE" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 # Load / Store
@@ -1183,7 +1184,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "comment"  => "construct Conv Int -> Floating Point",
   "latency"  => 10,
   "units"    => [ "SSE" ],
-  "mode"     => "mode_D",
+  "mode"     => "mode_E",
 },
 
 "Conv_FP2I" => {
@@ -1199,7 +1200,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "comment"  => "construct Conv Floating Point -> Floating Point",
   "latency"  => 8,
   "units"    => [ "SSE" ],
-  "mode"     => "mode_D",
+  "mode"     => "mode_E",
 },
 
 "CmpCMov" => {
@@ -1280,7 +1281,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
   "latency"   => 10,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 #----------------------------------------------------------#
@@ -1303,7 +1304,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfmul" => {
@@ -1312,7 +1313,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "l_vfmul" => {
@@ -1328,7 +1329,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "l_vfsub" => {
@@ -1357,7 +1358,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "latency"   => 20,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "l_vfprem" => {
@@ -1372,7 +1373,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
   "latency"   => 2,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfchs" => {
@@ -1381,7 +1382,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
   "latency"   => 2,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfsin" => {
@@ -1390,7 +1391,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
   "latency"   => 150,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfcos" => {
@@ -1399,7 +1400,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
   "latency"   => 150,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfsqrt" => {
@@ -1408,7 +1409,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
   "latency"   => 30,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 # virtual Load and Store
@@ -1474,7 +1475,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfld1" => {
@@ -1483,7 +1484,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfldpi" => {
@@ -1492,7 +1493,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfldln2" => {
@@ -1501,7 +1502,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfldlg2" => {
@@ -1510,7 +1511,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfldl2t" => {
@@ -1519,7 +1520,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfldl2e" => {
@@ -1528,7 +1529,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 4,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 "vfConst" => {
@@ -1539,7 +1540,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "reg_req"   => { "out" => [ "vfp" ] },
   "latency"   => 3,
   "units"     => [ "VFP" ],
-  "mode"      => "mode_D",
+  "mode"      => "mode_E",
 },
 
 # other
@@ -1566,7 +1567,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "rd_constructor" => "NONE",
   "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fadd %x87_binop',
+  "emit"      => '. fadd%XM %x87_binop',
 },
 
 "faddp" => {
@@ -1582,7 +1583,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fmul %x87_binop',
+  "emit"      => '. fmul%XM %x87_binop',
 },
 
 "fmulp" => {
@@ -1598,7 +1599,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
   "reg_req"   => { },
-  "emit"      => '. fsub %x87_binop',
+  "emit"      => '. fsub%XM %x87_binop',
 },
 
 "fsubp" => {
@@ -1615,7 +1616,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "irn_flags" => "R",
   "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
   "reg_req"   => { },
-  "emit"      => '. fsubr %x87_binop',
+  "emit"      => '. fsubr%XM %x87_binop',
 },
 
 "fsubrp" => {
@@ -1650,7 +1651,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Div: Div(a, b) = a / b",
   "reg_req"   => { },
-  "emit"      => '. fdiv %x87_binop',
+  "emit"      => '. fdiv%XM %x87_binop',
 },
 
 "fdivp" => {
@@ -1666,7 +1667,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
   "reg_req"   => { },
-  "emit"      => '. fdivr %x87_binop',
+  "emit"      => '. fdivr%XM %x87_binop',
 },
 
 "fdivrp" => {

diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c
index ae3ccf2..008168e 100644 (file)
--- a/ir/be/ia32/ia32_transform.c
+++ b/ir/be/ia32/ia32_transform.c
@@ -271,7 +271,7 @@ static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
                                set_ia32_op_type(load, ia32_AddrModeS);
                                set_ia32_am_flavour(load, ia32_am_N);
                                set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
-                               res       = new_r_Proj(irg, block, load, mode_D, pn_ia32_vfld_res);
+                               res       = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
                        }
                } else {
                        floatent = get_entity_for_tv(env->cg, node);
@@ -281,7 +281,7 @@ static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
                        set_ia32_op_type(load, ia32_AddrModeS);
                        set_ia32_am_flavour(load, ia32_am_N);
                        set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
-                       res = new_r_Proj(irg, block, load, mode_D, pn_ia32_xLoad_res);
+                       res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
                }
 
                set_ia32_ls_mode(load, mode);
@@ -388,7 +388,7 @@ static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
 
        ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
        set_ia32_am_support(conv, ia32_am_Source);
-       set_ia32_ls_mode(conv, mode_D);
+       set_ia32_ls_mode(conv, mode_E);
        SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
 
        return conv;
@@ -2039,8 +2039,8 @@ static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
 
                        /* in case the compare operands are int, we move them into xmm register */
                        if (! mode_is_float(get_irn_mode(cmp_a))) {
-                               new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_D);
-                               new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_D);
+                               new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E);
+                               new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E);
 
                                pnc |= 8;  /* transform integer compare to fp compare */
                        }
@@ -2416,7 +2416,7 @@ static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
                        pn_res = pn_ia32_vfld_res;
                }
 
-               proj_mode = mode_D;
+               proj_mode = mode_E;
        } else {
                new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
                proj_mode = mode_Iu;
@@ -2687,7 +2687,7 @@ static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
        }
 
        assert(get_method_n_ress(tp) == 1);
-       mode = mode_D;
+       mode = mode_E;
 
        pn_ret_val = get_Proj_proj(ret_val);
        pn_ret_mem = get_Proj_proj(ret_mem);
@@ -2726,7 +2726,7 @@ static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
        set_ia32_am_support(fld, ia32_am_Source);
 
        mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
-       fld   = new_r_Proj(irg, block, fld, mode_D, pn_ia32_SetST0_res);
+       fld   = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
        arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
 
        /* create a new barrier */
@@ -2847,8 +2847,8 @@ static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
                mode = mode_Iu;
        } else if(mode_is_float(mode)) {
                assert(mode == mode_D || mode == mode_F);
-               // all float operations are on mode_D registers
-               mode = mode_D;
+               // all float operations are on mode_E registers
+               mode = mode_E;
        }
 
        /* phi nodes allow loops, so we use the old arguments for now
@@ -3234,7 +3234,7 @@ static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
        set_ia32_am_support(res, ia32_am_Source);
        set_ia32_am_flavour(res, ia32_B);
        set_ia32_op_type(res, ia32_AddrModeS);
-       res = new_rd_Proj(dbg, irg, block, res, mode_D, pn_ia32_xLoad_res);
+       res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res);
 
        return res;
 }
@@ -3438,13 +3438,13 @@ static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
                }
        } else if(is_ia32_xLoad(new_pred)) {
                if(proj == pn_Load_res) {
-                       return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_xLoad_res);
+                       return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
                } else if(proj == pn_Load_M) {
                        return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
                }
        } else if(is_ia32_vfld(new_pred)) {
                if(proj == pn_Load_res) {
-                       return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfld_res);
+                       return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
                } else if(proj == pn_Load_M) {
                        return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
                }
@@ -3551,7 +3551,7 @@ static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
        case pn_ia32_l_vfdiv_M:
                return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
        case pn_ia32_l_vfdiv_res:
-               return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfdiv_res);
+               return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
        default:
                assert(0);
        }