}
/**
- * Generate the prologue.
+ * Generate the routine prologue.
* @param self The callback object.
* @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
* @return The register which shall be used as a stack frame base.
*
* All nodes which define registers in @p reg_map must keep @p reg_map current.
ir_node *push;
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem, mode_T);
- curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), 0);
- *mem = new_r_Proj(env->irg, bl, push, mode_M, 1);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
+ curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
+ *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
/* the push must have SP out register */
- arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ set_ia32_flags(push, arch_irn_flags_ignore);
/* move esp to ebp */
curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
return env->isa->sp;
}
+/**
+ * Generate the routine epilogue.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
+ */
static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
ia32_abi_env_t *env = self;
ir_mode *mode_bp = env->isa->bp->reg_class->mode;
int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
+ /* AMD processors prefer leave at the end of a routine */
if (ARCH_AMD(isa->opt_arch)) {
ir_node *leave;
/* leave */
- leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem, mode_T);
+ leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
set_ia32_flags(leave, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, 0);
- curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), 1);
- *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, 2);
+ curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+ *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
}
else {
ir_node *pop;
curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
/* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem, mode_T);
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
set_ia32_flags(pop, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, 0);
- curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), 1);
- *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, 2);
+ curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
+ curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+ *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
}
arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
else
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
set_ia32_am_support(new_op, ia32_am_Source);
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
else
- new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
set_ia32_am_support(new_op, ia32_am_Dest);
DBG_OPT_SPILL2ST(irn, new_op);
- proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
if (sched_point) {
sched_add_after(sched_point, new_op);
bl = get_nodes_block(irn);
push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
- be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp), mode_T);
- proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), 0);
- proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, 1);
+ be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
+ proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
+ proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
/* the push must have SP out register */
arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
reg = arch_get_irn_register(cg->arch_env, load);
sp = arch_get_irn_register(cg->arch_env, irn);
- pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2), mode_T);
- proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), 0);
- proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), 1);
- proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, 2);
+ pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
+ proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
+ proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
+ proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
exchange(old_proj_M, proj_M);
exchange(old_proj_res, proj_res);
# for i = 1 .. arity: ir_node *op_i
# ir_mode *mode
#
+# outs: if a node defines more than one output, the names of the projections
+# nodes having outs having automatically the mode mode_T
+#
# comment: OPTIONAL comment for the node constructor
#
# rd_constructor: for every operation there will be a
# |_| #
#--------------------------------------------------#
+%operands = (
+);
+
%nodes = (
#-----------------------------------------------------------------#
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Mul" => {
"comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
+ "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
"comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
- "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */'
+ "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
+ "outs" => [ "EAX", "EDX", "M" ],
},
"And" => {
"comment" => "construct And: And(a, b) = And(b, a) = a AND b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
+ "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Or" => {
"comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
+ "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Eor" => {
"comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
+ "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Max" => {
"comment" => "construct Sub: Sub(a, b) = a - b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
+ "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"DivMod" => {
else {
4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
-'
+',
+ "outs" => [ "div_res", "mod_res", "M" ],
},
"Shl" => {
"comment" => "construct Shl: Shl(a, b) = a << b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
+ "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Shr" => {
"comment" => "construct Shr: Shr(a, b) = a >> b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
+ "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Shrs" => {
"comment" => "construct Shrs: Shrs(a, b) = a >> b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
+ "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"RotR" => {
"comment" => "construct RotR: RotR(a, b) = a ROTR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
+ "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"RotL" => {
"comment" => "construct RotL: RotL(a, b) = a ROTL b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
+ "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# unary operations
"comment" => "construct Minus: Minus(a) = -a",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
+ "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
"Inc" => {
"comment" => "construct Increment: Inc(a) = a++",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
+ "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
"Dec" => {
"comment" => "construct Decrement: Dec(a) = a--",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
+ "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
"Not" => {
"comment" => "construct Not: Not(a) = !a",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
+ "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
# other operations
"comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
+ "outs" => [ "false", "true" ],
},
"TestJmp" => {
"comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
"reg_req" => { "in" => [ "gp", "gp" ] },
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "outs" => [ "false", "true" ],
},
"CJmpAM" => {
"comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
+ "outs" => [ "false", "true" ],
},
"CJmp" => {
"irn_flags" => "R",
"comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
"reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
- "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
+ "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
+ "outs" => [ "EAX", "EDX" ],
},
# Load / Store
else {
4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
}
-'
+',
+ "outs" => [ "res", "M" ],
},
"Store" => {
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
- "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
+ "outs" => [ "M" ],
},
"Store8Bit" => {
"comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
- "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
+ "outs" => [ "M" ],
},
"Lea" => {
"Push" => {
"comment" => "push a gp register on the stack",
- "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. push %S2 /* Push(%A2) */'
+ "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
+ "emit" => '. push %S2 /* Push(%A2) */',
+ "outs" => [ "stack", "M" ],
},
"Pop" => {
"comment" => "pop a gp register from the stack",
"reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
- "emit" => '. pop %D1 /* Pop -> %D1 */'
+ "emit" => '. pop %D1 /* Pop -> %D1 */',
+ "outs" => [ "res", "stack", "M" ],
},
"Enter" => {
"comment" => "create stack frame",
"reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
- "emit" => '. enter /* Enter */'
+ "emit" => '. enter /* Enter */',
+ "outs" => [ "frame", "stack", "M" ],
},
"Leave" => {
"comment" => "destroy stack frame",
"reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
- "emit" => '. leave /* Leave */'
+ "emit" => '. leave /* Leave */',
+ "outs" => [ "frame", "stack", "M" ],
},
#-----------------------------------------------------------------------------#
"comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
+ "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xMul" => {
"comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
+ "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xMax" => {
"comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
+ "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xMin" => {
"comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
+ "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xAnd" => {
"comment" => "construct SSE And: And(a, b) = a AND b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
+ "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xOr" => {
"comment" => "construct SSE Or: Or(a, b) = a OR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
+ "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xEor" => {
"comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
+ "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# not commutative operations
"comment" => "construct SSE Sub: Sub(a, b) = a - b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
+ "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xDiv" => {
"comment" => "construct SSE Div: Div(a, b) = a / b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
+ "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# other operations
"comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
+ "outs" => [ "false", "true" ],
},
"xConst" => {
"comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
- "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
+ "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xStore" => {
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
- "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
+ "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
+ "outs" => [ "M" ],
},
# CopyB
"Conv_I2I" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Int -> Int"
+ "comment" => "construct Conv Int -> Int",
+ "outs" => [ "res", "M" ],
},
"Conv_I2I8Bit" => {
"reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Int -> Int"
+ "comment" => "construct Conv Int -> Int",
+ "outs" => [ "res", "M" ],
},
"Conv_I2FP" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Int -> Floating Point"
+ "comment" => "construct Conv Int -> Floating Point",
+ "outs" => [ "res", "M" ],
},
"Conv_FP2I" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Floating Point -> Int"
+ "comment" => "construct Conv Floating Point -> Int",
+ "outs" => [ "res", "M" ],
},
"Conv_FP2FP" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
"comment" => "construct Conv Floating Point -> Floating Point",
+ "outs" => [ "res", "M" ],
},
#----------------------------------------------------------#
"comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfmul" => {
"comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfsub" => {
"comment" => "virtual fp Sub: Sub(a, b) = a - b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfdiv" => {
"comment" => "virtual fp Div: Div(a, b) = a / b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfabs" => {
"state" => "exc_pinned",
"comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+ "outs" => [ "res", "M" ],
},
"vfst" => {
"comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
+ "outs" => [ "M" ],
},
# Conversions
"irn_flags" => "R",
"comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+ "outs" => [ "res", "M" ],
},
"vfist" => {
"comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
+ "outs" => [ "M" ],
},
# constants
"rd_constructor" => "NONE",
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
+ "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
},
"faddp" => {
"rd_constructor" => "NONE",
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
- "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
+ "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
},
"fmul" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
+ "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
},
"fmulp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
+ "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
},
"fsub" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
- "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
+ "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
},
"fsubp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
- "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
+ "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
},
"fsubr" => {
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
- "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
+ "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
},
"fsubrp" => {
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
- "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
+ "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
},
"fdiv" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
- "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+ "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
},
"fdivp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
- "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+ "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
},
"fdivr" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
- "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+ "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
},
"fdivrp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
- "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+ "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
},
"fabs" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Abs: Abs(a) = |a|",
"reg_req" => { },
- "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */'
+ "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
},
"fchs" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Chs: Chs(a) = -a",
"reg_req" => { },
- "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */'
+ "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
},
"fsin" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sin: Sin(a) = sin(a)",
"reg_req" => { },
- "emit" => '. fsin /* x87 sin(%S1) -> %D1 */'
+ "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
},
"fcos" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Cos: Cos(a) = cos(a)",
"reg_req" => { },
- "emit" => '. fcos /* x87 cos(%S1) -> %D1 */'
+ "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
},
"fsqrt" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
"reg_req" => { },
- "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */'
+ "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
},
# x87 Load and Store
"state" => "exc_pinned",
"comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { },
- "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */'
+ "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
},
"fst" => {
"state" => "exc_pinned",
"comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { },
- "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */'
+ "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
},
"fstp" => {
"state" => "exc_pinned",
"comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { },
- "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */'
+ "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
},
# Conversions
"irn_flags" => "R",
"comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
"reg_req" => { },
- "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */'
+ "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
},
"fist" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"reg_req" => { },
- "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */'
+ "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
},
"fistp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"reg_req" => { },
- "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */'
+ "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
},
# constants
"rd_constructor" => "NONE",
"comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
"reg_req" => { },
- "emit" => '. fldz /* x87 0.0 -> %D1 */'
+ "emit" => '. fldz /* x87 0.0 -> %D1 */',
},
"fld1" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
"reg_req" => { },
- "emit" => '. fld1 /* x87 1.0 -> %D1 */'
+ "emit" => '. fld1 /* x87 1.0 -> %D1 */',
},
"fldpi" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load pi: Ld pi -> reg",
"reg_req" => { },
- "emit" => '. fldpi /* x87 pi -> %D1 */'
+ "emit" => '. fldpi /* x87 pi -> %D1 */',
},
"fldln2" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
"reg_req" => { },
- "emit" => '. fldln2 /* x87 ln(2) -> %D1 */'
+ "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
},
"fldlg2" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
"reg_req" => { },
- "emit" => '. fldlg2 /* x87 log(2) -> %D1 */'
+ "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
},
"fldl2t" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
"reg_req" => { },
- "emit" => '. fldll2t /* x87 ld(10) -> %D1 */'
+ "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
},
"fldl2e" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load ld e: Ld ld e -> reg",
"reg_req" => { },
- "emit" => '. fldl2e /* x87 ld(e) -> %D1 */'
+ "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
},
"fldConst" => {
extern ir_op *get_op_Mulh(void);
typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
- ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
+ ir_node *op1, ir_node *op2, ir_node *mem);
typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
- ir_node *op, ir_node *mem, ir_mode *mode);
+ ir_node *op, ir_node *mem);
typedef enum {
ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
/* floating point operations */
if (imm_op) {
DB((mod, LEVEL_1, "FP with immediate ..."));
- new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
set_ia32_Immop_attr(new_op, imm_op);
set_ia32_am_support(new_op, ia32_am_None);
}
else {
DB((mod, LEVEL_1, "FP binop ..."));
- new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
set_ia32_am_support(new_op, ia32_am_Source);
}
}
if (imm_op) {
/* This is expr + const */
DB((mod, LEVEL_1, "INT with immediate ..."));
- new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
set_ia32_Immop_attr(new_op, imm_op);
/* set AM support */
else {
DB((mod, LEVEL_1, "INT binop ..."));
/* This is a normal operation */
- new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
/* This is shift/rot with const */
DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
- new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
set_ia32_Immop_attr(new_op, imm_op);
}
else {
/* This is a normal shift/rot */
DB((mod, LEVEL_1, "Shift/Rot binop ..."));
- new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
}
/* set AM support */
ir_node *nomem = new_NoMem();
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
- new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
if (mode_is_float(mode)) {
DB((mod, LEVEL_1, "FP unop ..."));
if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
- new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
+ new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
normal_add = 0;
}
else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
- new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
+ new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
normal_add = 0;
}
}
if (normal_add) {
- new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
+ new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
set_ia32_Immop_attr(new_op, const_op);
}
}
else {
/* This is a normal add */
- new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
+ new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
- new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
+ new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
normal_sub = 0;
}
else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
- new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
+ new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
normal_sub = 0;
}
}
if (normal_sub) {
- new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
+ new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
set_ia32_Immop_attr(new_op, const_op);
}
}
else {
/* This is a normal sub */
- new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
+ new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
if (mode_is_signed(mode)) {
/* in signed mode, we need to sign extend the dividend */
- cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
- dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
- edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
+ cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
+ dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
+ edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
}
else {
edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
}
- res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T, dm_flav);
+ res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
set_ia32_n_res(res, 2);
FP_USED(env->cg);
if (USE_SSE2(env->cg)) {
if (is_ia32_xConst(op2)) {
- new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
+ new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
set_ia32_am_support(new_op, ia32_am_None);
set_ia32_Immop_attr(new_op, op2);
}
else {
- new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
+ new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
set_ia32_am_support(new_op, ia32_am_Source);
}
}
else {
- new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
+ new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
set_ia32_am_support(new_op, ia32_am_Source);
}
set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *nomem = new_rd_NoMem(env->irg);
- new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
+ new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
size = get_mode_size_bits(env->mode);
name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
set_ia32_res_mode(new_op, env->mode);
set_ia32_immop_type(new_op, ia32_ImmSymConst);
- new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
+ new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
}
else {
new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg)) {
- res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
+ res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
size = get_mode_size_bits(mode);
name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
set_ia32_res_mode(res, mode);
set_ia32_immop_type(res, ia32_ImmSymConst);
- res = new_rd_Proj(dbg, irg, block, res, mode, 0);
+ res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
}
else {
res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
}
}
else {
- res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
+ res = new_rd_ia32_Cdq(dbg, irg, block, op);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
- p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
- p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
+ p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
+ p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
- res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
+ res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
- res = new_rd_Proj(dbg, irg, block, res, mode, 0);
+ res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
- res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
+ res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
- res = new_rd_Proj(dbg, irg, block, res, mode, 0);
+ res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
}
return res;
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
else
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
}
/* base is an constant address */
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
else
- new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
}
else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem);
}
/* stored const is an attribute (saves a register) */
cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
}
- res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
+ res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
set_ia32_pncode(res, get_Proj_proj(sel));
set_ia32_res_mode(res, get_irn_mode(op1));
if (mode_is_float(get_irn_mode(expr))) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+ res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
else {
assert(0);
}
}
else {
- res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+ res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
}
set_ia32_Immop_attr(res, cnst);
set_ia32_res_mode(res, get_irn_mode(expr));
if (mode_is_float(get_irn_mode(cmp_a))) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+ res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
else {
assert(0);
}
}
else {
- res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+ res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
}
set_ia32_res_mode(res, get_irn_mode(cmp_a));
}
}
/* do a fist */
- fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg), mode_T);
+ fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
set_ia32_frame_ent(fist, ent);
set_ia32_use_frame(fist);
set_ia32_am_flavour(fist, ia32_B);
set_ia32_ls_mode(fist, mode_E);
- mem = new_r_Proj(irg, block, fist, mode_M, 0);
+ mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
/* do a Load */
- load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
+ load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
set_ia32_frame_ent(load, ent);
set_ia32_use_frame(load);
set_ia32_am_flavour(load, ia32_B);
set_ia32_ls_mode(load, tgt_mode);
- return new_r_Proj(irg, block, load, tgt_mode, 0);
+ return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
}
/**
/* first convert to 32 bit */
src_bits = get_mode_size_bits(src_mode);
if (src_bits == 8) {
- op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
op = new_r_Proj(irg, block, op, mode_Is, 0);
}
else if (src_bits < 32) {
- op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
op = new_r_Proj(irg, block, op, mode_Is, 0);
}
/* do a store */
- store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem, mode_T);
+ store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
mem = new_r_Proj(irg, block, store, mode_M, 0);
/* do a fild */
- fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
+ fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
set_ia32_frame_ent(fild, ent);
set_ia32_use_frame(fild);
/* ... to float */
if (USE_SSE2(env->cg)) {
DB((mod, LEVEL_1, "create Conv(float, float) ..."));
- new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
}
else {
DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
/* ... to int */
DB((mod, LEVEL_1, "create Conv(float, int) ..."));
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
else
return gen_x87_fp_to_gp(env, tgt_mode);
proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
if (tgt_bits == 8 || src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
}
else {
- new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
}
}
}
/* ... to float */
DB((mod, LEVEL_1, "create Conv(int, float) ..."));
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
else
return gen_x87_gp_to_fp(env, src_mode);
}
else {
DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
if (tgt_bits == 8 || src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
}
else {
- new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
}
}
}
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
else
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
set_ia32_frame_ent(new_op, ent);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
- return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
+ return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
}
/**
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_rd_NoMem(env->irg);
- new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
+ new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
set_ia32_frame_ent(new_op, be_get_frame_entity(node));
set_ia32_am_support(new_op, ia32_am_Full);
set_ia32_use_frame(new_op);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
- return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
+ return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
}
/**
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
else
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
else
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
else
- new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
}
else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
}
set_ia32_frame_ent(new_op, ent);
/* generate the add */
if (mode_is_float(tenv.mode)) {
- res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+ res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
set_ia32_am_support(res, ia32_am_Source);
}
else {
- res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+ res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
set_ia32_am_support(res, ia32_am_Full);
set_ia32_commutative(res);
}
break;
}
- res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
+ res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
arch_set_irn_register(cg->arch_env, res, out_reg);
set_ia32_op_type(res, ia32_Normal);
set_ia32_commutative(res);
projects / libfirm / commitdiff