mem_proj = NULL;
foreach_out_edge(node, edge) {
ir_node *out = get_edge_src_irn(edge);
- if(get_Proj_proj(out) == pn_ia32_mem) {
+ if(get_irn_mode(out) == mode_M) {
+ assert(mem_proj == NULL);
mem_proj = out;
- break;
}
}
type = get_ia32_op_type(node);
switch (type) {
- case ia32_AddrModeS: turn_back_am(node); break;
+ case ia32_AddrModeS:
+ turn_back_am(node);
+ break;
case ia32_AddrModeD:
/* TODO implement this later... */
ir_node *cmp = NULL;
ir_mode *cmp_mode;
- if (ia32_cg_config.use_cmov) {
- /* we can't handle psis with 64bit compares yet */
- if (is_Proj(sel)) {
- cmp = get_Proj_pred(sel);
- if (is_Cmp(cmp)) {
- left = get_Cmp_left(cmp);
- cmp_mode = get_irn_mode(left);
- if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
- return 0;
- } else {
- cmp = NULL;
- }
+ /* we can't handle psis with 64bit compares yet */
+ if (is_Proj(sel)) {
+ cmp = get_Proj_pred(sel);
+ if (is_Cmp(cmp)) {
+ left = get_Cmp_left(cmp);
+ cmp_mode = get_irn_mode(left);
+ if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
+ return 0;
+ } else {
+ cmp = NULL;
}
+ }
+ if (ia32_cg_config.use_cmov) {
if (ia32_cg_config.use_sse2 && cmp != NULL) {
pn_Cmp pn = get_Proj_proj(sel);
ir_node *cl = get_Cmp_left(cmp);
ir_node *load_res;
ir_node *mem;
int pnres;
+ int pnmem;
/* should_be same constraint is fullfilled, nothing to do */
if(out_reg == same_reg)
if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) {
load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
pnres = pn_ia32_Load_res;
+ pnmem = pn_ia32_Load_M;
proj_mode = mode_Iu;
} else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem,
get_ia32_ls_mode(irn));
pnres = pn_ia32_xLoad_res;
+ pnmem = pn_ia32_xLoad_M;
proj_mode = mode_E;
} else {
panic("cannot turn back address mode for this register class");
int pn = get_Proj_proj(node);
if(pn == 0) {
exchange(node, irn);
- } else {
- assert(pn == 1);
+ } else if(pn == pn_ia32_mem) {
set_Proj_pred(node, load);
+ set_Proj_proj(node, pnmem);
}
}
set_irn_mode(irn, mode_Iu);
Cmp => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "flags", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "eflags" ],
+ outs => [ "eflags", "unused", "M" ],
am => "source,binary",
emit => '. cmp%M %binop',
attr => "int ins_permuted, int cmp_unsigned",
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
-
/* loads might be part of source address mode matches, so we don't
- transform the ProjMs yet (with the exception of loads whose result is
- not used)
+ * transform the ProjMs yet (with the exception of loads whose result is
+ * not used)
*/
if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
ir_node *res;
- assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
- nodes is 1 */
/* this is needed, because sometimes we have loops that are only
reachable through the ProjM */
be_enqueue_preds(node);
/* do it in 2 steps, to silence firm verifier */
res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
- set_Proj_proj(res, pn_ia32_Load_M);
+ set_Proj_proj(res, pn_ia32_mem);
return res;
}