used new outs feature

renamed register classes

diff --git a/ir/be/ppc32/bearch_ppc32.c b/ir/be/ppc32/bearch_ppc32.c
index 8799e40..3b01383 100644 (file)
--- a/ir/be/ppc32/bearch_ppc32.c
+++ b/ir/be/ppc32/bearch_ppc32.c
@@ -128,10 +128,10 @@ static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_r
                        DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
 
                        if (mode_is_float(mode)) {
-                               memcpy(req, &(ppc32_default_req_ppc32_floating_point.req), sizeof(*req));
+                               memcpy(req, &(ppc32_default_req_ppc32_fp.req), sizeof(*req));
                        }
                        else if (mode_is_int(mode) || mode_is_reference(mode)) {
-                               memcpy(req, &(ppc32_default_req_ppc32_general_purpose.req), sizeof(*req));
+                               memcpy(req, &(ppc32_default_req_ppc32_gp.req), sizeof(*req));
                        }
                        else if (mode == mode_T || mode == mode_M) {
                                DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
@@ -323,9 +323,9 @@ static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap
        isleaf = flags.bits.irg_is_leaf;
 
        if(flags.bits.try_omit_fp)
-               return &ppc32_general_purpose_regs[REG_R1];
+               return &ppc32_gp_regs[REG_R1];
        else
-               return &ppc32_general_purpose_regs[REG_R31];
+               return &ppc32_gp_regs[REG_R31];
 }
 
 /**
@@ -469,15 +469,15 @@ static void ppc32_transform_spill(ir_node *node, void *env)
 
                const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
 
-               if (regclass == &ppc32_reg_classes[CLASS_ppc32_general_purpose])
+               if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
                {
                        store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
-                               get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph), mode_T);
+                               get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
                }
-               else if (regclass == &ppc32_reg_classes[CLASS_ppc32_floating_point])
+               else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
                {
                        store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
-                               get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph), mode_T);
+                               get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
                }
                else assert(0 && "Spill for register class not supported yet!");
 
@@ -505,15 +505,13 @@ static void ppc32_transform_spill(ir_node *node, void *env)
 
                const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
 
-               if (regclass == &ppc32_reg_classes[CLASS_ppc32_general_purpose])
+               if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
                {
-                       load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block,
-                               get_irn_n(node, 0), get_irn_n(node, 1), mode_T);
+                       load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block,   get_irn_n(node, 0), get_irn_n(node, 1));
                }
-               else if (regclass == &ppc32_reg_classes[CLASS_ppc32_floating_point])
+               else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
                {
-                       load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block,
-                               get_irn_n(node, 0), get_irn_n(node, 1), mode_T);
+                       load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block,   get_irn_n(node, 0), get_irn_n(node, 1));
                }
                else assert(0 && "Reload for register class not supported yet!");
 
@@ -661,8 +659,8 @@ static void *ppc32_cg_init(const be_irg_t *birg) {
 
 static ppc32_isa_t ppc32_isa_template = {
        &ppc32_isa_if,
-       &ppc32_general_purpose_regs[REG_R1],  // stack pointer
-       &ppc32_general_purpose_regs[REG_R31], // base pointer
+       &ppc32_gp_regs[REG_R1],  // stack pointer
+       &ppc32_gp_regs[REG_R31], // base pointer
        -1,                                   // stack is decreasing
        0,                                    // num codegens... ??
        NULL
@@ -721,9 +719,9 @@ static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i)
  */
 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
        if (mode_is_float(mode))
-               return &ppc32_reg_classes[CLASS_ppc32_floating_point];
+               return &ppc32_reg_classes[CLASS_ppc32_fp];
        else
-               return &ppc32_reg_classes[CLASS_ppc32_general_purpose];
+               return &ppc32_reg_classes[CLASS_ppc32_gp];
 }
 
 
@@ -763,7 +761,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca
                                {
                                        if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
                                        else gpregi += 2, stackparamsize=8;                                                             // mode == irm_D
-                                       reg = &ppc32_floating_point_regs[fpregi++];
+                                       reg = &ppc32_fp_regs[fpregi++];
                                }
                                else
                                {
@@ -775,7 +773,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca
                        else
                        {
                                if(gpregi <= REG_R10)
-                                       reg = &ppc32_general_purpose_regs[gpregi++];
+                                       reg = &ppc32_gp_regs[gpregi++];
                                else
                                        reg = NULL;
                                stackparamsize=4;
@@ -804,7 +802,7 @@ static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_ca
                mode = get_type_mode(tp);
 
                be_abi_call_res_reg(abi, 0,
-                       mode_is_float(mode) ? &ppc32_floating_point_regs[REG_F1] : &ppc32_general_purpose_regs[REG_R3]);
+                       mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
        }
 }
 

diff --git a/ir/be/ppc32/ppc32_emitter.c b/ir/be/ppc32/ppc32_emitter.c
index 2192d1d..4a1a0f7 100644 (file)
--- a/ir/be/ppc32/ppc32_emitter.c
+++ b/ir/be/ppc32/ppc32_emitter.c
@@ -454,11 +454,11 @@ static void emit_be_Copy(const ir_node *n, ppc32_emit_env_t *env) {
        FILE *F = env->out;
        const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, n, 0);
 
-       if (regclass == &ppc32_reg_classes[CLASS_ppc32_general_purpose])
+       if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
        {
                lc_efprintf(ppc32_get_arg_env(), F, "\tmr      %1D, %1S\t\t\t/* Move register */\n",n,n);
        }
-       else if (regclass == &ppc32_reg_classes[CLASS_ppc32_floating_point])
+       else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
        {
                lc_efprintf(ppc32_get_arg_env(), F, "\tfmr     %1D, %1S\t\t\t/* Move register */\n",n,n);
        }
@@ -476,13 +476,13 @@ static void emit_be_Perm(const ir_node *n, ppc32_emit_env_t *env) {
        FILE *F = env->out;
        const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, n, 0);
 
-       if (regclass == &ppc32_reg_classes[CLASS_ppc32_general_purpose])
+       if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
        {
                lc_efprintf(ppc32_get_arg_env(), F, "\txor     %1S, %1S, %2S\t\t\t/* Swap %1S, %2S with XOR */\n",n,n,n,n,n);
                lc_efprintf(ppc32_get_arg_env(), F, "\txor     %2S, %1S, %2S\t\t\t/* (continued) */\n",n,n,n);
                lc_efprintf(ppc32_get_arg_env(), F, "\txor     %1S, %1S, %2S\t\t\t/* (continued) */\n",n,n,n);
        }
-       else if (regclass == &ppc32_reg_classes[CLASS_ppc32_floating_point])
+       else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
        {
                lc_efprintf(ppc32_get_arg_env(), F, "\tfmr     f0, %1S\t\t\t/* Swap %1S, %2S with moves */\n",n,n,n);
                lc_efprintf(ppc32_get_arg_env(), F, "\tfmr     %1S, %2S\t\t\t/* (continued) */\n",n,n);

diff --git a/ir/be/ppc32/ppc32_spec.pl b/ir/be/ppc32/ppc32_spec.pl
index fa52301..7bda313 100644 (file)
--- a/ir/be/ppc32/ppc32_spec.pl
+++ b/ir/be/ppc32/ppc32_spec.pl
@@ -64,6 +64,9 @@ $comment_string = "/*";
 #        for i = 1 .. arity: ir_node *op_i
 #        ir_mode *mode
 #
+# outs:  if a node defines more than one output, the names of the projections
+#        nodes having outs having automatically the mode mode_T
+#
 # comment: OPTIONAL comment for the node constructor
 #
 # rd_constructor: for every operation there will be a
@@ -89,7 +92,7 @@ $comment_string = "/*";
 #   4 - ignore (do not assign this register)
 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
 %reg_classes = (
-  "general_purpose" => [
+  "gp" => [
                          { "name" => "r0", "type" => 1 },
                          { "name" => "r2", "type" => 1 },
                          { "name" => "r3", "type" => 1 },
@@ -124,7 +127,7 @@ $comment_string = "/*";
                          { "name" => "r1", "type" => 6 }, # this is our stackpointer
                          { "mode" => "mode_P" }
                        ],
-  "floating_point"  => [
+  "fp"  => [
 #                        { "name" => "f0", "type" => 1 }, # => reserved for FP Perm
                          { "name" => "f1", "type" => 1 },
                          { "name" => "f2", "type" => 1 },
@@ -159,25 +162,25 @@ $comment_string = "/*";
 #                        { "name" => "f31", "type" => 2 },
                          { "mode" => "mode_D" }
                        ],
-  "condition"          => [
-                                                { "name" => "cr0", "type" => 1 },
-                                                { "name" => "cr1", "type" => 1 },
-                                                { "name" => "cr2", "type" => 2 },
-                                                { "name" => "cr3", "type" => 2 },
-                                                { "name" => "cr4", "type" => 2 },
-                                                { "name" => "cr5", "type" => 1 },
-                                                { "name" => "cr6", "type" => 1 },
-#                                               { "name" => "cr7", "type" => 1 }, # => reserved for Condition Perm
-                                                { "mode" => "mode_P" } # real mode is 4 bit, but doesn't matter ...
-                                          ],
-  "link"                       => [
-                                                { "name" => "lr", "type" => 4 }, # 3
+  "condition" => [
+                         { "name" => "cr0", "type" => 1 },
+                         { "name" => "cr1", "type" => 1 },
+                         { "name" => "cr2", "type" => 2 },
+                         { "name" => "cr3", "type" => 2 },
+                         { "name" => "cr4", "type" => 2 },
+                         { "name" => "cr5", "type" => 1 },
+                         { "name" => "cr6", "type" => 1 },
+#                        { "name" => "cr7", "type" => 1 }, # => reserved for Condition Perm
+                         { "mode" => "mode_P" } # real mode is 4 bit, but doesn't matter ...
+                       ],
+  "link" => [
+                         { "name" => "lr", "type" => 4 }, # 3
                          { "mode" => "mode_P" }
-                                          ],
-  "count"                      => [
-                                                { "name" => "ctr", "type" => 1 },
+                       ],
+  "count" => [
+                         { "name" => "ctr", "type" => 1 },
                          { "mode" => "mode_P" }
-                                          ]
+                       ]
 ); # %reg_classes
 
 #--------------------------------------------------#
@@ -210,21 +213,21 @@ $comment_string = "/*";
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct Add: Add(a, b) = Add(b, a) = a + b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. add     %D1, %S1, %S2 /* Add(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. add     %D1, %S1, %S2 /* Add(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Addi" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "construct Add: Addi(a, const) = Addi(const, a) = a + const",
-  "reg_req"   => { "in" => [ "!r0" ], "out" => [ "general_purpose" ] },
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "!r0" ], "out" => [ "gp" ] },
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
   "emit"      => '. addi    %D1, %S1, %C /* Addi(%S1, %C) -> %D1, (%A1, const) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 
@@ -232,77 +235,77 @@ $comment_string = "/*";
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct Mul: Mullw(a, b) = Mullw(b, a) = lo32(a * b)",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. mullw   %D1, %S1, %S2 /* Mullw(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. mullw   %D1, %S1, %S2 /* Mullw(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Mulhw" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct Mul: Mulhw(a, b) = Mulhw(b, a) = hi32(a * b)",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. mulhw   %D1, %S1, %S2 /* Mulhw(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. mulhw   %D1, %S1, %S2 /* Mulhw(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Mulhwu" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct Mul: Mulhwu(a, b) = Mulhwu(b, a) = hi32(a * b)",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. mulhwu  %D1, %S1, %S2 /* Mulhwu(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. mulhwu  %D1, %S1, %S2 /* Mulhwu(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"Mul_i" => {
 #  "irn_flags" => "R",
 #  "comment"   => "construct Mul: Mul(a, const) = Mul(const, a) = a * const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. mul %S1, %C, %D1 /* signed Mul(%C, %S1) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. mul %S1, %C, %D1 /* signed Mul(%C, %S1) -> %D1, (%A1, const) */',
 #},
 
 "And" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct And: And(a, b) = And(b, a) = a AND b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. and     %D1, %S1, %S2 /* And(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. and     %D1, %S1, %S2 /* And(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"And_i" => {
 #  "irn_flags" => "R",
 #  "comment"   => "construct And: And(a, const) = And(const, a) = a AND const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. and %S1, %C, %D1 /* And(%C, %S1) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. and %S1, %C, %D1 /* And(%C, %S1) -> %D1, (%A1, const) */',
 #},
 
 "Or" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct Or: Or(a, b) = Or(b, a) = a OR b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. or      %D1, %S1, %S2 /* Or(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. or      %D1, %S1, %S2 /* Or(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"Or_i" => {
 #  "op_flags"  => "C",
 #  "irn_flags" => "R",
 #  "comment"   => "construct Or: Or(a, const) = Or(const, a) = a OR const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. or %S1, %C, %D1 /* Or(%C, %S1) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. or %S1, %C, %D1 /* Or(%C, %S1) -> %D1, (%A1, const) */',
 #},
 
 "Xor" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct Xor: Xor(a, b) = Xor(b, a) = a XOR b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. xor     %D1, %S1, %S2 /* Xor(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. xor     %D1, %S1, %S2 /* Xor(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"Xor_i" => {
 #  "irn_flags" => "R",
 #  "comment"   => "construct Xor: Xor(a, const) = Xor(const, a) = a EOR const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. xor %S1, %C, %D1 /* Xor(%C, %S1) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. xor %S1, %C, %D1 /* Xor(%C, %S1) -> %D1, (%A1, const) */',
 #},
 
 # not commutative operations
@@ -310,130 +313,130 @@ $comment_string = "/*";
 "Sub" => {
   "irn_flags" => "R",
   "comment"   => "construct Sub: Sub(a, b) = a - b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. sub     %D1, %S1, %S2 /* Sub(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. sub     %D1, %S1, %S2 /* Sub(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"Sub_i" => {
 #  "irn_flags" => "R",
 #  "comment"   => "construct Sub: Sub(a, const) = a - const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. subl %S1, %C, %D1 /* Sub(%S1, %C) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. subl %S1, %C, %D1 /* Sub(%S1, %C) -> %D1, (%A1, const) */',
 #},
 
 "Slw" => {
   "irn_flags" => "R",
   "comment"   => "construct Shl: Shl(a, b) = a << b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. slw     %D1, %S1, %S2 /* Shl(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. slw     %D1, %S1, %S2 /* Shl(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"Shl_i" => {
 #  "irn_flags" => "R",
 #  "comment"   => "construct Shl: Shl(a, const) = a << const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. shl %S1, %C, %D1 /* Shl(%S1, %C) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. shl %S1, %C, %D1 /* Shl(%S1, %C) -> %D1, (%A1, const) */',
 #},
 
 "Srw" => {
   "irn_flags" => "R",
   "comment"   => "construct Shr: Srw(a, b): c = a >> b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. srw     %D1, %S1, %S2 /* Srw(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. srw     %D1, %S1, %S2 /* Srw(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 #"Shr_i" => {
 #  "irn_flags" => "R",
 #  "comment"   => "construct Shr: Shr(a, const) = a >> const",
-#  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-#  "emit"      => '. shr %S1, %C, %D1 /* Shr(%S1, %C) -> %D1, (%A1, const) */'
+#  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+#  "emit"      => '. shr %S1, %C, %D1 /* Shr(%S1, %C) -> %D1, (%A1, const) */',
 #},
 
 "Sraw" => {
   "irn_flags" => "R",
   "comment"   => "construct Shrs: Sraw(a, b): c = a >> b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. sraw    %D1, %S1, %S2 /* Sraw(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. sraw    %D1, %S1, %S2 /* Sraw(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Srawi" => {
   "irn_flags" => "R",
   "comment"   => "construct Shrs: Srawi(a, const): c = a >> const",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
   "emit"      => '. sraw    %D1, %S1, %C /* Sraw(%S1, %C) -> %D1, (%A1, const) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 
 },
 
 "Rlwnm" => {
   "irn_flags" => "R",
   "comment"   => "construct ???: Rlwnm(a, b): c = a ROTL b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. rlwnm   %D1, %S1, %S2 /* Rlwnm(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. rlwnm   %D1, %S1, %S2 /* Rlwnm(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Rlwinm" => {
   "irn_flags" => "R",
   "comment"   => "construct ???: Rlwinm(a, b_const, c_const, d_const): (m = MASK(c, d)) e = (a ROTL b) & m",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
   "emit"      => '. rlwinm  %D1, %S1, %ppc32_rlwimi_emit_helper /* Rlwinm(%S1, %ppc32_rlwimi_emit_helper) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 
 "Neg" => {
   "irn_flags" => "R",
   "comment"   => "construct Minus: Neg(a) = -a",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. neg     %D1, %S1 /* Neg(%S1) -> %D1, (%A1) */'
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. neg     %D1, %S1 /* Neg(%S1) -> %D1, (%A1) */',
 },
 
 "Not" => {
   "irn_flags" => "R",
   "comment"   => "construct Not: Not(a) = !a",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. nor     %D1, %S1, %S1 /* Not(%S1) -> %D1, (%A1) */'
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. nor     %D1, %S1, %S1 /* Not(%S1) -> %D1, (%A1) */',
 },
 
 "Extsb" => {
   "irn_flags" => "R",
   "comment"   => "construct Sign extension of byte: Extsb(char a) = (int) a",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. extsb   %D1, %S1 /* Extsb(%S1) -> %D1, (%A1) */'
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. extsb   %D1, %S1 /* Extsb(%S1) -> %D1, (%A1) */',
 },
 
 "Extsh" => {
   "irn_flags" => "R",
   "comment"   => "construct Sign extension of halfword: Extsh(char a) = (short) a",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. extsh   %D1, %S1 /* Extsh(%S1) -> %D1, (%A1) */'
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. extsh   %D1, %S1 /* Extsh(%S1) -> %D1, (%A1) */',
 },
 
 "Divw" => {
   "irn_flags" => "R",
   "comment"   => "construct Div (signed): Div(a, b) = a div b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. divw    %D1, %S1, %S2 /* Div(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. divw    %D1, %S1, %S2 /* Div(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Divwu" => {
   "irn_flags" => "R",
   "comment"   => "construct Div (unsigned): Div(a, b) = a div b",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
-  "emit"      => '. divwu   %D1, %S1, %S2 /* Div(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+  "emit"      => '. divwu   %D1, %S1, %S2 /* Div(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Mtctr" => {
   "irn_flags" => "R",
   "comment"   => "construct Mtctr: Ctr = a",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "count" ] },
-  "emit"      => '. mtctr   %S1 /* Mtctr(%S1) -> %D1, (%A1) */'
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "count" ] },
+  "emit"      => '. mtctr   %S1 /* Mtctr(%S1) -> %D1, (%A1) */',
 },
 
 
@@ -443,57 +446,57 @@ $comment_string = "/*";
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "Const (high-level node)",
-  "reg_req"   => { "out" => [ "general_purpose" ] },
+  "reg_req"   => { "out" => [ "gp" ] },
   "cmp_attr"  =>
 '
        return attr_a->data.constant_tarval != attr_b->data.constant_tarval;
-'
+',
 },
 
 "fConst" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "float Const (high-level node)",
-  "reg_req"   => { "out" => [ "floating_point" ] },
+  "reg_req"   => { "out" => [ "fp" ] },
   "cmp_attr"  =>
 '
        return attr_a->data.constant_tarval != attr_b->data.constant_tarval;
-'
+',
 },
 
 "SymConst" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "SymConst (high-level node)",
-  "reg_req"   => { "out" => [ "general_purpose" ] },
+  "reg_req"   => { "out" => [ "gp" ] },
   "cmp_attr"  =>
 '
        return attr_a->data.constant_tarval != attr_b->data.constant_tarval;
-'
+',
 },
 
 "Unknown" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "construct unknown register",
-  "reg_req"   => { "out" => [ "general_purpose" ] },
+  "reg_req"   => { "out" => [ "gp" ] },
   "emit"      => '. \t\t /* use %D1 as uninitialized value */',
   "cmp_attr"  =>
 '
        return 1;
-'
+',
 },
 
 "fUnknown" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "construct unknown float register",
-  "reg_req"   => { "out" => [ "floating_point" ] },
+  "reg_req"   => { "out" => [ "fp" ] },
   "emit"      => '. \t\t /* use %D1 as uninitialized value */',
   "cmp_attr"  =>
 '
        return 1;
-'
+',
 },
 
 "cUnknown" => {
@@ -505,19 +508,19 @@ $comment_string = "/*";
   "cmp_attr"  =>
 '
        return 1;
-'
+',
 },
 
 "Addi_zero" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "load constant (16bit with sign extension)",
-  "reg_req"   => { "out" => [ "general_purpose" ] },
+  "reg_req"   => { "out" => [ "gp" ] },
   "emit"      => '. addi    %D1, 0, %C /* lower 16 bit of %C (sign extended) -> %D1 */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 "Branch" => {
@@ -527,30 +530,30 @@ $comment_string = "/*";
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 "LoopCopy" => {
   "irn_flags" => "R",
   "comment"   => "construct LoopCopy(src, dest, count, mem): Copy count words from src to dest",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose", "count", "none" ], "out" => [ "none", "in_r1", "in_r2", "in_r3", "general_purpose" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "count", "none" ], "out" => [ "none", "in_r1", "in_r2", "in_r3", "gp" ] },
 },
 
 "Switch" => {
   "op_flags" => "L|X|Y",
   "comment"   => "construct Switch(selector): Jump to whatever",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose", "condition" ], "out" => [ "none" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "condition" ], "out" => [ "none" ] },
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 "Addis_zero" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "load the constant to higher 16 bit of register",
-  "reg_req"   => { "out" => [ "general_purpose" ] },
+  "reg_req"   => { "out" => [ "gp" ] },
   "emit"      => '. addis   %D1, 0, %C /* %C << 16 -> %D1 */',
   "attr"      => "ppc32_attr_offset_mode om, tarval *tv, ident *id",
   "init_attr" =>
@@ -568,68 +571,68 @@ $comment_string = "/*";
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 "Ori" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "ors constant with register",
-  "reg_req"   => { "in" => [ "general_purpose"], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "gp"], "out" => [ "gp" ] },
   "emit"      => '. ori     %D1, %S1, %C /* Ori(%S1,%C) -> %D1 */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 "Andi_dot" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "ands constant with register with cr0 update",
-  "reg_req"   => { "in" => [ "general_purpose"], "out" => [ "general_purpose", "cr0" ] },
+  "reg_req"   => { "in" => [ "gp"], "out" => [ "gp", "cr0" ] },
   "emit"      => '. andi.   %D1, %S1,%C /* Andi(%S1,%C) -> %D1 (%D2 changed) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 "Cmp" => {
   "irn_flags" => "R",
   "comment"   => "construct Cmp: Cmp(a, b) = Flags in crX",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "condition" ] },
-  "emit"      => '. cmp     %D1, 0, %S1, %S2 /* Cmp(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "condition" ] },
+  "emit"      => '. cmp     %D1, 0, %S1, %S2 /* Cmp(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Cmpi" => {
   "irn_flags" => "R",
   "comment"   => "construct Cmp immediate: Cmpi(a, const) = Flags in crX",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "condition" ] },
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "condition" ] },
   "emit"      => '. cmpi    %D1, 0, %S1, %C /* Cmpi(%S1, %C) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 
 "Cmpl" => {
   "irn_flags" => "R",
   "comment"   => "construct Cmp logical: Cmpl(a, b) = Flags in crX",
-  "reg_req"   => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "condition" ] },
-  "emit"      => '. cmpl    %D1, 0, %S1, %S2 /* Cmpl(%S1, %S2) -> %D1, (%A1, %A2) */'
+  "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "condition" ] },
+  "emit"      => '. cmpl    %D1, 0, %S1, %S2 /* Cmpl(%S1, %S2) -> %D1, (%A1, %A2) */',
 },
 
 "Cmpli" => {
   "irn_flags" => "R",
   "comment"   => "construct Cmp logical immediate: Cmpli(a, const) = Flags in crX",
-  "reg_req"   => { "in" => [ "general_purpose" ], "out" => [ "condition" ] },
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "condition" ] },
   "emit"      => '. cmpli   %D1, 0, %S1, %C /* Cmpli(%S1, %C) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
 },
 
 
@@ -640,12 +643,13 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct Load (byte unsigned): Load(ptr, mem) = LD ptr -> reg",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
   "emit"      => '. lbz     %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Lhz" => {
@@ -653,12 +657,13 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct Load (halfword unsigned): Load(ptr, mem) = LD ptr -> reg",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
   "emit"      => '. lhz     %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Lha" => {
@@ -666,12 +671,13 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct Load (halfword signed): Load(ptr, mem) = LD ptr -> reg",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
   "emit"      => '. lha     %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Lwz" => {
@@ -679,12 +685,13 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct Load (word): Load(ptr, mem) = LD ptr -> reg",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "general_purpose" ] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
   "emit"      => '. lwz     %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Lwzu" => {
@@ -692,48 +699,52 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct Load with update (word): Load(ptr, mem) = LD ptr -> reg",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "general_purpose", "in_r1"] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "gp", "in_r1", "none"] },
   "emit"      => '. lwzu    %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, %S1 += %O, (%A1) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "ptr", "M" ],
 },
 
 "Stb" => {
   "op_flags"  => "L|F",
   "state"     => "exc_pinned",
   "comment"   => "construct Store: Store (byte) (ptr, val, mem) = ST ptr,val",
-  "reg_req"   => { "in" => [ "!r0", "general_purpose", "none" ] },
+  "reg_req"   => { "in" => [ "!r0", "gp", "none" ] },
   "emit"      => '. stb     %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "M" ],
 },
 
 "Sth" => {
   "op_flags"  => "L|F",
   "state"     => "exc_pinned",
   "comment"   => "construct Store: Store (halfword) (ptr, val, mem) = ST ptr,val",
-  "reg_req"   => { "in" => [ "!r0", "general_purpose", "none" ] },
+  "reg_req"   => { "in" => [ "!r0", "gp", "none" ] },
   "emit"      => '. sth     %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "M" ],
 },
 
 "Stw" => {
   "op_flags"  => "L|F",
   "state"     => "exc_pinned",
   "comment"   => "construct Store: Store (word) (ptr, val, mem) = ST ptr,val",
-  "reg_req"   => { "in" => [ "!r0", "general_purpose", "none" ] },
+  "reg_req"   => { "in" => [ "!r0", "gp", "none" ] },
   "emit"      => '. stw     %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "M" ],
 },
 
 #--------------------------------------------------------#
@@ -751,36 +762,36 @@ $comment_string = "/*";
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct FP Add: Add(a, b) = Add(b, a) = a + b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fadd    %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fadd    %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */',
 },
 
 "fAdds" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct FP Add (single): Add(a, b) = Add(b, a) = a + b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fadds   %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fadds   %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */',
 },
 
 "fMul" => {
   "op_flags"  => "C",
   "comment"   => "construct FP Mul: Mul(a, b) = Mul(b, a) = a * b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fmul    %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fmul    %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */',
 },
 
 "fMuls" => {
   "op_flags"  => "C",
   "comment"   => "construct FP Mul (single): Mul(a, b) = Mul(b, a) = a * b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fmuls   %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fmuls   %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */',
 },
 
 "fNeg" => {
   "comment"   => "construct FP Negation: fNeg(a) = -a",
-  "reg_req"   => { "in" => [ "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fneg    %D1, %S1 /* FP fNeg(%S1) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fneg    %D1, %S1 /* FP fNeg(%S1) -> %D1 */',
 },
 
 
@@ -788,16 +799,16 @@ $comment_string = "/*";
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct FP Max: Max(a, b) = Max(b, a) = a > b ? a : b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fmax    %S1, %S2, %D1 /* FP Max(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fmax    %S1, %S2, %D1 /* FP Max(%S1, %S2) -> %D1 */',
 },
 
 "fMin" => {
   "op_flags"  => "C",
   "irn_flags" => "R",
   "comment"   => "construct FP Min: Min(a, b) = Min(b, a) = a < b ? a : b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fmin    %S1, %S2, %D1 /* FP Min(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fmin    %S1, %S2, %D1 /* FP Min(%S1, %S2) -> %D1 */',
 },
 
 # not commutative operations
@@ -805,62 +816,62 @@ $comment_string = "/*";
 "fSub" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Sub: Sub(a, b) = a - b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fsub    %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fsub    %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */',
 },
 
 "fSubs" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Sub (single): Sub(a, b) = a - b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fsub    %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fsub    %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */',
 },
 
 "fDiv" => {
   "comment"   => "construct FP Div: Div(a, b) = a / b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fdiv    %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fdiv    %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */',
 },
 
 "fDivs" => {
   "comment"   => "construct FP Div (single): Div(a, b) = a / b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fdivs   %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fdivs   %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */',
 },
 
 "fMinus" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Minus: fMinus(a) = -a",
-  "reg_req"   => { "in" => [ "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fneg    %D1, %S1 /* FP fMinus(%S1) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fneg    %D1, %S1 /* FP fMinus(%S1) -> %D1 */',
 },
 
 "fCtiw" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Convert to integer word: fCtiw(a) = (int) a",
-  "reg_req"   => { "in" => [ "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fctiw   %D1, %S1 /* FP fCtiw(%S1) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fctiw   %D1, %S1 /* FP fCtiw(%S1) -> %D1 */',
 },
 
 "fRsp" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Round to single: fRsp(a) = (float) a",
-  "reg_req"   => { "in" => [ "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. frsp    %D1, %S1 /* FP fRsp(%S1) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. frsp    %D1, %S1 /* FP fRsp(%S1) -> %D1 */',
 },
 
 "fAbs" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Abs: fAbs(a) = |a|",
-  "reg_req"   => { "in" => [ "floating_point" ], "out" => [ "floating_point" ] },
-  "emit"      => '. fabs    %D1, %S1 /* FP fAbs(%S1) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp" ], "out" => [ "fp" ] },
+  "emit"      => '. fabs    %D1, %S1 /* FP fAbs(%S1) -> %D1 */',
 },
 
 "fCmpu" => {
   "irn_flags" => "R",
   "comment"   => "construct FP Cmp unordered: fCmpu(a, b) = a ? b",
-  "reg_req"   => { "in" => [ "floating_point", "floating_point" ], "out" => [ "condition" ] },
-  "emit"      => '. fcmpu   %D1, %S1, %S2 /* FP fCmpu(%S1, %S2) -> %D1 */'
+  "reg_req"   => { "in" => [ "fp", "fp" ], "out" => [ "condition" ] },
+  "emit"      => '. fcmpu   %D1, %S1, %S2 /* FP fCmpu(%S1, %S2) -> %D1 */',
 },
 
 # other operations
@@ -869,25 +880,25 @@ $comment_string = "/*";
 #  "op_flags"  => "c",
 #  "irn_flags" => "R",
 #  "comment"   => "represents a FP constant",
-#  "reg_req"   => { "out" => [ "floating_point" ] },
+#  "reg_req"   => { "out" => [ "fp" ] },
 #  "emit"      => '. fmov %C, %D1 /* Mov fConst into register */',
 #  "cmp_attr"  =>
 #'
 #      /* TODO: compare fConst attributes */
 #      return 1;
-#'
+#',
 #},
 
 "fUnknown" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
   "comment"   => "construct unknown floating point register",
-  "reg_req"   => { "out" => [ "floating_point" ] },
+  "reg_req"   => { "out" => [ "fp" ] },
   "emit"      => '. \t\t /* use %D1 as uninitialized value */',
   "cmp_attr"  =>
 '
        return 1;
-'
+',
 },
 
 # Load / Store
@@ -897,12 +908,13 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct FP Load (double): Load(ptr, mem) = LD ptr",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "floating_point" ] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "fp", "none" ] },
   "emit"      => '. lfd     %D1, %O(%S1) /* Load(%O(%S1)) -> %D1 */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Lfs" => {
@@ -910,36 +922,39 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct FP Load (single): Load(ptr, mem) = LD ptr",
-  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "floating_point" ] },
+  "reg_req"   => { "in" => [ "!r0", "none" ], "out" => [ "fp","none" ] },
   "emit"      => '. lfs     %D1, %O(%S1) /* Load(%O(%S1)) -> %D1 */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Stfd" => {
   "op_flags"  => "L|F",
   "state"     => "exc_pinned",
   "comment"   => "construct Store (double): Store(ptr, val, mem)  = ST ptr,val",
-  "reg_req"   => { "in" => [ "!r0", "floating_point", "none" ] },
+  "reg_req"   => { "in" => [ "!r0", "fp", "none" ] },
   "emit"      => '. stfd    %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "M" ],
 },
 
 "Stfs" => {
   "op_flags"  => "L|F",
   "state"     => "exc_pinned",
   "comment"   => "construct Store (single): Store(ptr, val, mem)  = ST ptr,val",
-  "reg_req"   => { "in" => [ "!r0", "floating_point", "none" ] },
+  "reg_req"   => { "in" => [ "!r0", "fp", "none" ] },
   "emit"      => '. stfs    %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
   "cmp_attr"  =>
 '
        return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
-'
+',
+  "outs"      => [ "M" ],
 },
 
 ); # end of %nodes

diff --git a/ir/be/ppc32/ppc32_transform.c b/ir/be/ppc32/ppc32_transform.c
index 3023f3f..2bab558 100644 (file)
--- a/ir/be/ppc32/ppc32_transform.c
+++ b/ir/be/ppc32/ppc32_transform.c
@@ -993,13 +993,13 @@ static ir_node *gen_Load(ppc32_transform_env_t *env) {
        loadptr = ldst_insert_const(loadptr, &tv_const, &id_symconst, env);
        switch(get_nice_modecode(mode)){
                case irm_Bu:
-                       load = new_rd_ppc32_Lbz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load = new_rd_ppc32_Lbz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        break;
 
                case irm_Bs:
                {
                        ir_node *proj_load, *extsb_node;
-                       load =  new_rd_ppc32_Lbz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load =  new_rd_ppc32_Lbz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        proj_load = new_rd_Proj(env->dbg, env->irg, env->block, load, mode, pn_Load_res);
                        extsb_node = new_rd_ppc32_Extsb(env->dbg, env->irg, env->block, proj_load, mode);
                        exchange(get_succ_Proj(env->irn, pn_Load_res), extsb_node);
@@ -1008,22 +1008,22 @@ static ir_node *gen_Load(ppc32_transform_env_t *env) {
 
 
                case irm_Hu:
-                       load = new_rd_ppc32_Lhz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load = new_rd_ppc32_Lhz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        break;
                case irm_Hs:
-                       load =new_rd_ppc32_Lha(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load =new_rd_ppc32_Lha(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        break;
                case irm_Is:
                case irm_Iu:
                case irm_P:
-                       load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        break;
 
                case irm_D:
-                       load = new_rd_ppc32_Lfd(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load = new_rd_ppc32_Lfd(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        break;
                case irm_F:
-                       load = new_rd_ppc32_Lfs(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node), env->mode);
+                       load = new_rd_ppc32_Lfs(env->dbg, env->irg, env->block, loadptr, get_Load_mem(node));
                        break;
 
                default:
@@ -1067,24 +1067,24 @@ static ir_node *gen_Store(ppc32_transform_env_t *env) {
        switch(get_nice_modecode(mode)){
                case irm_Bu:
                case irm_Bs:
-                       store = new_rd_ppc32_Stb(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node), env->mode);
+                       store = new_rd_ppc32_Stb(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node));
                        break;
 
                case irm_Hu:
                case irm_Hs:
-                       store = new_rd_ppc32_Sth(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node), env->mode);
+                       store = new_rd_ppc32_Sth(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node));
                        break;
                case irm_Is:
                case irm_Iu:
                case irm_P:
-                       store = new_rd_ppc32_Stw(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node), env->mode);
+                       store = new_rd_ppc32_Stw(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node));
                        break;
 
                case irm_D:
-                       store = new_rd_ppc32_Stfd(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node), env->mode);
+                       store = new_rd_ppc32_Stfd(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node));
                        break;
                case irm_F:
-                       store = new_rd_ppc32_Stfs(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node), env->mode);
+                       store = new_rd_ppc32_Stfs(env->dbg, env->irg, env->block, storeptr, get_Store_value(node), get_Store_mem(node));
                        break;
 
                default:
@@ -1127,26 +1127,26 @@ static ir_node *gen_CopyB(ppc32_transform_env_t *env) {
                tarval *offset0 = new_tarval_from_long(0, mode_Is);
                tarval *offset4 = new_tarval_from_long(4, mode_Is);
 
-               load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, src, mem, mode_T);
+               load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, src, mem);
                set_ppc32_constant_tarval(load, offset0);
                set_ppc32_offset_mode(load, ppc32_ao_None);
                mem = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_M, pn_Load_M);
                res = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_Is, pn_Load_res);
 
-               store = new_rd_ppc32_Stw(env->dbg, env->irg, env->block, dest, res, mem, mode_T);
+               store = new_rd_ppc32_Stw(env->dbg, env->irg, env->block, dest, res, mem);
                set_ppc32_constant_tarval(store, offset0);
                set_ppc32_offset_mode(store, ppc32_ao_None);
                mem = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_M, pn_Store_M);
 
                if(size/4==2)
                {
-                       load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, src, mem, mode_T);
+                       load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, src, mem);
                        set_ppc32_constant_tarval(load, offset4);
                        set_ppc32_offset_mode(load, ppc32_ao_None);
                        mem = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_M, pn_Load_M);
                        res = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_Is, pn_Load_res);
 
-                       store = new_rd_ppc32_Stw(env->dbg, env->irg, env->block, dest, res, mem, mode_T);
+                       store = new_rd_ppc32_Stw(env->dbg, env->irg, env->block, dest, res, mem);
                        set_ppc32_constant_tarval(store, offset4);
                        set_ppc32_offset_mode(store, ppc32_ao_None);
                        mem = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_M, pn_Store_M);
@@ -1179,7 +1179,7 @@ static ir_node *gen_CopyB(ppc32_transform_env_t *env) {
                        in[0] = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_Is, 1); // src
                        in[1] = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_Is, 2); // dest
                        in[2] = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_Is, 4); // temp
-                       be_new_Keep(&ppc32_reg_classes[CLASS_ppc32_general_purpose], env->irg, env->block, 3, in);
+                       be_new_Keep(&ppc32_reg_classes[CLASS_ppc32_gp], env->irg, env->block, 3, in);
                        in[0] = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_Is, 3); // ctr
                        be_new_Keep(&ppc32_reg_classes[CLASS_ppc32_count], env->irg, env->block, 1, in);
 
@@ -1193,13 +1193,13 @@ static ir_node *gen_CopyB(ppc32_transform_env_t *env) {
        {
                ir_node *res;
                tarval* offset_tarval = new_tarval_from_long(offset, mode_Is);
-               load = new_rd_ppc32_Lhz(env->dbg, env->irg, env->block, src, mem, mode_T);
+               load = new_rd_ppc32_Lhz(env->dbg, env->irg, env->block, src, mem);
                set_ppc32_constant_tarval(load, offset_tarval);
                set_ppc32_offset_mode(load, ppc32_ao_None);
                mem = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_M, pn_Load_M);
                res = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_Is, pn_Load_res);
 
-               store = new_rd_ppc32_Sth(env->dbg, env->irg, env->block, dest, res, mem, mode_T);
+               store = new_rd_ppc32_Sth(env->dbg, env->irg, env->block, dest, res, mem);
                set_ppc32_constant_tarval(store, offset_tarval);
                set_ppc32_offset_mode(store, ppc32_ao_None);
                mem = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_M, pn_Store_M);
@@ -1211,13 +1211,13 @@ static ir_node *gen_CopyB(ppc32_transform_env_t *env) {
        {
                ir_node *res;
                tarval* offset_tarval = new_tarval_from_long(offset, mode_Is);
-               load = new_rd_ppc32_Lbz(env->dbg, env->irg, env->block, src, mem, mode_T);
+               load = new_rd_ppc32_Lbz(env->dbg, env->irg, env->block, src, mem);
                set_ppc32_constant_tarval(load, offset_tarval);
                set_ppc32_offset_mode(load, ppc32_ao_None);
                mem = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_M, pn_Load_M);
                res = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_Is, pn_Load_res);
 
-               store = new_rd_ppc32_Stb(env->dbg, env->irg, env->block, dest, res, mem, mode_T);
+               store = new_rd_ppc32_Stb(env->dbg, env->irg, env->block, dest, res, mem);
                set_ppc32_constant_tarval(store, offset_tarval);
                set_ppc32_offset_mode(store, ppc32_ao_None);
                // mem = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_M, pn_Store_M);
@@ -1244,7 +1244,7 @@ static ir_node *gen_be_FrameAddr(ppc32_transform_env_t *env) {
  * @param env   The transformation environment
  */
 static ir_node *gen_be_StackParam(ppc32_transform_env_t *env) {
-       ir_node *load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, get_irn_n(env->irn, 0), new_NoMem(), mode_T);
+       ir_node *load = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, get_irn_n(env->irn, 0), new_NoMem());
        ir_node *proj = new_rd_Proj(env->dbg, env->irg, env->block, load, env->mode, pn_Load_res);
        set_ppc32_frame_entity(load, be_get_frame_entity(env->irn));
        return proj;
@@ -1574,9 +1574,9 @@ static ir_node *gen_ppc32_fConst(ppc32_transform_env_t *env) {
                                ir_node *node_addis = new_rd_ppc32_Addis_zero(env->dbg, env->irg, env->block, env->mode, ppc32_ao_Ha16, NULL, id_symconst);
 
                                if(mode==mode_D)
-                                       load = new_rd_ppc32_Lfd(env->dbg, env->irg, env->block, node_addis, new_NoMem(), mode_T);
+                                       load = new_rd_ppc32_Lfd(env->dbg, env->irg, env->block, node_addis, new_NoMem());
                                else // mode_F
-                                       load = new_rd_ppc32_Lfs(env->dbg, env->irg, env->block, node_addis, new_NoMem(), mode_T);
+                                       load = new_rd_ppc32_Lfs(env->dbg, env->irg, env->block, node_addis, new_NoMem());
 
                                set_ppc32_symconst_ident(load, id_symconst);
                                set_ppc32_offset_mode(load, ppc32_ao_Lo16);
@@ -1585,9 +1585,9 @@ static ir_node *gen_ppc32_fConst(ppc32_transform_env_t *env) {
                        {
                                addr = gen_ppc32_SymConst (env);
                                if(mode==mode_D)
-                                       load = new_rd_ppc32_Lfd(env->dbg, env->irg, env->block, addr, new_NoMem(), mode_T);
+                                       load = new_rd_ppc32_Lfd(env->dbg, env->irg, env->block, addr, new_NoMem());
                                else // mode_F
-                                       load = new_rd_ppc32_Lfs(env->dbg, env->irg, env->block, addr, new_NoMem(), mode_T);
+                                       load = new_rd_ppc32_Lfs(env->dbg, env->irg, env->block, addr, new_NoMem());
                        }
                        return new_rd_Proj(env->dbg, env->irg, env->block, load, mode, pn_Load_res);
                }
@@ -1644,7 +1644,7 @@ static ir_node *gen_ppc32_SymConst(ppc32_transform_env_t *env) {
                        else
                        {
                                ir_node *node_addis = new_rd_ppc32_Addis_zero(env->dbg, env->irg, env->block, env->mode, ppc32_ao_Ha16, NULL, id_symconst);
-                               node = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, node_addis, new_NoMem(), mode_T);
+                               node = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, node_addis, new_NoMem());
                                set_ppc32_symconst_ident(node, id_symconst);
                                set_ppc32_offset_mode(node, ppc32_ao_Lo16);
                                node = new_rd_Proj(env->dbg, env->irg, env->block, node, env->mode, pn_Load_res);

diff --git a/ir/be/ppc32/ppc32_transform_conv.c b/ir/be/ppc32/ppc32_transform_conv.c
index b500292..8470506 100644 (file)
--- a/ir/be/ppc32/ppc32_transform_conv.c
+++ b/ir/be/ppc32/ppc32_transform_conv.c
@@ -101,10 +101,10 @@ static ir_node *gen_Conv(ppc32_transform_env_t *env, ir_node *op) {
                        {
                                ir_node *fctiw = new_rd_ppc32_fCtiw(env->dbg, env->irg, env->block, op, from_mode);
                                ir_node *stfd = new_rd_ppc32_Stfd(env->dbg, env->irg, env->block, get_irg_frame(env->irg),
-                                       fctiw, memory, mode_T);
+                                       fctiw, memory);
                                ir_node *storememproj = new_rd_Proj(env->dbg, env->irg, env->block, stfd, mode_M, pn_Store_M);
                                ir_node *lwz = new_rd_ppc32_Lwz(env->dbg, env->irg, env->block, get_irg_frame(env->irg),
-                                       storememproj, mode_T);
+                                       storememproj);
                                set_ppc32_frame_entity(stfd, memslot);
                                set_ppc32_offset_mode(stfd, ppc32_ao_Lo16);     // TODO: only allows a 16-bit offset on stack
                                set_ppc32_frame_entity(lwz, memslot);