&ia32_registers[REG_GP_NOREG]);
}
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
+ir_node *ia32_new_NoReg_fp(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
- return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
- &ia32_registers[REG_VFP_NOREG]);
+ return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
+ &ia32_registers[REG_FP_NOREG]);
}
ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
if (ia32_cg_config.use_sse2) {
return ia32_new_NoReg_xmm(irg);
} else {
- return ia32_new_NoReg_vfp(irg);
+ return ia32_new_NoReg_fp(irg);
}
}
if (ia32_cg_config.use_sse2)
new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
else
- new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
} else {
- store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
- res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+ store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
+ res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
}
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
break;
}
- case iro_ia32_vfild:
- case iro_ia32_vfld:
+ case iro_ia32_fild:
+ case iro_ia32_fld:
case iro_ia32_xLoad: {
mode = get_ia32_ls_mode(node);
align = 4;
case iro_ia32_Store8Bit:
case iro_ia32_Store:
case iro_ia32_fst:
- case iro_ia32_vfist:
- case iro_ia32_vfisttp:
- case iro_ia32_vfst:
+ case iro_ia32_fist:
+ case iro_ia32_fisttp:
case iro_ia32_xStore:
case iro_ia32_xStoreSimple:
#endif
const arch_register_t *reg;
assert(is_atomic_type(tp));
- reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
/* all XMM registers are caller save */
return reg->index != REG_XMM_NOREG;
- } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* all VFP registers are caller save */
- return reg->index != REG_VFP_NOREG;
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
+ /* all FP registers are caller save */
+ return reg->index != REG_FP_NOREG;
}
}
return 0;
typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t;
typedef struct ia32_irg_data_t {
- ir_node **blk_sched; /**< an array containing the scheduled blocks */
- unsigned do_x87_sim:1; /**< set to 1 if x87 simulation should be enforced */
- unsigned dump:1; /**< set to 1 if graphs should be dumped */
+ ir_node **blk_sched; /**< an array containing the scheduled blocks */
+ unsigned do_x87_sim:1; /**< set to 1 if x87 simulation should be enforced */
+ unsigned dump:1; /**< set to 1 if graphs should be dumped */
ir_node *noreg_gp; /**< unique NoReg_GP node */
- ir_node *noreg_vfp; /**< unique NoReg_VFP node */
+ ir_node *noreg_fp; /**< unique NoReg_FP node */
ir_node *noreg_xmm; /**< unique NoReg_XMM node */
ir_node *fpu_trunc_mode; /**< truncate fpu mode */
*/
ir_node *ia32_new_NoReg_gp(ir_graph *irg);
ir_node *ia32_new_NoReg_xmm(ir_graph *irg);
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg);
+ir_node *ia32_new_NoReg_fp(ir_graph *irg);
/**
* Returns the unique per irg FPU truncation mode node.
case 't':
case 'u':
/* TODO: mark values so the x87 simulator knows about t and u */
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_fp])
panic("multiple register classes not supported");
- cls = &ia32_reg_classes[CLASS_ia32_vfp];
+ cls = &ia32_reg_classes[CLASS_ia32_fp];
all_registers_allowed = 1;
break;
if (ia32_cg_config.use_sse2) {
res = new_bd_ia32_xUnknown(dbgi, block);
} else {
- res = new_bd_ia32_vfldz(dbgi, block);
+ res = new_bd_ia32_fldz(dbgi, block);
}
} else if (ia32_mode_needs_gp_reg(mode)) {
res = new_bd_ia32_Unknown(dbgi, block);
if (in == out) {
return;
}
- /* copies of vf nodes aren't real... */
- if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
ia32_emitf(node, "movl %R, %R", in, out);
ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
if (in == out)
return;
- /* copies of vf nodes aren't real... */
- if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
//ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
//ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
//ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
{ name => "xmm_NOREG", type => $ignore | $virtual }, # we need a dummy register for NoReg nodes
{ mode => $mode_xmm }
],
- vfp => [
- { name => "vf0" },
- { name => "vf1" },
- { name => "vf2" },
- { name => "vf3" },
- { name => "vf4" },
- { name => "vf5" },
- { name => "vf6" },
- { name => "vf7" },
- { name => "vfp_NOREG", type => $ignore | $arbitrary | $virtual }, # we need a dummy register for NoReg nodes
+ fp => [
+ { name => "st0", realname => "st", dwarf => 11 },
+ { name => "st1", realname => "st(1)", dwarf => 12 },
+ { name => "st2", realname => "st(2)", dwarf => 13 },
+ { name => "st3", realname => "st(3)", dwarf => 14 },
+ { name => "st4", realname => "st(4)", dwarf => 15 },
+ { name => "st5", realname => "st(5)", dwarf => 16 },
+ { name => "st6", realname => "st(6)", dwarf => 17 },
+ { name => "st7", realname => "st(7)", dwarf => 18 },
+ { name => "fp_NOREG", type => $ignore | $arbitrary | $virtual }, # we need a dummy register for NoReg nodes
{ mode => $mode_fp87 }
],
- st => [
- { name => "st0", realname => "st", dwarf => 11, type => $ignore },
- { name => "st1", realname => "st(1)", dwarf => 12, type => $ignore },
- { name => "st2", realname => "st(2)", dwarf => 13, type => $ignore },
- { name => "st3", realname => "st(3)", dwarf => 14, type => $ignore },
- { name => "st4", realname => "st(4)", dwarf => 15, type => $ignore },
- { name => "st5", realname => "st(5)", dwarf => 16, type => $ignore },
- { name => "st6", realname => "st(6)", dwarf => 17, type => $ignore },
- { name => "st7", realname => "st(7)", dwarf => 18, type => $ignore },
- { mode => $mode_fp87, flags => "manual_ra" }
- ],
fp_cw => [ # the floating point control word
{ name => "fpcw", dwarf => 37, type => $ignore | $state },
{ mode => $mode_fpcw, flags => "manual_ra|state" }
mode => $mode_gp
},
-NoReg_VFP => {
+NoReg_FP => {
state => "pinned",
op_flags => [ "constlike", "dump_noblock" ],
irn_flags => [ "not_scheduled" ],
- reg_req => { out => [ "vfp_NOREG:I" ] },
+ reg_req => { out => [ "fp_NOREG:I" ] },
units => [],
emit => "",
mode => $mode_fp87,
state => "exc_pinned",
reg_req => {
in => [ "gp", "gp", "none", "gp", "esp", "fpcw", "eax", "ecx", "edx" ],
- out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "none", "none" ]
+ out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "none", "none" ]
},
ins => [ "base", "index", "mem", "addr", "stack", "fpcw", "eax", "ecx", "edx" ],
- outs => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "X_regular", "X_except" ],
+ outs => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "X_regular", "X_except" ],
emit => "call %*AS3",
attr_type => "ia32_call_attr_t",
attr => "unsigned pop, ir_type *call_tp",
# rematerialisation disabled for all float nodes for now, because the fpcw
# handler runs before spilling and we might end up with wrong fpcw then
-vfadd => {
+fadd => {
# irn_flags => [ "rematerializable" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
- out => [ "vfp", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+ out => [ "fp", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
outs => [ "res", "dummy", "M" ],
+ emit => 'fadd%FP%FM %AF',
am => "source,binary",
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfmul => {
+fmul => {
# irn_flags => [ "rematerializable" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
- out => [ "vfp", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+ out => [ "fp", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
outs => [ "res", "dummy", "M" ],
+ emit => 'fmul%FP%FM %AF',
am => "source,binary",
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfsub => {
+fsub => {
# irn_flags => [ "rematerializable" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
- out => [ "vfp", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+ out => [ "fp", "none", "none" ] },
ins => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ],
outs => [ "res", "dummy", "M" ],
+ emit => 'fsub%FR%FP%FM %AF',
am => "source,binary",
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfdiv => {
+fdiv => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
- out => [ "vfp", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+ out => [ "fp", "none", "none" ] },
ins => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ],
outs => [ "res", "dummy", "M" ],
+ emit => 'fdiv%FR%FP%FM %AF',
am => "source,binary",
latency => 20,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfprem => {
- reg_req => { in => [ "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+fprem => {
+ reg_req => { in => [ "fp", "fp", "fpcw" ], out => [ "fp" ] },
ins => [ "left", "right", "fpcw" ],
+ emit => 'fprem1',
latency => 20,
units => [ "VFP" ],
mode => $mode_fp87,
attr_type => "ia32_x87_attr_t",
},
-vfabs => {
+fabs => {
irn_flags => [ "rematerializable" ],
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ reg_req => { in => [ "fp"], out => [ "fp" ] },
ins => [ "value" ],
+ emit => 'fabs',
latency => 2,
units => [ "VFP" ],
mode => $mode_fp87,
attr_type => "ia32_x87_attr_t",
},
-vfchs => {
+fchs => {
irn_flags => [ "rematerializable" ],
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ reg_req => { in => [ "fp"], out => [ "fp" ] },
+ emit => 'fchs',
ins => [ "value" ],
latency => 2,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfld => {
+fld => {
irn_flags => [ "rematerializable" ],
op_flags => [ "uses_memory", "fragile" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ],
- out => [ "vfp", "none", "none", "none", "none" ] },
+ out => [ "fp", "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
outs => [ "res", "unused", "M", "X_regular", "X_except" ],
+ emit => 'fld%FM %AM',
attr => "ir_mode *load_mode",
init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
attr_type => "ia32_x87_attr_t",
},
-vfst => {
+fst => {
irn_flags => [ "rematerializable" ],
op_flags => [ "uses_memory", "fragile" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp" ],
+ reg_req => { in => [ "gp", "gp", "none", "fp" ],
out => [ "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_regular", "X_except" ],
+ emit => 'fst%FP%FM %AM',
attr => "ir_mode *store_mode",
init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
attr_type => "ia32_x87_attr_t",
},
-vfild => {
+fild => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ],
- out => [ "vfp", "none", "none" ] },
+ out => [ "fp", "none", "none" ] },
outs => [ "res", "unused", "M" ],
ins => [ "base", "index", "mem" ],
+ emit => 'fild%FM %AM',
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfist => {
+fist => {
op_flags => [ "uses_memory", "fragile" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ],
+ reg_req => { in => [ "gp", "gp", "none", "fp", "fpcw" ],
out => [ "none", "none", "none", "none" ] },
ins => [ "base", "index", "mem", "val", "fpcw" ],
outs => [ "dummy", "M", "X_regular", "X_except" ],
+ emit => 'fist%FP%FM %AM',
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
# SSE3 fisttp instruction
-vfisttp => {
+fisttp => {
op_flags => [ "uses_memory", "fragile" ],
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp" ],
+ reg_req => { in => [ "gp", "gp", "none", "fp" ],
out => [ "in_r4", "none", "none", "none" ]},
ins => [ "base", "index", "mem", "val" ],
outs => [ "res", "M", "X_regular", "X_except" ],
+ emit => 'fisttp%FM %AM',
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfldz => {
+fldz => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
outs => [ "res" ],
+ emit => 'fldz',
latency => 4,
units => [ "VFP" ],
mode => $mode_fp87,
attr_type => "ia32_x87_attr_t",
},
-vfld1 => {
+fld1 => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
outs => [ "res" ],
+ emit => 'fld1',
latency => 4,
units => [ "VFP" ],
mode => $mode_fp87,
attr_type => "ia32_x87_attr_t",
},
-vfldpi => {
+fldpi => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
outs => [ "res" ],
+ emit => 'fldpi',
latency => 4,
units => [ "VFP" ],
mode => $mode_fp87,
attr_type => "ia32_x87_attr_t",
},
-vfldln2 => {
+fldln2 => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
outs => [ "res" ],
+ emit => 'fldln2',
latency => 4,
units => [ "VFP" ],
mode => $mode_fp87,
attr_type => "ia32_x87_attr_t",
},
-vfldlg2 => {
+fldlg2 => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
+ emit => 'fldlg2',
outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfldl2t => {
+fldl2t => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
+ emit => 'fldll2t',
outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vfldl2e => {
+fldl2e => {
irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
+ reg_req => { out => [ "fp" ] },
+ emit => 'fldl2e',
outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-vFucomFnstsw => {
+FucomFnstsw => {
+# we can't allow to rematerialize this node so we don't
+# accidently produce Phi(Fucom, Fucom(ins_permuted))
+# irn_flags => [ "rematerializable" ],
+ reg_req => { in => [ "fp", "fp" ], out => [ "eax" ] },
+ ins => [ "left", "right" ],
+ outs => [ "flags" ],
+ emit => "fucom%FP %F0\n".
+ "fnstsw %%ax",
+ attr => "bool ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
+ latency => 3,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
+ mode => $mode_gp
+},
+
+FucomppFnstsw => {
# we can't allow to rematerialize this node so we don't
# accidently produce Phi(Fucom, Fucom(ins_permuted))
# irn_flags => [ "rematerializable" ],
- reg_req => { in => [ "vfp", "vfp" ], out => [ "eax" ] },
+ reg_req => { in => [ "fp", "fp" ], out => [ "eax" ] },
ins => [ "left", "right" ],
outs => [ "flags" ],
+ emit => "fucom%FP %F0\n".
+ "fnstsw %%ax",
attr => "bool ins_permuted",
init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
latency => 3,
mode => $mode_gp
},
-vFucomi => {
+Fucomi => {
irn_flags => [ "rematerializable" ],
- reg_req => { in => [ "vfp", "vfp" ], out => [ "eflags" ] },
+ reg_req => { in => [ "fp", "fp" ], out => [ "eflags" ] },
ins => [ "left", "right" ],
outs => [ "flags" ],
+ emit => 'fucom%FPi %F0',
attr => "bool ins_permuted",
init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
latency => 3,
mode => $mode_gp
},
-vFtstFnstsw => {
+FtstFnstsw => {
# irn_flags => [ "rematerializable" ],
- reg_req => { in => [ "vfp" ], out => [ "eax" ] },
+ reg_req => { in => [ "fp" ], out => [ "eax" ] },
ins => [ "left" ],
outs => [ "flags" ],
+ emit => "ftst\n".
+ "fnstsw %%ax",
attr => "bool ins_permuted",
init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
latency => 3,
mode => $mode_flags,
},
-fadd => {
- state => "exc_pinned",
- emit => 'fadd%FP%FM %AF',
- latency => 4,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fmul => {
- state => "exc_pinned",
- emit => 'fmul%FP%FM %AF',
- latency => 4,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fsub => {
- state => "exc_pinned",
- emit => 'fsub%FR%FP%FM %AF',
- latency => 4,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fprem => {
- emit => 'fprem1',
- latency => 20,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fdiv => {
- state => "exc_pinned",
- emit => 'fdiv%FR%FP%FM %AF',
- latency => 20,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fabs => {
- emit => 'fabs',
- latency => 4,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fchs => {
- op_flags => [ "keep" ],
- irn_flags => [ "rematerializable" ],
- emit => 'fchs',
- latency => 4,
- attr_type => "ia32_x87_attr_t",
- constructors => {},
-},
-
-fld => {
- irn_flags => [ "rematerializable" ],
- state => "exc_pinned",
- emit => 'fld%FM %AM',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
- constructors => {},
-},
-
-fst => {
- irn_flags => [ "rematerializable" ],
- state => "exc_pinned",
- emit => 'fst%FP%FM %AM',
- mode => "mode_M",
- attr_type => "ia32_x87_attr_t",
- latency => 2,
- constructors => {},
-},
-
-fild => {
- state => "exc_pinned",
- emit => 'fild%FM %AM',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
- constructors => {},
-},
-
-fist => {
- state => "exc_pinned",
- emit => 'fist%FP%FM %AM',
- mode => "mode_M",
- attr_type => "ia32_x87_attr_t",
- latency => 2,
- constructors => {},
-},
-
-# SSE3 fisttp instruction
-fisttp => {
- state => "exc_pinned",
- emit => 'fisttp%FM %AM',
- mode => "mode_M",
- attr_type => "ia32_x87_attr_t",
- latency => 2,
- constructors => {},
-},
-
-fldz => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fldz',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-fld1 => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fld1',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-fldpi => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fldpi',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-fldln2 => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fldln2',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-fldlg2 => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fldlg2',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-fldl2t => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fldll2t',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-fldl2e => {
- op_flags => [ "constlike", "keep" ],
- irn_flags => [ "rematerializable" ],
- reg_req => { out => [ "vfp" ] },
- emit => 'fldl2e',
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
# fxch, fpush, fpop
# Note that it is NEVER allowed to do CSE on these nodes
# Moreover, note the virtual register requierements!
},
fpushCopy => {
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ reg_req => { in => [ "fp"], out => [ "fp" ] },
cmp_attr => "return 1;",
emit => 'fld %F0',
attr_type => "ia32_x87_attr_t",
latency => 3,
},
-FucomFnstsw => {
- reg_req => { },
- emit => "fucom%FP %F0\n".
- "fnstsw %%ax",
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-FucomppFnstsw => {
- reg_req => { },
- emit => "fucompp\n".
- "fnstsw %%ax",
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
-Fucomi => {
- reg_req => { },
- emit => 'fucom%FPi %F0',
- attr_type => "ia32_x87_attr_t",
- latency => 1,
-},
-
-FtstFnstsw => {
- reg_req => { },
- emit => "ftst\n".
- "fnstsw %%ax",
- attr_type => "ia32_x87_attr_t",
- latency => 2,
-},
-
# Spilling and reloading of SSE registers, hardcoded, not generated #
xxLoad => {
/* define this to construct SSE constants instead of load them */
#undef CONSTRUCT_SSE_CONST
-#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
+#define mode_fp (ia32_reg_classes[CLASS_ia32_fp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
}
} else {
if (tarval_is_null(tv)) {
- load = new_bd_ia32_vfldz(dbgi, block);
+ load = new_bd_ia32_fldz(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else if (tarval_is_one(tv)) {
- load = new_bd_ia32_vfld1(dbgi, block);
+ load = new_bd_ia32_fld1(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else {
smaller entities */
ls_mode = get_type_mode(get_entity_type(floatent));
base = get_symconst_base();
- load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
- ls_mode);
+ load = new_bd_ia32_fld(dbgi, block, base, noreg_GP, nomem,
+ ls_mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
arch_add_irn_flags(load, arch_irn_flags_rematerializable);
- res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
+ res = new_r_Proj(load, mode_fp, pn_ia32_fld_res);
}
}
#ifdef CONSTRUCT_SSE_CONST
if (ia32_cg_config.use_sse2)
cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D);
else
- cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
+ cnst = new_bd_ia32_fld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
set_ia32_am_sc(cnst, get_SymConst_entity(node));
set_ia32_use_frame(cnst);
} else {
build_address(am, op2, ia32_create_am_normal);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (mode_is_float(mode)) {
- new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
+ new_op2 = ia32_new_NoReg_fp(current_ir_graph);
} else {
new_op2 = noreg_GP;
}
build_address(am, op1, ia32_create_am_normal);
if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_vfp(current_ir_graph);
+ noreg = ia32_new_NoReg_fp(current_ir_graph);
} else {
noreg = noreg_GP;
}
return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fadd);
}
ia32_mark_non_am(node);
return gen_binop(node, op1, op2, new_bd_ia32_xMul,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fmul);
}
return gen_binop(node, op1, op2, new_bd_ia32_IMul,
match_commutative | match_am | match_mode_neutral |
if (ia32_cg_config.use_sse2)
return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fsub);
}
if (is_Const(op2)) {
if (ia32_cg_config.use_sse2) {
return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
} else {
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fdiv);
}
}
set_ia32_op_type(new_node, ia32_AddrModeS);
set_ia32_ls_mode(new_node, mode);
} else {
- new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
+ new_node = new_bd_ia32_fchs(dbgi, block, new_op);
}
} else {
new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
assert(!negate);
} else {
check_x87_floatmode(mode);
- new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
+ new_node = new_bd_ia32_fabs(dbgi, new_block, new_op);
SET_IA32_ORIG_NODE(new_node, node);
if (negate) {
- new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
+ new_node = new_bd_ia32_fchs(dbgi, new_block, new_node);
SET_IA32_ORIG_NODE(new_node, node);
}
}
new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
mode);
} else {
- new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem,
+ new_node = new_bd_ia32_fld(dbgi, block, base, idx, new_mem,
mode);
}
} else {
set_address(new_node, &addr);
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_add_irn_flags(new_node, arch_irn_flags_rematerializable);
}
if (ia32_cg_config.use_fisttp) {
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
- ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
- ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_vfisttp_res);
+ ir_node *vfisttp = new_bd_ia32_fisttp(dbgi, block, base, index, mem, val);
+ ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_fisttp_res);
be_new_Keep(block, 1, &value);
return vfisttp;
ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
/* do a fist */
- ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
+ ir_node *vfist = new_bd_ia32_fist(dbgi, block, base, index, mem, val, trunc_mode);
return vfist;
}
}
} else {
val = ia32_skip_float_downconv(val);
new_val = be_transform_node(val);
- new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
+ new_node = new_bd_ia32_fst(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
} else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
if (ia32_cg_config.use_fucomi) {
new_right = be_transform_node(right);
- new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
+ new_node = new_bd_ia32_Fucomi(dbgi, new_block, new_left,
new_right, 0);
set_ia32_commutative(new_node);
SET_IA32_ORIG_NODE(new_node, node);
} else {
if (is_Const_0(right)) {
- new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
+ new_node = new_bd_ia32_FtstFnstsw(dbgi, new_block, new_left, 0);
} else {
new_right = be_transform_node(right);
- new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
+ new_node = new_bd_ia32_FucomFnstsw(dbgi, new_block, new_left, new_right, 0);
set_ia32_commutative(new_node);
}
if (ia32_cg_config.use_sse2)
load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
else
- load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
+ load = new_bd_ia32_fld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
set_am_attributes(load, &am);
- return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
+ return new_rd_Proj(NULL, load, mode_fp, pn_ia32_res);
}
panic("cannot transform floating point Mux");
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
- assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
- mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
+ assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
+ mem = new_r_Proj(fist, mode_M, pn_ia32_fist_M);
assert(get_mode_size_bits(mode) <= 32);
/* exception we can only store signed 32 bit integers, so for unsigned
ir_node *store, *load;
ir_node *new_node;
- store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
+ store = new_bd_ia32_fst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
SET_IA32_ORIG_NODE(store, node);
- store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+ store_mem = new_r_Proj(store, mode_M, pn_ia32_fst_M);
- load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
+ load = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
SET_IA32_ORIG_NODE(load, node);
- new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_vfld_res);
+ new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_fld_res);
return new_node;
}
if (am.op_type == ia32_AddrModeS) {
ia32_address_t *addr = &am.addr;
- fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
- new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ fild = new_bd_ia32_fild(dbgi, block, addr->base, addr->index, addr->mem);
+ new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
set_am_attributes(fild, &am);
SET_IA32_ORIG_NODE(fild, node);
}
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
+ fild = new_bd_ia32_fild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_ls_mode(fild, store_mode);
- new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
return new_node;
}
store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
/* load into x87 register */
- fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode);
+ fld = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
- mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
- fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
+ mproj = new_r_Proj(fld, mode_M, pn_ia32_fld_M);
+ fld = new_r_Proj(fld, mode_fp, pn_ia32_fld_res);
/* create a new return */
arity = get_irn_arity(node);
mode = mode_xmm;
req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
} else {
- mode = mode_vfp;
- req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
+ mode = mode_fp;
+ req = ia32_reg_classes[CLASS_ia32_fp].class_req;
}
} else {
req = arch_no_register_req;
sync = new_rd_Sync(dbgi, block, 2, in);
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
+ fild = new_bd_ia32_fild(dbgi, block, frame, noreg_GP, sync);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
SET_IA32_ORIG_NODE(fild, node);
- res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ res = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
if (! mode_is_signed(get_irn_mode(val_high))) {
ia32_address_mode_t am;
am.mem_proj = nomem;
am.op_type = ia32_AddrModeS;
am.new_op1 = res;
- am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
+ am.new_op2 = ia32_new_NoReg_fp(current_ir_graph);
am.pinned = op_pin_state_floats;
am.commutative = 1;
am.ins_permuted = false;
- fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
+ fadd = new_bd_ia32_fadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
am.new_op1, am.new_op2, get_fpcw());
set_am_attributes(fadd, &am);
set_irn_mode(fadd, mode_T);
- res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
+ res = new_rd_Proj(NULL, fadd, mode_fp, pn_ia32_res);
}
return res;
}
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
- assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
- return new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
+ assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
+ return new_r_Proj(fist, mode_M, pn_ia32_fist_M);
}
static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
}
- } else if (is_ia32_vfld(new_pred)) {
+ } else if (is_ia32_fld(new_pred)) {
switch ((pn_Load)proj) {
case pn_Load_res:
- return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
+ return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fld_res);
case pn_Load_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fld_M);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_except);
case pn_Load_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_regular);
}
} else {
/* can happen for ProJMs when source address mode happened for the
case pn_Store_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
}
- } else if (is_ia32_vfist(new_pred)) {
+ } else if (is_ia32_fist(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fist_M);
case pn_Store_X_except:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_except);
case pn_Store_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_regular);
}
- } else if (is_ia32_vfisttp(new_pred)) {
+ } else if (is_ia32_fisttp(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fisttp_M);
case pn_Store_X_except:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_except);
case pn_Store_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_regular);
}
- } else if (is_ia32_vfst(new_pred)) {
+ } else if (is_ia32_fst(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fst_M);
case pn_Store_X_except:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_except);
case pn_Store_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_regular);
}
} else if (is_ia32_xStore(new_pred)) {
switch ((pn_Store)pn) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
} else if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
- } else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
+ } else if (is_ia32_fdiv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fdiv_M);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
} else if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
- } else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ } else if (is_ia32_fdiv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fdiv_res);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_add_irn_flags(load, arch_irn_flags_rematerializable);
}
}
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_add_irn_flags(load, arch_irn_flags_rematerializable);
}
be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
- be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
+ be_set_transform_function(op_ia32_NoReg_FP, be_duplicate_node);
be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
be_set_transform_function(op_ia32_Push, be_duplicate_node);
ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
- irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
+ irg_data->noreg_fp = be_pre_transform_node(irg_data->noreg_fp);
irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
continue;
}
- res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
+ res = be_get_Proj_for_pn(call, pn_ia32_Call_st0 + j);
new_res = NULL;
/* now patch the users */
ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
ir_mode *mode = get_ia32_ls_mode(succ);
- ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode);
- //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M);
+ ir_node *st = new_bd_ia32_fst(db, block, base, idx, mem, value, mode);
+ //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_fst_M);
set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
if (is_ia32_use_frame(succ))
set_ia32_use_frame(st);
set_irn_pinned(st, get_irn_pinned(succ));
set_ia32_op_type(st, ia32_AddrModeD);
- assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M);
- assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular);
- assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except);
+ assert((long)pn_ia32_xStore_M == (long)pn_ia32_fst_M);
+ assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_fst_X_regular);
+ assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_fst_X_except);
exchange(succ, st);
ir_node *vfst_mem;
/* store st(0) on stack */
- vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem,
+ vfst = new_bd_ia32_fst(db, block, frame, noreg_GP, call_mem,
res, res_mode);
set_ia32_op_type(vfst, ia32_AddrModeD);
set_ia32_use_frame(vfst);
- vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M);
+ vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_fst_M);
/* load into SSE register */
xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
#include "ia32_x87.h"
#include "ia32_architecture.h"
+#define N_FLOAT_REGS (N_ia32_fp_REGS-1) // exclude NOREG
+
/** the debug handle */
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
* The x87 state.
*/
typedef struct x87_state {
- st_entry st[N_ia32_st_REGS]; /**< the register stack */
- int depth; /**< the current stack depth */
- x87_simulator *sim; /**< The simulator. */
+ st_entry st[N_FLOAT_REGS]; /**< the register stack */
+ int depth; /**< the current stack depth */
+ x87_simulator *sim; /**< The simulator. */
} x87_state;
/** An empty state, used for blocks without fp instructions. */
x87_state *end; /**< state at the end or NULL if not assigned */
} blk_state;
-/** liveness bitset for vfp registers. */
-typedef unsigned char vfp_liveness;
+/** liveness bitset for fp registers. */
+typedef unsigned char fp_liveness;
/**
* The x87 simulator.
struct obstack obst; /**< An obstack for fast allocating. */
pmap *blk_states; /**< Map blocks to states. */
be_lv_t *lv; /**< intrablock liveness. */
- vfp_liveness *live; /**< Liveness information. */
+ fp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
waitq *worklist; /**< Worklist of blocks that must be processed. */
};
static st_entry *x87_get_entry(x87_state *const state, int const pos)
{
assert(0 <= pos && pos < state->depth);
- return &state->st[N_ia32_st_REGS - state->depth + pos];
+ return &state->st[N_FLOAT_REGS - state->depth + pos];
}
/**
* @param state the x87 state
* @param pos a stack position
*
- * @return the vfp register index that produced the value at st(pos)
+ * @return the fp register index that produced the value at st(pos)
*/
static int x87_get_st_reg(const x87_state *state, int pos)
{
* Set a virtual register to st(pos).
*
* @param state the x87 state
- * @param reg_idx the vfp register index that should be set
- * @param node the IR node that produces the value of the vfp register
+ * @param reg_idx the fp register index that should be set
+ * @param node the IR node that produces the value of the fp register
* @param pos the stack position where the new value should be entered
*/
static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
* Convert a virtual register to the stack index.
*
* @param state the x87 state
- * @param reg_idx the register vfp index
+ * @param reg_idx the register fp index
*
* @return the stack position where the register is stacked
* or -1 if the virtual register was not found
* Push a virtual Register onto the stack, double pushes are NOT allowed.
*
* @param state the x87 state
- * @param reg_idx the register vfp index
- * @param node the node that produces the value of the vfp register
+ * @param reg_idx the register fp index
+ * @param node the node that produces the value of the fp register
*/
static void x87_push(x87_state *state, int reg_idx, ir_node *node)
{
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
- assert(state->depth < N_ia32_st_REGS && "stack overrun");
+ assert(state->depth < N_FLOAT_REGS && "stack overrun");
++state->depth;
st_entry *const entry = x87_get_entry(state, 0);
return res;
}
-/**
- * Patch a virtual instruction into a x87 one and return
- * the node representing the result value.
- *
- * @param n the IR node to patch
- * @param op the x87 opcode to patch in
- */
-static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
-{
- ir_mode *mode = get_irn_mode(n);
- ir_node *res = n;
-
- set_irn_op(n, op);
-
- if (mode == mode_T) {
- /* patch all Proj's */
- foreach_out_edge(n, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- if (is_Proj(proj)) {
- mode = get_irn_mode(proj);
- if (mode_is_float(mode)) {
- res = proj;
- set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
- }
- }
- }
- } else if (mode_is_float(mode))
- set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
- return res;
-}
-
/**
* Returns the first Proj of a mode_T node having a given mode.
*
{
const arch_register_t *res = arch_get_irn_register(irn);
- assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
+ assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
return res;
}
{
const arch_register_t *res = arch_get_irn_register_out(irn, pos);
- assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
+ assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
return res;
}
*
* @return The live bitset.
*/
-static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
+static fp_liveness fp_liveness_transfer(ir_node *irn, fp_liveness live)
{
int i, n;
- const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
+ const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
if (get_irn_mode(irn) == mode_T) {
foreach_out_edge(irn, edge) {
*
* @return The live bitset at the end of this block
*/
-static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
+static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
{
- vfp_liveness live = 0;
- const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
+ fp_liveness live = 0;
+ const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
const be_lv_t *lv = sim->lv;
be_lv_foreach(lv, block, be_lv_state_end, node) {
*
* @return The live bitset.
*/
-static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
+static unsigned fp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
{
unsigned idx = get_irn_idx(pos);
*/
static void update_liveness(x87_simulator *sim, ir_node *block)
{
- vfp_liveness live = vfp_liveness_end_of_block(sim, block);
+ fp_liveness live = fp_liveness_end_of_block(sim, block);
unsigned idx;
/* now iterate through the block backward and cache the results */
idx = get_irn_idx(irn);
sim->live[idx] = live;
- live = vfp_liveness_transfer(irn, live);
+ live = fp_liveness_transfer(irn, live);
}
idx = get_irn_idx(block);
sim->live[idx] = live;
/**
* Returns true if a register is live in a set.
*
- * @param reg_idx the vfp register index
+ * @param reg_idx the fp register index
* @param live a live bitset
*/
-#define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
+#define is_fp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
#ifdef DEBUG_libfirm
/**
*
* @param live the live bitset
*/
-static void vfp_dump_live(vfp_liveness live)
+static void fp_dump_live(fp_liveness live)
{
int i;
*
* @return NO_NODE_ADDED
*/
-static int sim_binop(x87_state *const state, ir_node *const n, ir_op *const op)
+static int sim_binop(x87_state *const state, ir_node *const n)
{
- ir_node *patched_insn;
x87_simulator *sim = state->sim;
ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
int reg_index_1 = op1_reg->index;
int reg_index_2 = op2_reg->index;
- vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
+ fp_liveness live = fp_live_args_after(sim, n, REGMASK(out));
int op1_live_after;
int op2_live_after;
DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, op1_reg->name, op2_reg->name, out->name));
- DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(fp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state);)
int op1_idx = x87_on_stack(state, reg_index_1);
assert(op1_idx >= 0);
- op1_live_after = is_vfp_live(reg_index_1, live);
+ op1_live_after = is_fp_live(reg_index_1, live);
int op2_idx;
int out_idx;
bool pop = false;
int const out_reg_idx = out->index;
ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
- if (reg_index_2 != REG_VFP_VFP_NOREG) {
- /* second operand is a vfp register */
+ if (reg_index_2 != REG_FP_FP_NOREG) {
+ /* second operand is a fp register */
op2_idx = x87_on_stack(state, reg_index_2);
assert(op2_idx >= 0);
- op2_live_after = is_vfp_live(reg_index_2, live);
+ op2_live_after = is_fp_live(reg_index_2, live);
if (op2_live_after) {
/* Second operand is live. */
assert(op1_idx == 0 || op2_idx == 0);
assert(out_idx == op1_idx || out_idx == op2_idx);
- patched_insn = x87_patch_insn(n, op);
- x87_set_st(state, out_reg_idx, patched_insn, out_idx);
+ x87_set_st(state, out_reg_idx, n, out_idx);
if (pop)
x87_pop(state);
*
* @param state the x87 state
* @param n the node that should be simulated (and patched)
- * @param op the x87 opcode that will replace n's opcode
*
* @return NO_NODE_ADDED
*/
-static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
+static int sim_unop(x87_state *state, ir_node *n)
{
arch_register_t const *const out = x87_get_irn_register(n);
- unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
+ unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
- DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(fp_dump_live(live);)
ir_node *const op1 = get_irn_n(n, 0);
arch_register_t const *const op1_reg = x87_get_irn_register(op1);
int const op1_reg_idx = op1_reg->index;
int const op1_idx = x87_on_stack(state, op1_reg_idx);
int const out_reg_idx = out->index;
- if (is_vfp_live(op1_reg_idx, live)) {
+ if (is_fp_live(op1_reg_idx, live)) {
/* push the operand here */
x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
} else {
}
}
- x87_set_st(state, out_reg_idx, x87_patch_insn(n, op), 0);
+ x87_set_st(state, out_reg_idx, n, 0);
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
return NO_NODE_ADDED;
*
* @param state the x87 state
* @param n the node that should be simulated (and patched)
- * @param op the x87 opcode that will replace n's opcode
*
* @return NO_NODE_ADDED
*/
-static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
+static int sim_load(x87_state *state, ir_node *n)
{
- const arch_register_t *out = x87_irn_get_register(n, res_pos);
+ assert((int)pn_ia32_fld_res == (int)pn_ia32_fild_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_fld1_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_fldz_res);
+ const arch_register_t *out = x87_irn_get_register(n, pn_ia32_fld_res);
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
- x87_push(state, out->index, x87_patch_insn(n, op));
- assert(out == x87_irn_get_register(n, res_pos));
+ x87_push(state, out->index, n);
+ assert(out == x87_irn_get_register(n, pn_ia32_fld_res));
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
return NO_NODE_ADDED;
*
* @param state the x87 state
* @param n the node that should be simulated (and patched)
- * @param op the x87 store opcode
*/
-static int sim_store(x87_state *state, ir_node *n, ir_op *op)
+static int sim_store(x87_state *state, ir_node *n)
{
- ir_node *const val = get_irn_n(n, n_ia32_vfst_val);
+ ir_node *const val = get_irn_n(n, n_ia32_fst_val);
arch_register_t const *const op2 = x87_get_irn_register(val);
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
int insn = NO_NODE_ADDED;
int const op2_reg_idx = op2->index;
int const op2_idx = x87_on_stack(state, op2_reg_idx);
- unsigned const live = vfp_live_args_after(state->sim, n, 0);
- int const live_after_node = is_vfp_live(op2_reg_idx, live);
+ unsigned const live = fp_live_args_after(state->sim, n, 0);
+ int const live_after_node = is_fp_live(op2_reg_idx, live);
assert(op2_idx >= 0);
if (live_after_node) {
/* Problem: fst doesn't support 80bit modes (spills), only fstp does
* Note that we cannot test on mode_E, because floats might be 80bit ... */
ir_mode *const mode = get_ia32_ls_mode(n);
if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
- if (x87_get_depth(state) < N_ia32_st_REGS) {
+ if (x87_get_depth(state) < N_FLOAT_REGS) {
/* ok, we have a free register: push + fstp */
- x87_create_fpush(state, n, op2_idx, REG_VFP_VFP_NOREG, val);
- x87_patch_insn(n, op);
+ x87_create_fpush(state, n, op2_idx, REG_FP_FP_NOREG, val);
do_pop = true;
} else {
/* stack full here: need fstp + load */
- x87_patch_insn(n, op);
do_pop = true;
ir_node *const block = get_nodes_block(n);
ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
- ir_node *const vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
+ ir_node *const vfld = new_bd_ia32_fld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
/* copy all attributes */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, mode);
- ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_vfld_res);
- ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
+ ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_fld_res);
+ ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_fld_M);
arch_set_irn_register(rproj, op2);
/* we can only store the tos to memory */
if (op2_idx != 0)
x87_create_fxch(state, n, op2_idx);
-
- /* mode size 64 or smaller -> use normal fst */
- x87_patch_insn(n, op);
}
} else {
/* we can only store the tos to memory */
if (op2_idx != 0)
x87_create_fxch(state, n, op2_idx);
- x87_patch_insn(n, op);
do_pop = true;
}
return insn;
}
-#define GEN_BINOP(op) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_binop(state, n, op_ia32_##op); \
-}
-
-#define GEN_LOAD(op) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
-}
-
-#define GEN_UNOP(op) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_unop(state, n, op_ia32_##op); \
-}
-
-#define GEN_STORE(op) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_store(state, n, op_ia32_##op); \
-}
-
-/* all stubs */
-GEN_BINOP(fadd)
-GEN_BINOP(fsub)
-GEN_BINOP(fmul)
-GEN_BINOP(fdiv)
-
-GEN_UNOP(fabs)
-GEN_UNOP(fchs)
-
-GEN_LOAD(fld)
-GEN_LOAD(fild)
-GEN_LOAD(fldz)
-GEN_LOAD(fld1)
-
-GEN_STORE(fst)
-GEN_STORE(fist)
-
static int sim_fprem(x87_state *const state, ir_node *const n)
{
(void)state;
*/
static int sim_fisttp(x87_state *state, ir_node *n)
{
- ir_node *val = get_irn_n(n, n_ia32_vfst_val);
+ ir_node *val = get_irn_n(n, n_ia32_fst_val);
const arch_register_t *op2 = x87_get_irn_register(val);
int const op2_idx = x87_on_stack(state, op2->index);
x87_create_fxch(state, n, op2_idx);
x87_pop(state);
- x87_patch_insn(n, op_ia32_fisttp);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
static int sim_FtstFnstsw(x87_state *state, ir_node *n)
{
x87_simulator *sim = state->sim;
- ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
+ ir_node *op1_node = get_irn_n(n, n_ia32_FtstFnstsw_left);
const arch_register_t *reg1 = x87_get_irn_register(op1_node);
int reg_index_1 = reg1->index;
int op1_idx = x87_on_stack(state, reg_index_1);
- unsigned live = vfp_live_args_after(sim, n, 0);
+ unsigned live = fp_live_args_after(sim, n, 0);
DB((dbg, LEVEL_1, ">>> %+F %s\n", n, reg1->name));
- DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(fp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state);)
assert(op1_idx >= 0);
x87_create_fxch(state, n, op1_idx);
}
- /* patch the operation */
- x87_patch_insn(n, op_ia32_FtstFnstsw);
-
- if (!is_vfp_live(reg_index_1, live))
+ if (!is_fp_live(reg_index_1, live))
x87_create_fpop(state, sched_next(n), 0);
return NO_NODE_ADDED;
*/
static int sim_Fucom(x87_state *state, ir_node *n)
{
- ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
- ir_op *dst;
- x87_simulator *sim = state->sim;
- ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
- ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
- const arch_register_t *op1 = x87_get_irn_register(op1_node);
- const arch_register_t *op2 = x87_get_irn_register(op2_node);
+ ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
+ x87_simulator *sim = state->sim;
+ ir_node *op1_node = get_irn_n(n, n_ia32_FucomFnstsw_left);
+ ir_node *op2_node = get_irn_n(n, n_ia32_FucomFnstsw_right);
+ const arch_register_t *op1 = x87_get_irn_register(op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(op2_node);
int reg_index_1 = op1->index;
int reg_index_2 = op2->index;
- unsigned live = vfp_live_args_after(sim, n, 0);
+ unsigned live = fp_live_args_after(sim, n, 0);
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, op1->name, op2->name));
- DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(fp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state);)
int op2_idx;
int pops = 0;
/* BEWARE: check for comp a,a cases, they might happen */
- if (reg_index_2 != REG_VFP_VFP_NOREG) {
- /* second operand is a vfp register */
+ if (reg_index_2 != REG_FP_FP_NOREG) {
+ /* second operand is a fp register */
op2_idx = x87_on_stack(state, reg_index_2);
assert(op2_idx >= 0);
- if (is_vfp_live(reg_index_2, live)) {
+ if (is_fp_live(reg_index_2, live)) {
/* second operand is live */
- if (is_vfp_live(reg_index_1, live)) {
+ if (is_fp_live(reg_index_1, live)) {
/* both operands are live */
if (op1_idx != 0 && op2_idx != 0) {
/* bring the first one to tos */
}
} else {
/* second operand is dead */
- if (is_vfp_live(reg_index_1, live)) {
+ if (is_fp_live(reg_index_1, live)) {
/* first operand is live: bring second to tos.
This means further, op1_idx != op2_idx. */
assert(op1_idx != op2_idx);
if (op1_idx != 0)
x87_create_fxch(state, n, op1_idx);
/* Pop first operand, if it is dead. */
- if (!is_vfp_live(reg_index_1, live))
+ if (!is_fp_live(reg_index_1, live))
pops = 1;
op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
assert(op1_idx == 0 || op2_idx == 0);
/* patch the operation */
- if (is_ia32_vFucomFnstsw(n)) {
- if (pops == 2 && (op1_idx == 1 || op2_idx == 1)) {
- dst = op_ia32_FucomppFnstsw;
- x87_pop(state);
- x87_pop(state);
- } else {
- dst = op_ia32_FucomFnstsw;
- goto pop;
- }
- } else if (is_ia32_vFucomi(n)) {
- dst = op_ia32_Fucomi;
-pop:
+ if (is_ia32_FucomFnstsw(n) && pops == 2
+ && (op1_idx == 1 || op2_idx == 1)) {
+ set_irn_op(n, op_ia32_FucomppFnstsw);
+ x87_pop(state);
+ x87_pop(state);
+ } else {
if (pops != 0)
x87_pop(state);
if (pops == 2) {
int const idx = (op1_idx != 0 ? op1_idx : op2_idx) - 1 /* Due to prior pop. */;
x87_create_fpop(state, sched_next(n), idx);
}
- } else {
- panic("invalid operation %+F", n);
}
- x87_patch_insn(n, dst);
-
int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
attr->attr.data.ins_permuted = op1_idx != 0;
for (i = 0; i < arity; ++i) {
op = get_irn_n(node, i);
op_reg = arch_get_irn_register(op);
- if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_vfp])
+ if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_fp])
continue;
reg_id = op_reg->index;
- live = vfp_live_args_after(state->sim, node, 0);
+ live = fp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
- if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
+ if (op_stack_idx >= 0 && !is_fp_live(reg_id, live))
x87_create_fpop(state, sched_next(node), 0);
}
ir_mode *mode = get_irn_mode(n);
ir_node *block = get_nodes_block(n);
ir_node *pred = get_irn_n(n, 0);
- ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
+ ir_node *(*cnstr)(dbg_info *, ir_node *) = NULL;
ir_node *res;
const arch_register_t *out;
const arch_register_t *op1;
if (cnstr != NULL) {
/* copy a constant */
- res = (*cnstr)(n_dbg, block, mode);
+ res = (*cnstr)(n_dbg, block);
x87_push(state, out->index, res);
} else {
static int sim_Copy(x87_state *state, ir_node *n)
{
arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
- if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
+ if (cls != &ia32_reg_classes[CLASS_ia32_fp])
return NO_NODE_ADDED;
ir_node *const pred = be_get_Copy_op(n);
arch_register_t const *const op1 = x87_get_irn_register(pred);
arch_register_t const *const out = x87_get_irn_register(n);
- unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
+ unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, op1->name, out->name));
- DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(fp_dump_live(live);)
- if (is_vfp_live(op1->index, live)) {
+ if (is_fp_live(op1->index, live)) {
/* Operand is still live, a real copy. We need here an fpush that can
hold a a register, so use the fpushCopy or recreate constants */
ir_node *const node = create_Copy(state, n);
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
- if (pn == pn_ia32_Call_vf0)
+ if (pn == pn_ia32_Call_st0)
return proj;
}
for (size_t i = get_irn_arity(n); i-- != 0;) {
arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
- if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
panic("cannot handle %+F with x87 constraints", n);
}
for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
- if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
panic("cannot handle %+F with x87 constraints", n);
}
{
ir_node *first_insn = sched_first(block);
ir_node *keep = NULL;
- unsigned live = vfp_live_args_after(sim, block, 0);
+ unsigned live = fp_live_args_after(sim, block, 0);
unsigned kill_mask;
int i, depth;
for (i = depth - 1; i >= 0; --i) {
int reg = x87_get_st_reg(state, i);
- if (! is_vfp_live(reg, live))
+ if (! is_fp_live(reg, live))
kill_mask |= (1 << i);
}
if (kill_mask) {
DB((dbg, LEVEL_1, "Killing deads:\n"));
- DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(fp_dump_live(live);)
DEBUG_ONLY(x87_dump_stack(state);)
if (kill_mask != 0 && live == 0) {
obstack_init(&sim->obst);
sim->blk_states = pmap_create();
sim->n_idx = get_irg_last_idx(irg);
- sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
+ sim->live = OALLOCN(&sim->obst, fp_liveness, sim->n_idx);
DB((dbg, LEVEL_1, "--------------------------------\n"
"x87 Simulator started for %+F\n", irg));
register_sim(op_ia32_Asm, sim_Asm);
register_sim(op_ia32_Call, sim_Call);
- register_sim(op_ia32_vfld, sim_fld);
- register_sim(op_ia32_vfild, sim_fild);
- register_sim(op_ia32_vfld1, sim_fld1);
- register_sim(op_ia32_vfldz, sim_fldz);
- register_sim(op_ia32_vfadd, sim_fadd);
- register_sim(op_ia32_vfsub, sim_fsub);
- register_sim(op_ia32_vfmul, sim_fmul);
- register_sim(op_ia32_vfdiv, sim_fdiv);
- register_sim(op_ia32_vfprem, sim_fprem);
- register_sim(op_ia32_vfabs, sim_fabs);
- register_sim(op_ia32_vfchs, sim_fchs);
- register_sim(op_ia32_vfist, sim_fist);
- register_sim(op_ia32_vfisttp, sim_fisttp);
- register_sim(op_ia32_vfst, sim_fst);
- register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
- register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
- register_sim(op_ia32_vFucomi, sim_Fucom);
+ register_sim(op_ia32_fld, sim_load);
+ register_sim(op_ia32_fild, sim_load);
+ register_sim(op_ia32_fld1, sim_load);
+ register_sim(op_ia32_fldz, sim_load);
+ register_sim(op_ia32_fadd, sim_binop);
+ register_sim(op_ia32_fsub, sim_binop);
+ register_sim(op_ia32_fmul, sim_binop);
+ register_sim(op_ia32_fdiv, sim_binop);
+ register_sim(op_ia32_fprem, sim_fprem);
+ register_sim(op_ia32_fabs, sim_unop);
+ register_sim(op_ia32_fchs, sim_unop);
+ register_sim(op_ia32_fist, sim_store);
+ register_sim(op_ia32_fisttp, sim_fisttp);
+ register_sim(op_ia32_fst, sim_store);
+ register_sim(op_ia32_FtstFnstsw, sim_FtstFnstsw);
+ register_sim(op_ia32_FucomFnstsw, sim_Fucom);
+ register_sim(op_ia32_Fucomi, sim_Fucom);
register_sim(op_be_Copy, sim_Copy);
register_sim(op_be_Return, sim_Return);
register_sim(op_be_Perm, sim_Perm);
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