static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
- const arch_register_class_t *cls0, *cls1;
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
- cls0 = arch_register_get_class(in0);
- cls1 = arch_register_get_class(in1);
-
- assert(cls0 == cls1 && "Register class mismatch at Perm");
+ arch_register_class_t const* const cls0 = in0->reg_class;
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
amd64_emitf(node, "xchg %R, %R", in0, in1);
keep = be_new_Keep(bl, n, in);
for (i = 0; i < n; ++i) {
const arch_register_t *reg = (const arch_register_t*)get_irn_link(in[i]);
- be_node_set_reg_class_in(keep, i, arch_register_get_class(reg));
+ be_node_set_reg_class_in(keep, i, reg->reg_class);
}
}
if (req->type == arch_register_req_type_none)
return false;
if (req->type & arch_register_req_type_limited) {
- if (arch_register_get_class(reg) != req->cls)
+ if (reg->reg_class != req->cls)
return false;
return rbitset_is_set(req->limited, reg->index);
}
- return req->cls == arch_register_get_class(reg);
+ return req->cls == reg->reg_class;
}
void arch_dump_register_req(FILE *F, const arch_register_req_t *req,
unsigned short dwarf_number;
};
-static inline const arch_register_class_t *arch_register_get_class(
- const arch_register_t *reg)
-{
- return reg->reg_class;
-}
-
/**
* A class of registers.
* Like general purpose or floating point.
const arch_register_t *reg, arch_register_req_type_t additional_types)
{
arch_register_req_t *req = OALLOC(obst, arch_register_req_t);
- const arch_register_class_t *cls = arch_register_get_class(reg);
+ const arch_register_class_t *cls = reg->reg_class;
unsigned *limited_bitset;
limited_bitset = rbitset_obstack_alloc(obst, arch_register_class_n_regs(cls));
= arch_get_irn_register_req_out(start, i);
if (! (out_req->type & arch_register_req_type_limited))
continue;
- if (out_req->cls != arch_register_get_class(reg))
+ if (out_req->cls != reg->reg_class)
continue;
if (!rbitset_is_set(out_req->limited, reg->index))
continue;
{
int i = get_start_reg_index(irg, reg);
ir_node *start = get_irg_start(irg);
- ir_mode *mode = arch_register_class_mode(arch_register_get_class(reg));
+ ir_mode *mode = arch_register_class_mode(reg->reg_class);
foreach_out_edge(start, edge) {
ir_node *proj = get_edge_src_irn(edge);
const arch_register_req_t *req = arch_get_irn_register_req_in(ret, i);
if (! (req->type & arch_register_req_type_limited))
continue;
- if (req->cls != arch_register_get_class(reg))
+ if (req->cls != reg->reg_class)
continue;
if (!rbitset_is_set(req->limited, reg->index))
continue;
new_sp_req = OALLOCZ(obst, arch_register_req_t);
new_sp_req->type = arch_register_req_type_limited
| arch_register_req_type_produces_sp;
- new_sp_req->cls = arch_register_get_class(arch_env->sp);
+ new_sp_req->cls = arch_env->sp->reg_class;
new_sp_req->width = 1;
limited_bitset = rbitset_obstack_alloc(obst, new_sp_req->cls->n_regs);
req = OALLOCZ(obst, arch_register_req_t);
req->type = arch_register_req_type_limited;
- req->cls = arch_register_get_class(reg);
+ req->cls = reg->reg_class;
req->limited = limited;
req->width = 1;
return;
}
/* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
return;
ia32_emitf(node, "movl %R, %R", in, out);
static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
- const arch_register_class_t *cls0, *cls1;
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
- cls0 = arch_register_get_class(in0);
- cls1 = arch_register_get_class(in1);
-
- assert(cls0 == cls1 && "Register class mismatch at Perm");
+ arch_register_class_t const *const cls0 = in0->reg_class;
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
ia32_emitf(node, "xchg %R, %R", in1, in0);
if (in == out)
return;
/* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
return;
- assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
+ assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
bemit8(0x8B);
bemit_modrr(in, out);
}
{
const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
- const arch_register_class_t *cls0 = arch_register_get_class(in0);
+ const arch_register_class_t *cls0 = in0->reg_class;
- assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
if (in0->index == REG_GP_EAX) {
int same_pos;
ir_node *uses_out_reg;
const arch_register_req_t *req = arch_get_irn_register_req_out(node, i);
- const arch_register_class_t *cls;
int uses_out_reg_pos;
if (!arch_register_req_is(req, should_be_same))
/* requirement already fulfilled? */
if (in_reg == out_reg)
continue;
- cls = arch_register_get_class(in_reg);
- assert(cls == arch_register_get_class(out_reg));
+ assert(in_reg->reg_class == out_reg->reg_class);
/* check if any other input operands uses the out register */
arity = get_irn_arity(node);
for (i = 0; i < arity; ++i) {
op = get_irn_n(node, i);
op_reg = arch_get_irn_register(op);
- if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
+ if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_vfp])
continue;
reg_id = op_reg->index;