be_emit_init_env(&isa->emit, outfile);
- TEMPLATE_register_init(isa);
+ TEMPLATE_register_init();
TEMPLATE_create_opcodes();
return isa;
-static int TEMPLATE_get_n_reg_class(const void *self) {
+static int TEMPLATE_get_n_reg_class(const void *self)
+{
+ (void) self;
return N_CLASSES;
}
-static const arch_register_class_t *TEMPLATE_get_reg_class(const void *self, int i) {
+static const arch_register_class_t *TEMPLATE_get_reg_class(const void *self,
+ int i)
+{
+ (void) self;
assert(i >= 0 && i < N_CLASSES && "Invalid TEMPLATE register class requested.");
return &TEMPLATE_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *TEMPLATE_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+const arch_register_class_t *TEMPLATE_get_reg_class_for_mode(const void *self,
+ const ir_mode *mode)
+{
+ (void) self;
if (mode_is_float(mode))
return &TEMPLATE_reg_classes[CLASS_TEMPLATE_floating_point];
else
* @param self The callback object.
* @return The between type of for that call.
*/
-static ir_type *TEMPLATE_get_between_type(void *self) {
- //TEMPLATE_abi_env_t *env = self;
+static ir_type *TEMPLATE_get_between_type(void *self)
+{
static ir_type *between_type = NULL;
- static ir_entity *old_bp_ent = NULL;
+ static ir_entity *old_bp_ent = NULL;
+ (void) self;
if(!between_type) {
ir_entity *ret_addr_ent;
/**
* Build the prolog, return the BASE POINTER register
*/
-static const arch_register_t *TEMPLATE_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
+static const arch_register_t *TEMPLATE_abi_prologue(void *self, ir_node **mem,
+ pmap *reg_map)
+{
TEMPLATE_abi_env_t *env = self;
+ (void) reg_map;
+ (void) mem;
if(env->flags.try_omit_fp)
return env->isa->sp;
}
/* Build the epilog */
-static void TEMPLATE_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
- //TEMPLATE_abi_env_t *env = self;
+static void TEMPLATE_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
+ pmap *reg_map)
+{
+ (void) self;
+ (void) bl;
+ (void) mem;
+ (void) reg_map;
}
static const be_abi_callbacks_t TEMPLATE_abi_callbacks = {
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-void TEMPLATE_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+void TEMPLATE_get_call_abi(const void *self, ir_type *method_type,
+ be_abi_call_t *abi)
+{
ir_type *tp;
ir_mode *mode;
int i, n = get_method_n_params(method_type);
be_abi_call_flags_t call_flags;
+ (void) self;
/* set abi flags for calls */
call_flags.bits.left_to_right = 0;
}
}
-static const void *TEMPLATE_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
+static const void *TEMPLATE_get_irn_ops(const arch_irn_handler_t *self,
+ const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
return &TEMPLATE_irn_ops;
}
TEMPLATE_get_irn_ops
};
-const arch_irn_handler_t *TEMPLATE_get_irn_handler(const void *self) {
+const arch_irn_handler_t *TEMPLATE_get_irn_handler(const void *self)
+{
+ (void) self;
return &TEMPLATE_irn_handler;
}
-int TEMPLATE_to_appear_in_schedule(void *block_env, const ir_node *irn) {
+int TEMPLATE_to_appear_in_schedule(void *block_env, const ir_node *irn)
+{
+ (void) block_env;
+
if(!is_TEMPLATE_irn(irn))
return -1;
/**
* Initializes the code generator interface.
*/
-static const arch_code_generator_if_t *TEMPLATE_get_code_generator_if(void *self) {
+static const arch_code_generator_if_t *TEMPLATE_get_code_generator_if(
+ void *self)
+{
+ (void) self;
return &TEMPLATE_code_gen_if;
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-static const list_sched_selector_t *TEMPLATE_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
+static const list_sched_selector_t *TEMPLATE_get_list_sched_selector(
+ const void *self, list_sched_selector_t *selector)
+{
+ (void) self;
memcpy(&TEMPLATE_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
TEMPLATE_sched_selector.to_appear_in_schedule = TEMPLATE_to_appear_in_schedule;
return &TEMPLATE_sched_selector;
*/
static const
arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
- int pos) {
+ int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(node);
+ (void) self;
if (is_Block(node) || mode == mode_X || mode == mode_M) {
return arch_no_register_req;
return arch_no_register_req;
}
-static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void arm_set_irn_reg(const void *self, ir_node *irn,
+ const arch_register_t *reg)
+{
int pos = 0;
+ (void) self;
if (get_irn_mode(irn) == mode_X) {
return;
}
}
-static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *arm_get_irn_reg(const void *self,
+ const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
+ (void) self;
if (is_Proj(irn)) {
return reg;
}
-static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
+static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
+{
+ (void) self;
irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return 0;
}
-static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
+static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
+{
+ (void) self;
irn = skip_Proj_const(irn);
if (is_arm_irn(irn)) {
return 0;
}
-static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
/* TODO: return the entity assigned to the frame */
return NULL;
}
/* TODO: correct offset if irn accesses the stack */
}
-static int arm_get_sp_bias(const void *self, const ir_node *irn) {
+static int arm_get_sp_bias(const void *self, const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
return 0;
}
/**
* Called immediately before emit phase.
*/
-static void arm_finish_irg(void *self) {
+static void arm_finish_irg(void *self)
+{
+ (void) self;
/* TODO: - fix offsets for nodes accessing stack
- ...
*/
/**
* These are some hooks which must be filled but are probably not needed.
*/
-static void arm_before_sched(void *self) {
+static void arm_before_sched(void *self)
+{
+ (void) self;
/* Some stuff you need to do after scheduling but before register allocation */
}
-static void arm_before_ra(void *self) {
+static void arm_before_ra(void *self)
+{
+ (void) self;
/* Some stuff you need to do immediately after register allocation */
}
* We transform Spill and Reload here. This needs to be done before
* stack biasing otherwise we would miss the corrected offset for these nodes.
*/
-static void arm_after_ra(void *self) {
+static void arm_after_ra(void *self)
+{
arm_code_gen_t *cg = self;
be_coalesce_spillslots(cg->birg);
}
* 1.) A constant: simply move
* 2.) A load: simply load
*/
-static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
+static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
+{
+ (void) bl;
+
if (is_Const(arg)) {
tarval *tv = get_Const_tarval(arg);
unsigned v;
isa = xmalloc(sizeof(*isa));
memcpy(isa, &arm_isa_template, sizeof(*isa));
- arm_register_init(isa);
+ arm_register_init();
isa->cg = NULL;
be_emit_init_env(&isa->emit, file_handle);
return req->cls->n_regs;
}
-void arch_put_non_ignore_regs(const arch_env_t *env, const arch_register_class_t *cls, bitset_t *bs)
+void arch_put_non_ignore_regs(const arch_env_t *env,
+ const arch_register_class_t *cls, bitset_t *bs)
{
int i;
+ (void) env;
for(i = 0; i < cls->n_regs; ++i) {
if(!arch_register_type_is(&cls->regs[i], ignore))
}
}
-int arch_count_non_ignore_regs(const arch_env_t *env, const arch_register_class_t *cls)
+int arch_count_non_ignore_regs(const arch_env_t *env,
+ const arch_register_class_t *cls)
{
int i;
int result = 0;
+ (void) env;
for(i = 0; i < cls->n_regs; ++i) {
if(!arch_register_type_is(&cls->regs[i], ignore))
int *assignment;
pmap *partners;
int i, n_alloc;
- long col;
+ bitset_pos_t col;
const ir_edge_t *edge;
ir_node *perm = NULL;
int match_res, cost;
static int set_cmp_conflict_t(const void *x, const void *y, size_t size) {
const conflict_t *xx = x;
const conflict_t *yy = y;
+ (void) size;
+
return ! (xx->n1 == yy->n1 && xx->n2 == yy->n2);
}
}
static int set_cmp_node_stat_t(const void *x, const void *y, size_t size) {
+ (void) size;
return ((node_stat_t *)x)->irn != ((node_stat_t *)y)->irn;
}
ir_node **safe, **unsafe;
int i, o, safe_count, safe_costs, unsafe_count, *unsafe_costs;
bitset_t *curr, *best;
- int max, next, pos, curr_weight, best_weight = 0;
+ bitset_pos_t pos;
+ int max, next, curr_weight, best_weight = 0;
/* assign the nodes into two groups.
* safe: node has no interference, hence it is in every max stable set.
qnode_t *curr = NULL, *tmp;
const arch_env_t *aenv = ou->co->aenv;
const arch_register_class_t *cls = ou->co->cls;
+ bitset_pos_t idx;
bitset_t *pos_regs = bitset_alloca(cls->n_regs);
DBG((dbg, LEVEL_1, "\tOptimizing unit:\n"));
assert(bitset_popcnt(pos_regs) != 0 && "No register is allowed for this node !!?");
/* create new qnode */
- bitset_foreach(pos_regs, i)
- ou_insert_qnode(ou, new_qnode(ou, i));
+ bitset_foreach(pos_regs, idx)
+ ou_insert_qnode(ou, new_qnode(ou, idx));
/* search best */
while (!list_empty(&ou->queue)) {
co2_t *env = ci->cloud->env;
col_cost_pair_t *seq = alloca(env->n_regs * sizeof(seq[0]));
int is_root = ci->mst_parent == ci;
- col_t parent_col = is_root ? -1 : get_col(env, ci->mst_parent->inh.irn);
+ col_t parent_col = is_root ? (col_t) -1 : get_col(env, ci->mst_parent->inh.irn);
int min_badness = INT_MAX;
int best_col_costs = INT_MAX;
int best_col = -1;
|_| |___/
*/
-static const char *get_dot_color_name(int col)
+static const char *get_dot_color_name(size_t col)
{
static const char *names[] = {
"blue",
"palevioletred"
};
- return col < sizeof(names)/sizeof(names[0]) ? names[col] : "white";
+ return col < (sizeof(names)/sizeof(names[0])) ? names[col] : "white";
}
static const char *get_dot_shape_name(co2_t *env, co2_irn_t *ci)
static void ifg_dump_graph_attr(FILE *f, void *self)
{
+ (void) self;
fprintf(f, "overlay=false");
}
static void determine_color_costs(co_mst_env_t *env, co_mst_irn_t *node, col_cost_t *costs) {
affinity_node_t *an = get_affinity_info(env->co, node->irn);
neighb_t *aff_neigh;
- int idx, i;
+ bitset_pos_t idx;
+ int i;
col_cost_init(env, costs, 0.0);
LC_OPT_ENT_BOOL ("net", "solve over the net", &solve_net),
LC_OPT_ENT_BOOL ("log", "show ilp solving log", &solve_log),
LC_OPT_ENT_ENUM_MASK("dump", "dump flags", &dump_var),
- { NULL }
+ LC_OPT_ENT_NULL
};
void be_init_copyilp(void)
} my_env_t;
-int co_solve_ilp1(copy_opt_t *co, double time_limit) {
+int co_solve_ilp1(copy_opt_t *co, double time_limit)
+{
+ (void) co;
+ (void) time_limit;
return 1;
}
/**
* Collect phi node data
*/
-static void stat_phi_node(be_chordal_env_t *chordal_env, ir_node *phi) {
+static void stat_phi_node(be_chordal_env_t *chordal_env, ir_node *phi)
+{
int arity, i;
ir_node *phi_bl;
assert(is_Phi(phi));
+ (void) chordal_env;
/* count all phi phis */
curr_vals[I_PHI_CNT]++;
int linelength; /**< The length of the current line. */
} be_emit_env_t;
+#define NULL_EMITTER { NULL, {}, 0 }
+
/**
* Emit a character to the (assembler) output.
*
}
};
- assert(be_gas_flavour >= 0 && be_gas_flavour < GAS_FLAVOUR_MAX);
- assert(section >= 0 && section < GAS_SECTION_MAX);
+ assert((int) be_gas_flavour >= 0 && be_gas_flavour < GAS_FLAVOUR_MAX);
+ assert((int) section >= 0 && section < GAS_SECTION_MAX);
return text[be_gas_flavour][section];
}
ir_node *live_irn;
bitset_pos_t elm;
- bitset_foreach_irn(ifg->env->irg, live, elm, live_irn)
- {
+ bitset_foreach_irn(ifg->env->irg, live, elm, live_irn) {
ptr_head_t *head = phase_get_or_set_irn_data(&ifg->ph, live_irn);
ptr_head_t *element = ptr_get_new_head(ifg);
static ir_node *ifg_pointer_neighbours_next(const void *self, void *iter)
{
+ (void) self;
return get_next_neighbour(iter);
}
static void ifg_pointer_neighbours_break(const void *self, void *iter)
{
ptr_iter_t *it = iter;
+ (void) self;
bitset_free(it->visited_neighbours);
static ir_node *ifg_pointer_nodes_next(const void *self, void *iter)
{
+ (void) self;
return get_next_irn(iter);
}
static void ifg_pointer_nodes_break(const void *self, void *iter)
{
+ (void) self;
+ (void) iter;
return;
}
LC_OPT_ENT_STR ("jvm", "absolute path to jvm dll", jvm_lib, sizeof(jvm_lib)),
LC_OPT_ENT_STR ("jar", "jar file of the coalescer", jar_file, sizeof(jar_file)),
LC_OPT_ENT_STR ("cls", "name of the class providing the factory", cls_name, sizeof(cls_name)),
- { NULL }
+ LC_OPT_ENT_NULL
};
void be_init_javacoal(void)
static char *locate_jvm_lib(char *path, size_t n)
{
+ (void) path;
+ (void) n;
return NULL;
}
#endif /* _WIN32 */
void be_java_coal_set_debug(be_java_coal_t *c, int n, const char *dbg)
{
+ (void) c;
+ (void) n;
+ (void) dbg;
#if 0
JNIEnv *jni = c->env->jni;
jmethodID mid = c->mth_ids[mth_set_debug];
static const lc_opt_table_entry_t list_sched_option_table[] = {
LC_OPT_ENT_ENUM_PTR("prep", "schedule preparation", &sched_prep_var),
LC_OPT_ENT_ENUM_PTR("select", "node selector", &sched_select_var),
- { NULL }
+ LC_OPT_ENT_NULL
};
/**
{
const arch_env_t *arch_env = birg->main_env->arch_env;
ir_graph *irg = birg->irg;
+ (void) be_opts;
int num_nodes;
sched_env_t env;
}
/* List schedule a block. */
-void list_sched_single_block(const be_irg_t *birg, ir_node *block, be_options_t *be_opts)
+void list_sched_single_block(const be_irg_t *birg, ir_node *block,
+ be_options_t *be_opts)
{
const arch_env_t *arch_env = birg->main_env->arch_env;
ir_graph *irg = birg->irg;
+ (void) be_opts;
int num_nodes;
sched_env_t env;
{
struct _be_lv_info_t *info = phase_alloc(phase, LV_STD_SIZE * sizeof(info[0]));
(void) irn;
+ (void) old;
memset(info, 0, LV_STD_SIZE * sizeof(info[0]));
info[0].u.head.n_size = LV_STD_SIZE - 1;
{
#ifndef USE_LIVE_CHK
be_liveness_assure_sets(be_lv_t *lv);
+#else
+ (void) lv;
#endif
}
be_irg_t *birg;
};
-static int cmp_loop_info(const void *a, const void *b, size_t sz) {
+static int cmp_loop_info(const void *a, const void *b, size_t size) {
const be_loop_info_t *i1 = a;
const be_loop_info_t *i2 = b;
+ (void) size;
return ! (i1->loop == i2->loop && i1->cls == i2->cls);
}
va_list args;
const char *opt;
const be_module_list_entry_t *module;
+ (void) type;
+ (void) name;
va_start(args, length);
opt = va_arg(args, const char*);
{
module_opt_data_t *moddata = data;
const be_module_list_entry_t *module;
+ (void) name;
+ (void) type;
+ (void) length;
for (module = *(moddata->list_head); module != NULL; module = module->next) {
if (module->data == *(moddata->var)) {
module_opt_data_t *moddata = data;
char *p = buf;
const be_module_list_entry_t *module;
+ (void) name;
+ (void) type;
+ (void) len;
for (module = *(moddata->list_head); module != NULL; module = module->next) {
size_t len = strlen(module->name);
}
int sched_skip_phi_predicator(const ir_node *irn, void *data) {
+ (void) data;
return is_Phi(irn);
}
return irn;
}
-static void *random_init_graph(const list_sched_selector_t *vtab, const arch_env_t *arch_env, ir_graph *irg)
+static void *random_init_graph(const list_sched_selector_t *vtab,
+ const arch_env_t *arch_env, ir_graph *irg)
{
+ (void) vtab;
+ (void) irg;
/* Using time(NULL) as a seed here gives really random results,
but is NOT deterministic which makes debugging impossible.
Moreover no-one want non-deterministic compilers ... */
return (void *)arch_env;
}
-static void *random_init_block(void *graph_env, ir_node *bl)
+static void *random_init_block(void *graph_env, ir_node *block)
{
+ (void) block;
return graph_env;
}
* Just assure that branches are executed last, otherwise select
* the first node ready.
*/
-static ir_node *trivial_select(void *block_env, ir_nodeset_t *ready_set, ir_nodeset_t *live_set)
+static ir_node *trivial_select(void *block_env, ir_nodeset_t *ready_set,
+ ir_nodeset_t *live_set)
{
const arch_env_t *arch_env = block_env;
ir_node *irn = NULL;
ir_nodeset_iterator_t iter;
+ (void) live_set;
/* assure that branches and constants are executed last */
foreach_ir_nodeset(ready_set, irn, iter) {
return irn;
}
-static void *trivial_init_graph(const list_sched_selector_t *vtab, const arch_env_t *arch_env, ir_graph *irg)
+static void *trivial_init_graph(const list_sched_selector_t *vtab,
+ const arch_env_t *arch_env, ir_graph *irg)
{
+ (void) vtab;
+ (void) irg;
return (void *)arch_env;
}
-static void *trivial_init_block(void *graph_env, ir_node *bl)
+static void *trivial_init_block(void *graph_env, ir_node *block)
{
+ (void) block;
return graph_env;
}
irg_walk_graph(irg, collect_phis, NULL, NULL);
}
-static void count_num_reachable_nodes(ir_node *irn, void *env) {
+static void count_num_reachable_nodes(ir_node *irn, void *env)
+{
int *num = env;
(*num)++;
+ (void) irn;
}
unsigned get_num_reachable_nodes(ir_graph *irg) {
static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
int pos = 0;
+ (void) self;
if (get_irn_mode(irn) == mode_X) {
return;
static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
int pos = 0;
const arch_register_t *reg = NULL;
+ (void) self;
if (is_Proj(irn)) {
static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
arch_irn_class_t classification = arch_irn_class_normal;
+ (void) self;
irn = skip_Proj_const(irn);
static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
arch_irn_flags_t flags = arch_irn_flags_none;
+ (void) self;
if (is_Unknown(irn))
return arch_irn_flags_ignore;
} ia32_abi_env_t;
static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
+ (void) self;
return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
}
static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+ (void) self;
set_ia32_frame_ent(irn, ent);
}
}
static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
+ (void) self;
if(is_Proj(irn)) {
long proj = get_Proj_proj(irn);
ir_node *pred = get_Proj_pred(irn);
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
dbg_info *dbg;
+ (void) self;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
ir_node *op = get_irn_n(irn, i);
const ir_mode *mode = get_irn_mode(op);
const ir_mode *spillmode = get_spill_mode(op);
+ (void) self;
if (! is_ia32_irn(irn) || /* must be an ia32 irn */
get_irn_arity(irn) != 5 || /* must be a binary operation */
* Dummy functions for hooks we don't need but which must be filled.
*/
static void ia32_before_sched(void *self) {
+ (void) self;
}
/**
7, /* costs for a spill instruction */
5, /* costs for a reload instruction */
},
- { NULL, }, /* emitter environment */
+ NULL_EMITTER, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
NULL, /* 8bit register names high */
mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
}
- ia32_register_init(isa);
+ ia32_register_init();
ia32_create_opcodes();
ia32_register_copy_attr_func();
* - the SSE vector register set
*/
static int ia32_get_n_reg_class(const void *self) {
+ (void) self;
return N_CLASSES;
}
*/
static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
{
+ (void) self;
assert(i >= 0 && i < N_CLASSES);
return &ia32_reg_classes[i];
}
}
-static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
+static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
+ const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
return &ia32_irn_ops;
}
ia32_get_irn_ops
};
-const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
+const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
+{
+ (void) self;
return &ia32_irn_handler;
}
-int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
+int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
+{
+ (void) block_env;
+
if(!is_ia32_irn(irn)) {
return -1;
}
/**
* Initializes the code generator interface.
*/
-static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
+static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
+{
+ (void) self;
return &ia32_code_gen_if;
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
+static const list_sched_selector_t *ia32_get_list_sched_selector(
+ const void *self, list_sched_selector_t *selector)
+{
+ (void) self;
memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
ia32_sched_selector.exectime = ia32_sched_exectime;
ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
return &ia32_sched_selector;
}
-static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
+static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
+{
+ (void) self;
return NULL;
}
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+static int ia32_get_reg_class_alignment(const void *self,
+ const arch_register_class_t *cls)
+{
ir_mode *mode = arch_register_class_mode(cls);
int bytes = get_mode_size_bytes(mode);
+ (void) self;
if (mode_is_float(mode) && bytes > 8)
return 16;
return bytes;
}
-static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
+static const be_execution_unit_t ***ia32_get_allowed_execution_units(
+ const void *self, const ir_node *irn)
+{
static const be_execution_unit_t *_allowed_units_BRANCH[] = {
&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
NULL
};
const be_execution_unit_t ***ret;
+ (void) self;
if (is_ia32_irn(irn)) {
ret = get_ia32_exec_units(irn);
/**
* Return irp irgs in the desired order.
*/
-static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
+static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
+{
+ (void) self;
+ (void) irg_list;
return NULL;
}
LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
- { NULL }
+ LC_OPT_ENT_NULL
};
const arch_isa_if_t ia32_isa_if = {
* returns the condition code
*/
static
-const char *get_cmp_suffix(int cmp_code)
+const char *get_cmp_suffix(pn_Cmp cmp_code)
{
assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
}
static
-void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
+void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
+{
long pnc = get_ia32_pncode(node);
const arch_register_t *in1, *in2, *out;
}
static
-void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
+void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
+{
CMov_emitter(env, node);
}
static
-void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
+void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
+{
CMov_emitter(env, node);
}
static
-void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
+void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
+{
long pnc = get_ia32_pncode(node);
const char *reg8bit;
const arch_register_t *out;
static
void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
- Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
+ Set_emitter(env, node);
}
static
void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
- Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
+ Set_emitter(env, node);
}
static
/* jump table for switch generation */
typedef struct _jmp_tbl_t {
ir_node *defProj; /**< default target */
- int min_value; /**< smallest switch case */
- int max_value; /**< largest switch case */
- int num_branches; /**< number of jumps */
+ long min_value; /**< smallest switch case */
+ long max_value; /**< largest switch case */
+ long num_branches; /**< number of jumps */
char *label; /**< label of the jump table */
branch_t *branches; /**< jump array */
} jmp_tbl_t;
}
static
-void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
+void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
+{
be_emit_cstring(env, "\tret");
be_emit_finish_line_gas(env, node);
}
static
-void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
+void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
+{
+ (void) env;
+ (void) node;
}
* Sets labels for control flow nodes (jump target)
*/
static
-void ia32_gen_labels(ir_node *block, void *data) {
+void ia32_gen_labels(ir_node *block, void *data)
+{
ir_node *pred;
int n = get_Block_n_cfgpreds(block);
+ (void) data;
for (n--; n >= 0; n--) {
pred = get_Block_cfgpred(block, n);
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res, *add;
+ (void) ctx;
/* l_res = a_l + b_l */
/* h_res = a_h + b_h + carry */
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res, *res;
+ (void) ctx;
/* l_res = a_l - b_l */
/* h_res = a_h - b_h - carry */
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res;
+ (void) ctx;
/* h_res = SHLD a_h, a_l, cnt */
h_res = new_rd_ia32_l_ShlD(dbg, irg, block, a_h, a_l, cnt, l_res_mode);
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res;
+ (void) ctx;
/* l_res = SHRD a_l, a_h, cnt */
l_res = new_rd_ia32_l_ShrD(dbg, irg, block, a_l, a_h, cnt, l_res_mode);
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res;
+ (void) ctx;
/* l_res = SHRD a_l, a_h, cnt */
l_res = new_rd_ia32_l_ShrD(dbg, irg, block, a_l, a_h, cnt, l_res_mode);
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res, *mul, *pEDX, *add;
+ (void) ctx;
/*
EDX:EAX = a_l * b_l
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res, *cnst, *res;
+ (void) ctx;
/* too bad: we need 0 in a register here */
cnst = new_Const_long(h_res_mode, 0);
ir_mode *l_res_mode = get_type_mode(get_method_res_type(method, 0));
ir_mode *h_res_mode = get_type_mode(get_method_res_type(method, 1));
ir_node *l_res, *h_res, *sign, *sub_l, *sub_h, *res;
+ (void) ctx;
/*
Code inspired by gcc output :) (although gcc doubles the
int ia32_cmp_irn_reg_assoc(const void *a, const void *b, size_t len) {
const struct ia32_irn_reg_assoc *x = a;
const struct ia32_irn_reg_assoc *y = b;
+ (void) len;
return x->irn != y->irn;
}
/* dump pn code */
if(is_ia32_SwitchJmp(n)) {
- fprintf(F, "pn_code = %d\n", get_ia32_pncode(n));
+ fprintf(F, "pn_code = %ld\n", get_ia32_pncode(n));
} else {
if(get_ia32_pncode(n) & ia32_pn_Cmp_Unsigned) {
- int pnc = get_ia32_pncode(n);
- fprintf(F, "pn_code = %d (%s, unsigned)\n",
+ long pnc = get_ia32_pncode(n);
+ fprintf(F, "pn_code = %ld (%s, unsigned)\n",
pnc, get_pnc_string(pnc & ~ia32_pn_Cmp_Unsigned));
} else {
- fprintf(F, "pn_code = %d (%s)\n", get_ia32_pncode(n),
+ fprintf(F, "pn_code = %ld (%s)\n", get_ia32_pncode(n),
get_pnc_string(get_ia32_pncode(n)));
}
}
/**
* Returns the projnum code.
*/
-pn_Cmp get_ia32_pncode(const ir_node *node) {
+long get_ia32_pncode(const ir_node *node)
+{
const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->pn_code;
}
/**
* Sets the projnum code
*/
-void set_ia32_pncode(ir_node *node, pn_Cmp code) {
+void set_ia32_pncode(ir_node *node, long code)
+{
ia32_attr_t *attr = get_ia32_attr(node);
attr->pn_code = code;
}
/**
* Returns the projnum code.
*/
-pn_Cmp get_ia32_pncode(const ir_node *node);
+long get_ia32_pncode(const ir_node *node);
/**
* Sets the projnum code
*/
-void set_ia32_pncode(ir_node *node, pn_Cmp code);
+void set_ia32_pncode(ir_node *node, long code);
/**
* Gets the instruction latency.
char immediate_type;
};
-void parse_asm_constraint(ir_node *node, int pos, constraint_t *constraint,
- const char *c)
+void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
{
int immediate_possible = 0;
char immediate_type = 0;
void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
const char *c)
{
+ (void) node;
+ (void) pos;
+ (void) constraint;
+ (void) c;
panic("Clobbers not supported yet");
}
const ir_asm_constraint *constraint;
constraint = & get_ASM_output_constraints(node) [i];
c = get_id_str(constraint->constraint);
- parse_asm_constraint(node, i, &parsed_constraint, c);
+ parse_asm_constraint(i, &parsed_constraint, c);
} else {
ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
c = get_id_str(glob_id);
constraint = & get_ASM_input_constraints(node) [i];
constr_id = constraint->constraint;
c = get_id_str(constr_id);
- parse_asm_constraint(node, i, &parsed_constraint, c);
+ parse_asm_constraint(i, &parsed_constraint, c);
in_reqs[i] = parsed_constraint.req;
if(parsed_constraint.immediate_possible) {
* @param irn The irn
* @param First proj with mode == mode or NULL if none found
*/
-ir_node *ia32_get_proj_for_mode(const ir_node *irn, ir_mode *mode) {
+ir_node *ia32_get_proj_for_mode(const ir_node *irn, ir_mode *mode)
+{
const ir_edge_t *edge;
ir_node *src;
assert(is_Proj(src) && "Proj expected");
- if (get_irn_mode(src) == mode_M)
+ if (get_irn_mode(src) == mode)
return src;
}
} x87_state;
/** An empty state, used for blocks without fp instructions. */
-static x87_state _empty = { { {0, NULL}, }, 0, 0 };
+static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
static x87_state *empty = (x87_state *)&_empty;
enum {
*
* @return state
*/
-static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *state, ir_node *dst_block, const x87_state *dst_state) {
+static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
+ x87_state *state, ir_node *dst_block,
+ const x87_state *dst_state)
+{
int i, n_cycles, k, ri;
unsigned cycles[4], all_mask;
char cycle_idx[4][8];
ir_node *fxch, *before, *after;
+ (void) sim;
+ (void) dst_block;
assert(state->depth == dst_state->depth);
* @param state the x87 state
* @param n the node after the fxch
* @param pos exchange st(pos) with st(0)
- * @param op_idx if >= 0, replace input op_idx of n with the fxch result
*
* @return the fxch
*/
-static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_idx) {
+static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
+{
ir_node *fxch;
ia32_x87_attr_t *attr;
ir_graph *irg = get_irn_irg(n);
} else {
/* Second live, first operand is dead here, bring it to tos. */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
if (op2_idx == 0)
op2_idx = op1_idx;
op1_idx = 0;
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* First operand is live: bring second to tos. */
if (op2_idx != 0) {
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
if (op1_idx == 0)
op1_idx = op2_idx;
op2_idx = 0;
out_idx = op2_idx;
} else {
/* Bring the second on top. */
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
if (op1_idx == op2_idx) {
/* Both are identically and on tos now, no pop needed. */
op1_idx = 0;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
else {
/* operand is dead, bring it to tos */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, UNOP_IDX);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
}
} else {
/* we can only store the tos to memory */
if (op2_idx != 0)
- x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
+ x87_create_fxch(state, n, op2_idx);
/* mode != mode_E -> use normal fst */
x87_patch_insn(n, op);
} else {
/* we can only store the tos to memory */
if (op2_idx != 0)
- x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
+ x87_create_fxch(state, n, op2_idx);
x87_pop(state);
x87_patch_insn(n, op_p);
return insn;
} /* sim_store */
-/**
- * Simulate a virtual Phi.
- * Just for cosmetic reasons change the mode of Phi nodes to mode_E.
- *
- * @param state the x87 state
- * @param n the node that should be simulated (and patched)
- * @param arch_env the architecture environment
- *
- * @return NO_NODE_ADDED
- */
-static int sim_Phi(x87_state *state, ir_node *n, const arch_env_t *arch_env) {
- ir_mode *mode = get_irn_mode(n);
-
- if (mode_is_float(mode))
- set_irn_mode(n, mode_E);
-
- return NO_NODE_ADDED;
-} /* sim_Phi */
-
#define _GEN_BINOP(op, rev) \
static int sim_##op(x87_state *state, ir_node *n) { \
exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
dst = op_ia32_fcomrJmp;
} else {
/* bring the first one to tos */
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
if (op2_idx == 0)
op2_idx = op1_idx;
op1_idx = 0;
This means further, op1_idx != op2_idx. */
assert(op1_idx != op2_idx);
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
if (op2_idx == 0)
op2_idx = op1_idx;
op1_idx = 0;
This means further, op1_idx != op2_idx. */
assert(op1_idx != op2_idx);
if (op2_idx != 0) {
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
if (op1_idx == 0)
op1_idx = op2_idx;
op2_idx = 0;
if (op1_idx == op2_idx) {
/* identically, one pop needed */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
op2_idx = 0;
}
/* good, second operand is already in the right place, move the first */
if (op1_idx != 0) {
/* bring the first on top */
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
assert(op2_idx != 0);
op1_idx = 0;
}
/* good, first operand is already in the right place, move the second */
if (op2_idx != 0) {
/* bring the first on top */
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
assert(op1_idx != 0);
op2_idx = 0;
}
/* if one is already the TOS, we need two fxch */
if (op1_idx == 0) {
/* first one is TOS, move to st(1) */
- x87_create_fxch(state, n, 1, BINOP_IDX_1);
+ x87_create_fxch(state, n, 1);
assert(op2_idx != 1);
op1_idx = 1;
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
op2_idx = 0;
/* res = op X tos, pop, pop */
dst = op_ia32_fcomrppJmp;
pop_cnt = 2;
} else if (op2_idx == 0) {
/* second one is TOS, move to st(1) */
- x87_create_fxch(state, n, 1, BINOP_IDX_2);
+ x87_create_fxch(state, n, 1);
assert(op1_idx != 1);
op2_idx = 1;
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
/* res = tos X op, pop, pop */
dst = op_ia32_fcomppJmp;
pop_cnt = 2;
} else {
/* none of them is either TOS or st(1), 3 fxch needed */
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
assert(op1_idx != 0);
- x87_create_fxch(state, n, 1, BINOP_IDX_2);
+ x87_create_fxch(state, n, 1);
op2_idx = 1;
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
/* res = tos X op, pop, pop */
dst = op_ia32_fcomppJmp;
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* first operand is live: bring it to TOS */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
dst = op_ia32_fcomJmp;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
dst = op_ia32_fcompJmp;
} else {
/* move op1 to tos, store and pop it */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, 0);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
x87_patch_insn(n, op_ia32_Pop);
*
* @return NO_NODE_ADDED
*/
-static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) {
+static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
+{
ir_type *call_tp = be_Call_get_type(n);
ir_type *res_type;
ir_mode *mode;
ir_node *resproj;
const arch_register_t *reg;
+ (void) arch_env;
/* at the begin of a call the x87 state should be empty */
assert(state->depth == 0 && "stack not empty before call");
if (keep)
x87_set_st(state, -1, keep, i);
- x87_create_fxch(state, first_insn, i, -1);
+ x87_create_fxch(state, first_insn, i);
}
if ((kill_mask & 3) == 3) {
ASSOC_BE(Return);
ASSOC_BE(Perm);
ASSOC_BE(Keep);
- ASSOC(Phi);
#undef ASSOC_BE
#undef ASSOC_IA32
#undef ASSOC
*/
static const
arch_register_req_t *mips_get_irn_reg_req(const void *self,
- const ir_node *node, int pos) {
+ const ir_node *node, int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(node);
+ (void) self;
if (is_Block(node) || mode == mode_X || mode == mode_M) {
return arch_no_register_req;
return arch_no_register_req;
}
-static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void mips_set_irn_reg(const void *self, ir_node *irn,
+ const arch_register_t *reg)
+{
int pos = 0;
+ (void) self;
if (is_Proj(irn)) {
}
}
-static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *mips_get_irn_reg(const void *self,
+ const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
+ (void) self;
if (is_Proj(irn)) {
return reg;
}
-static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
+static arch_irn_class_t mips_classify(const void *self, const ir_node *irn)
+{
+ (void) self;
irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return 0;
}
-static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
+static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn)
+{
+ (void) self;
irn = skip_Proj_const(irn);
if (is_mips_irn(irn)) {
}
static
-ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) {
+ir_entity *mips_get_frame_entity(const void *self, const ir_node *node)
+{
const mips_attr_t *attr;
+ (void) self;
if(!is_mips_irn(node))
return NULL;
}
static
-void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
+{
mips_attr_t *attr = get_mips_attr(irn);
+ (void) self;
attr->stack_entity = ent;
}
*/
static void mips_set_frame_offset(const void *self, ir_node *irn, int offset)
{
+ (void) self;
+ (void) irn;
+ (void) offset;
panic("TODO");
#if 0
mips_attr_t *attr = get_mips_attr(irn);
#endif
}
-static int mips_get_sp_bias(const void *self, const ir_node *irn) {
+static int mips_get_sp_bias(const void *self, const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
return 0;
}
/**
* These are some hooks which must be filled but are probably not needed.
*/
-static void mips_before_sched(void *self) {
- /* Some stuff you need to do after scheduling but before register allocation */
+static void mips_before_sched(void *self)
+{
+ (void) self;
}
-static void mips_before_ra(void *self) {
- /* Some stuff you need to do immediately after register allocation */
+static void mips_before_ra(void *self)
+{
+ (void) self;
}
-static void mips_after_ra(void* self) {
+static void mips_after_ra(void* self)
+{
mips_code_gen_t *cg = self;
be_coalesce_spillslots(cg->birg);
irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
* Emits the code, closes the output file and frees
* the code generator interface.
*/
-static void mips_emit_and_done(void *self) {
+static void mips_emit_and_done(void *self)
+{
mips_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
+ (void) self;
mips_gen_routine(cg, irg);
/**
* Initializes the code generator.
*/
-static void *mips_cg_init(be_irg_t *birg) {
+static void *mips_cg_init(be_irg_t *birg)
+{
const arch_env_t *arch_env = be_get_birg_arch_env(birg);
mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
mips_code_gen_t *cg = xmalloc(sizeof(*cg));
7, /* spill costs */
5, /* reload costs */
},
- { NULL, }, /* emitter environment */
+ NULL_EMITTER, /* emitter environment */
};
/**
be_emit_init_env(&isa->emit, file_handle);
- mips_register_init(isa);
+ mips_register_init();
mips_create_opcodes();
// mips_init_opcode_transforms();
/**
* Closes the output file and frees the ISA structure.
*/
-static void mips_done(void *self) {
+static void mips_done(void *self)
+{
mips_isa_t *isa = self;
be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
free(isa);
}
-static int mips_get_n_reg_class(const void *self) {
+static int mips_get_n_reg_class(const void *self)
+{
+ (void) self;
return N_CLASSES;
}
-static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
+static const arch_register_class_t *mips_get_reg_class(const void *self, int i)
+{
+ (void) self;
assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
return &mips_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
+ const ir_mode *mode)
+{
+ (void) self;
ASSERT_NO_FLOAT(mode);
return &mips_reg_classes[CLASS_mips_gp];
}
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+static void mips_get_call_abi(const void *self, ir_type *method_type,
+ be_abi_call_t *abi)
+{
ir_type *tp;
ir_mode *mode;
int n = get_method_n_params(method_type);
ir_mode **modes;
const arch_register_t *reg;
be_abi_call_flags_t call_flags;
+ (void) self;
memset(&call_flags, 0, sizeof(call_flags));
call_flags.bits.left_to_right = 0;
}
}
-static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
+static const void *mips_get_irn_ops(const arch_irn_handler_t *self,
+ const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
return &mips_irn_ops;
}
mips_get_irn_ops
};
-const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
+const arch_irn_handler_t *mips_get_irn_handler(const void *self)
+{
+ (void) self;
return &mips_irn_handler;
}
/**
* Initializes the code generator interface.
*/
-static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
+static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
+{
+ (void) self;
return &mips_code_gen_if;
}
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+static int mips_get_reg_class_alignment(const void *self,
+ const arch_register_class_t *cls)
+{
ir_mode *mode = arch_register_class_mode(cls);
+ (void) self;
return get_mode_size_bytes(mode);
}
-static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
+static const be_execution_unit_t ***mips_get_allowed_execution_units(
+ const void *self, const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
/* TODO */
assert(0);
return NULL;
}
-static const be_machine_t *mips_get_machine(const void *self) {
+static const be_machine_t *mips_get_machine(const void *self)
+{
+ (void) self;
/* TODO */
assert(0);
return NULL;
/**
* Return irp irgs in the desired order.
*/
-static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) {
+static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
+{
+ (void) self;
+ (void) irg_list;
return NULL;
}
{
ir_node *pred;
int n = get_Block_n_cfgpreds(block);
+ (void) env;
for (n--; n >= 0; n--) {
pred = get_Block_cfgpred(block, n);
const arch_register_t *reg;
};
-int mips_cmp_irn_reg_assoc(const void *a, const void *b, size_t len) {
+int mips_cmp_irn_reg_assoc(const void *a, const void *b, size_t size) {
const struct mips_irn_reg_assoc *x = a;
const struct mips_irn_reg_assoc *y = b;
+ (void) size;
return x->irn != y->irn;
}
/**
* Initializes the nodes attributes.
*/
-void init_mips_attributes(ir_node *node, arch_irn_flags_t flags, const arch_register_req_t **in_reqs,
- const arch_register_req_t **out_reqs,
- const be_execution_unit_t ***execution_units,
- int n_res, unsigned latency)
+void init_mips_attributes(ir_node *node, arch_irn_flags_t flags,
+ const arch_register_req_t **in_reqs,
+ const arch_register_req_t **out_reqs,
+ const be_execution_unit_t ***execution_units,
+ int n_res, unsigned latency)
{
ir_graph *irg = get_irn_irg(node);
struct obstack *obst = get_irg_obstack(irg);
mips_attr_t *attr = get_mips_attr(node);
+ (void) execution_units;
+ (void) latency;
attr->flags = flags;
attr->out_req = out_reqs;
static
int mips_to_appear_in_schedule(void *block_env, const ir_node *node)
{
+ (void) block_env;
+
if(!is_mips_irn(node))
return -1;
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-const list_sched_selector_t *mips_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
+const list_sched_selector_t *mips_get_list_sched_selector(const void *self,
+ list_sched_selector_t *selector)
{
+ (void) self;
#if 0
memset(&mips_sched_selector, 0, sizeof(mips_sched_selector));
mips_sched_selector.init_graph = mips_scheduler_init_graph;
return &mips_selector;
}
-const ilp_sched_selector_t *mips_get_ilp_sched_selector(const void *self) {
+const ilp_sched_selector_t *mips_get_ilp_sched_selector(const void *self)
+{
+ (void) self;
return NULL;
}
return gen_node_for_Const(env, dbg, irg, block, pred);
}
-static ir_node* gen_node_for_SymConst(mips_transform_env_t *env, ir_node* pred, int n) {
+static ir_node* gen_node_for_SymConst(mips_transform_env_t *env, ir_node* pred)
+{
mips_attr_t *attr;
ir_node *node = env->irn;
dbg_info *dbg = get_irn_dbg_info(pred);
ir_node* constnode = exchange_node_for_Const(&tenv, pred, i);
set_irn_n(node, i, constnode);
} else if (get_irn_op(pred) == op_SymConst) {
- ir_node* constnode = gen_node_for_SymConst(&tenv, pred, i);
+ ir_node* constnode = gen_node_for_SymConst(&tenv, pred);
set_irn_n(node, i, constnode);
}
}
be_emit_init_env(&isa->emit, file_handle);
- ppc32_register_init(isa);
+ ppc32_register_init();
ppc32_create_opcodes();
inited = 1;
if($n{"emit"} eq "") {
push(@obst_func, $line." {\n");
+ push(@obst_func, "\t(void) env;\n");
+ push(@obst_func, "\t(void) node;\n");
push(@obst_func, "}\n\n");
next;
}
print OUT "extern arch_register_class_t $arch\_reg_classes[N_CLASSES];\n\n";
-print OUT "void ".$arch."_register_init(void *isa_ptr);\n\n";
+print OUT "void ".$arch."_register_init(void);\n\n";
print OUT @obst_header_all, "\n";
print OUT @obst_regtypes_def, "\n";
-print OUT "void ${arch}_register_init(void *isa_ptr) {\n";
+print OUT "void ${arch}_register_init(void) {\n";
print OUT @obst_reginit;
print OUT "}\n\n";
#include <stdio.h>
int __signbit (double __x) {
- union { double __d; int __i[3]; } __u = { __d: __x };
+ union {
+ double __d;
+ int __i[3];
+ } __u = { __d: __x };
+
return __u.__i[1] < 0;
}
projects / libfirm / commitdiff