return 1;
}
else if (is_ia32_DivMod(pred)) {
- if (nr == pn_DivMod_res_div || nr == pn_Div_res)
+ if (nr == pn_DivMod_res_div)
return 0;
- if (nr == pn_DivMod_res_mod || nr == pn_Mod_res)
+ if (nr == pn_DivMod_res_mod)
return 1;
+
+ switch(get_ia32_flavour(pred)) {
+ if (nr == pn_DivMod_res_div)
+ return 0;
+ if (nr == pn_DivMod_res_mod)
+ return 1;
+ assert(0 && "unsupported DivMod");
+ }
}
else if (is_ia32_fDiv(pred)) {
if (nr == pn_Quot_res)
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
+static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
+ const ir_edge_t *edge;
+ ir_node *proj;
+ assert(get_irn_mode(irn) == mode_T && "need mode_T");
+ foreach_out_edge(irn, edge) {
+ proj = get_edge_src_irn(edge);
+
+ if (get_Proj_proj(proj) == pn)
+ return proj;
+ }
+
+ return NULL;
+}
/**
* Generates an ia32 DivMod with additional infrastructure for the
switch (dm_flav) {
case flavour_Div:
- mem = get_Div_mem(irn);
+ mem = get_Div_mem(irn);
+ mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
break;
case flavour_Mod:
- mem = get_Mod_mem(irn);
+ mem = get_Mod_mem(irn);
+ mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
break;
case flavour_DivMod:
- mem = get_DivMod_mem(irn);
+ mem = get_DivMod_mem(irn);
+ mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
break;
default:
assert(0);