ins => [ "left", "right", "eflags" ],
},
-Add64Bit => {
- irn_flags => "R",
- arity => 4,
- reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S1, %D1
-. addl %SI2, %D0
-. adcl %SI3, %D1
-',
- outs => [ "low_res", "high_res" ],
- units => [ "GP" ],
- modified_flags => $status_flags
-},
-
Mul => {
# we should not rematrialize this node. It produces 2 results and has
# very strict constrains
return muls;
}
-static ir_node *gen_ia32_Add64Bit(ir_node *node)
-{
- ir_node *a_l = be_transform_node(get_irn_n(node, 0));
- ir_node *a_h = be_transform_node(get_irn_n(node, 1));
- ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
- ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
- ir_node *block = be_transform_node(get_nodes_block(node));
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_graph *irg = current_ir_graph;
- ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
-}
-
static ir_node *gen_ia32_Sub64Bit(ir_node *node)
{
ir_node *a_l = be_transform_node(get_irn_n(node, 0));
GEN(IJmp);
/* transform ops from intrinsic lowering */
- GEN(ia32_Add64Bit);
GEN(ia32_Sub64Bit);
GEN(ia32_l_Add);
GEN(ia32_l_Adc);