}
/* dump OUT requirements */
- if (attr->n_res > 0) {
+ if (ARR_LEN(attr->slots) > 0) {
reqs = get_TEMPLATE_out_req_all(n);
dump_reg_req(F, n, reqs, 1);
}
/* dump assigned registers */
slots = get_TEMPLATE_slots(n);
- if (slots && attr->n_res > 0) {
- for (i = 0; i < attr->n_res; i++) {
+ if (slots && ARR_LEN(attr->slots) > 0) {
+ for (i = 0; i < ARR_LEN(attr->slots); i++) {
if (slots[i]) {
fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
}
const TEMPLATE_attr_t *attr = get_TEMPLATE_attr_const(node);
assert(is_TEMPLATE_irn(node) && "Not an TEMPLATE node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
const TEMPLATE_attr_t *attr = get_TEMPLATE_attr_const(node);
assert(is_TEMPLATE_irn(node) && "Not an TEMPLATE node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
const TEMPLATE_attr_t *attr = get_TEMPLATE_attr_const(node);
assert(is_TEMPLATE_irn(node) && "Not an TEMPLATE node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
}
-/**
- * Sets the number of results.
- */
-void set_TEMPLATE_n_res(ir_node *node, int n_res) {
- TEMPLATE_attr_t *attr = get_TEMPLATE_attr(node);
- attr->n_res = n_res;
-}
-
/**
* Returns the number of results.
*/
int get_TEMPLATE_n_res(const ir_node *node) {
const TEMPLATE_attr_t *attr = get_TEMPLATE_attr_const(node);
- return attr->n_res;
+ return ARR_LEN(attr->slots);
}
/**
const be_execution_unit_t ***execution_units,
int n_res, unsigned latency)
{
+ ir_graph *irg = get_irn_irg(node);
+ struct obstack *obst = get_irg_obstack(irg);
TEMPLATE_attr_t *attr = get_TEMPLATE_attr(node);
- attr->flags = flags;
+ attr->flags = flags;
attr->out_req = out_reqs;
- attr->in_req = in_reqs;
- attr->n_res = n_res;
+ attr->in_req = in_reqs;
- memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
+ attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
+ memset(attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
/***************************************************************************************
*/
const arch_register_t *get_TEMPLATE_out_reg(const ir_node *node, int pos);
-/**
- * Sets the number of results.
- */
-void set_TEMPLATE_n_res(ir_node *node, int n_res);
-
/**
* Returns the number of results.
*/
struct TEMPLATE_attr_t
{
arch_irn_flags_t flags; /**< indicating if spillable, rematerializeable ... etc. */
- int n_res; /**< number of results for this node */
const arch_register_req_t **in_req; /**< register requirements for arguments */
const arch_register_req_t **out_req; /**< register requirements for results */
- /* must be last, dynamically allocated */
- const arch_register_t *slots[1]; /**< register slots for assigned registers */
+ const arch_register_t **slots; /**< register slots for assigned registers */
};
#endif
}
int TEMPLATE_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_TEMPLATE_irn(irn);
+ if(!is_TEMPLATE_irn(irn))
+ return -1;
+
+ return 1;
}
/**
/**
* Returns the libFirm configuration parameter for this backend.
*/
-static const backend_params *TEMPLATE_get_libfirm_params(void) {
+static const backend_params *TEMPLATE_get_backend_params(void) {
static arch_dep_params_t ad = {
1, /* allow subs */
0, /* Muls are fast enough on Firm */
return NULL;
}
+static ir_graph **TEMPLATE_get_backend_irg_list(const void *self, ir_graph ***irgs) {
+ return NULL;
+}
+
const arch_isa_if_t TEMPLATE_isa_if = {
TEMPLATE_init,
TEMPLATE_get_list_sched_selector,
TEMPLATE_get_ilp_sched_selector,
TEMPLATE_get_reg_class_alignment,
- TEMPLATE_get_libfirm_params,
+ TEMPLATE_get_backend_params,
TEMPLATE_get_allowed_execution_units,
- TEMPLATE_get_machine
+ TEMPLATE_get_machine,
+ TEMPLATE_get_backend_irg_list
};
void be_init_arch_TEMPLATE(void)
}
/* dump OUT requirements */
- if (attr->n_res > 0) {
+ if (ARR_LEN(attr->slots) > 0) {
reqs = get_arm_out_req_all(n);
dump_reg_req(F, n, reqs, 1);
}
/* dump assigned registers */
slots = get_arm_slots(n);
- if (slots && attr->n_res > 0) {
- for (i = 0; i < attr->n_res; i++) {
+ if (slots && ARR_LEN(attr->slots) > 0) {
+ for (i = 0; i < ARR_LEN(attr->slots); i++) {
if (slots[i]) {
fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
}
arm_attr_t *attr = get_arm_attr(node);
assert(is_arm_irn(node) && "Not an arm node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
arm_attr_t *attr = get_arm_attr(node);
assert(is_arm_irn(node) && "Not an arm node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
arm_attr_t *attr = get_arm_attr(node);
assert(is_arm_irn(node) && "Not an arm node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
}
-/**
- * Sets the number of results.
- */
-void set_arm_n_res(ir_node *node, int n_res) {
- arm_attr_t *attr = get_arm_attr(node);
- attr->n_res = n_res;
-}
-
/**
* Returns the number of results.
*/
int get_arm_n_res(const ir_node *node) {
arm_attr_t *attr = get_arm_attr(node);
- return attr->n_res;
+ return ARR_LEN(attr->slots);
}
/**
* Returns the tarvalue
void init_arm_attributes(ir_node *node, int flags, const arch_register_req_t ** in_reqs,
const arch_register_req_t ** out_reqs, const be_execution_unit_t ***execution_units,
int n_res, unsigned latency) {
- arm_attr_t *attr = get_arm_attr(node);
+ ir_graph *irg = get_irn_irg(node);
+ struct obstack *obst = get_irg_obstack(irg);
+ arm_attr_t *attr = get_arm_attr(node);
+
attr->in_req = in_reqs;
attr->out_req = out_reqs;
- attr->n_res = n_res;
attr->flags = flags;
attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE;
attr->value = NULL;
attr->n_projs = 0;
attr->default_proj_num = 0;
- memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
+ attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
+ memset(attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
static int arm_comp_condJmp(arm_attr_t *attr_a, arm_attr_t *attr_b) {
*/
const arch_register_t *get_arm_out_reg(const ir_node *node, int pos);
-/**
- * Sets the number of results.
- */
-void set_arm_n_res(ir_node *node, int n_res);
-
/**
* Returns the number of results.
*/
typedef struct _arm_attr_t {
arch_irn_flags_t flags; /**< indicating if spillable, rematerializeable ... etc. */
- int n_res; /**< number of results for this node */
const arch_register_req_t **in_req; /**< register requirements for arguments */
const arch_register_req_t **out_req; /**< register requirements for results */
int n_projs;
long default_proj_num;
- /* must be last, dynamically allocated */
- const arch_register_t *slots[1]; /**< register slots for assigned registers */
+ const arch_register_t **slots; /**< register slots for assigned registers */
} arm_attr_t;
/**
void be_init_arch_mips(void);
void be_init_arch_arm(void);
void be_init_arch_sta(void);
+void be_init_arch_TEMPLATE(void);
void be_init_ilpsched(void);
void be_init_copyilp(void);
void be_init_javacoal(void);
be_init_arch_ppc32();
be_init_arch_mips();
be_init_arch_arm();
+ be_init_arch_TEMPLATE();
#ifdef WITH_ILP
be_init_ilpsched();
int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
if(!is_ia32_irn(irn)) {
- if (is_ASM(irn))
- return 1;
return -1;
}
void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
{
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
assert(pos < 3);
be_emit_char(env, '%');
// should not happen...
assert(0);
} else {
- ia32_attr_t *attr = get_ia32_attr(node);
- const arch_register_t *in1 = attr->x87[0];
- const arch_register_t *in2 = attr->x87[1];
- const arch_register_t *out = attr->x87[2];
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ const arch_register_t *in1 = attr->x87[0];
+ const arch_register_t *in2 = attr->x87[1];
+ const arch_register_t *out = attr->x87[2];
const arch_register_t *in;
in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
*/
static
void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
- const char *reg = attr->x87[1]->name;
- long pnc = get_ia32_pncode(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ const char *reg = attr->x87[1]->name;
+ long pnc = get_ia32_pncode(node);
switch (get_ia32_irn_opcode(node)) {
case iro_ia32_fcomrJmp:
static
void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
{
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
if(attr->am_sc != NULL) {
ident *id = get_entity_ld_ident(attr->am_sc);
const char *s)
{
const arch_register_t *reg;
- const char *reg_name;
- char c;
- char modifier = 0;
- int num = -1;
- ia32_attr_t *attr;
- int n_outs;
- int p;
+ const char *reg_name;
+ char c;
+ char modifier = 0;
+ int num = -1;
+ const ia32_attr_t *attr;
+ int n_outs;
+ int p;
assert(*s == '%');
c = *(++s);
}
/* get register */
- attr = get_ia32_attr(node);
- n_outs = attr->data.n_res;
+ attr = get_ia32_attr_const(node);
+ n_outs = ARR_LEN(attr->slots);
if(num < n_outs) {
reg = get_out_reg(env, node, num);
} else {
static
void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
{
- ia32_attr_t *attr = get_ia32_attr(node);
- ident *asm_text = attr->cnst_val.asm_text;
- const char *s = get_id_str(asm_text);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ ident *asm_text = attr->cnst_val.asm_text;
+ const char *s = get_id_str(asm_text);
be_emit_cstring(env, "# Begin ASM \t");
be_emit_finish_line_gas(env, node);
* |___/
***************************************************************************************************/
-/**
- * Wraps get_irn_generic_attr() as it takes no const ir_node, so we need to do a cast.
- * Firm was made by people hating const :-(
- */
-ia32_attr_t *get_ia32_attr(const ir_node *node) {
+ia32_attr_t *get_ia32_attr(ir_node *node) {
assert(is_ia32_irn(node) && "need ia32 node to get ia32 attributes");
- return (ia32_attr_t *)get_irn_generic_attr((ir_node *)node);
+ return (ia32_attr_t *)get_irn_generic_attr(node);
}
const ia32_attr_t *get_ia32_attr_const(const ir_node *node) {
* Gets the type of an ia32 node.
*/
ia32_op_type_t get_ia32_op_type(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.tp;
}
* Gets the immediate op type of an ia32 node.
*/
ia32_immop_type_t get_ia32_immop_type(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.imm_tp;
}
* Gets the supported address mode of an ia32 node
*/
ia32_am_type_t get_ia32_am_support(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.am_support;
}
* Gets the address mode flavour of an ia32 node
*/
ia32_am_flavour_t get_ia32_am_flavour(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.am_flavour;
}
* Gets the address mode offset as int.
*/
int get_ia32_am_offs_int(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->am_offs;
}
* Returns the symconst entity associated to address mode.
*/
ir_entity *get_ia32_am_sc(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->am_sc;
}
* Returns the sign bit for address mode symconst.
*/
int is_ia32_am_sc_sign(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.am_sc_sign;
}
* Gets the addr mode const.
*/
int get_ia32_am_scale(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.am_scale;
}
* Return the tarval of an immediate operation or NULL in case of SymConst
*/
tarval *get_ia32_Immop_tarval(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
assert(attr->data.imm_tp == ia32_ImmConst);
return attr->cnst_val.tv;
}
}
ir_entity *get_ia32_Immop_symconst(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
assert(attr->data.imm_tp == ia32_ImmSymConst);
return attr->cnst_val.sc;
}
* Gets the uses_frame flag.
*/
int is_ia32_use_frame(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.use_frame;
}
* Checks if node is commutative.
*/
int is_ia32_commutative(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.is_commutative;
}
* Checks if node needs %cl.
*/
int is_ia32_emit_cl(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.emit_cl;
}
* Checks if node got lea.
*/
int is_ia32_got_lea(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.got_lea;
}
}
int is_ia32_need_stackent(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.need_stackent;
}
* Gets the mode of the stored/loaded value (only set for Store/Load)
*/
ir_mode *get_ia32_ls_mode(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->ls_mode;
}
* Gets the frame entity assigned to this node.
*/
ir_entity *get_ia32_frame_ent(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->frame_ent;
}
* Gets the instruction latency.
*/
unsigned get_ia32_latency(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->latency;
}
* Returns the argument register requirements of an ia32 node.
*/
const arch_register_req_t **get_ia32_in_req_all(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->in_req;
}
* Returns the result register requirements of an ia32 node.
*/
const arch_register_req_t **get_ia32_out_req_all(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->out_req;
}
* Returns the argument register requirement at position pos of an ia32 node.
*/
const arch_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
if(attr->in_req == NULL)
return arch_no_register_req;
* Returns the result register requirement at position pos of an ia32 node.
*/
const arch_register_req_t *get_ia32_out_req(const ir_node *node, int pos) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
if(attr->out_req == NULL)
return arch_no_register_req;
* Returns the register flag of an ia32 node.
*/
arch_irn_flags_t get_ia32_flags(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.flags;
}
* Returns the result register slots of an ia32 node.
*/
const arch_register_t **get_ia32_slots(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->slots;
}
-/**
- * Sets the number of results.
- */
-void set_ia32_n_res(ir_node *node, int n_res) {
- ia32_attr_t *attr = get_ia32_attr(node);
- attr->data.n_res = n_res;
-}
-
/**
* Returns the number of results.
*/
int get_ia32_n_res(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
- return attr->data.n_res;
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ return ARR_LEN(attr->slots);
}
/**
* Returns the flavour of an ia32 node,
*/
ia32_op_flavour_t get_ia32_flavour(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.op_flav;
}
* Returns the projnum code.
*/
pn_Cmp get_ia32_pncode(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->pn_code;
}
*/
void set_ia32_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
ia32_attr_t *attr = get_ia32_attr(node);
- assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
attr->out_flags[pos] = flags;
}
* Gets the flags for the n'th out.
*/
arch_irn_flags_t get_ia32_out_flags(const ir_node *node, int pos) {
- ia32_attr_t *attr = get_ia32_attr(node);
- return pos < (int)attr->data.n_res ? attr->out_flags[pos] : arch_irn_flags_none;
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
+ return attr->out_flags[pos];
}
/**
* Get the list of available execution units.
*/
const be_execution_unit_t ***get_ia32_exec_units(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->exec_units;
}
* Get the exception label attribute.
*/
unsigned get_ia32_exc_label(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->data.except_label;
}
* Returns the name of the original ir node.
*/
const char *get_ia32_orig_node(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return attr->orig_node;
}
* Returns whether or not the node is an immediate operation with Const.
*/
int is_ia32_ImmConst(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return (attr->data.imm_tp == ia32_ImmConst);
}
* Returns whether or not the node is an immediate operation with SymConst.
*/
int is_ia32_ImmSymConst(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return (attr->data.imm_tp == ia32_ImmSymConst);
}
* Returns whether or not the node is an AddrModeS node.
*/
int is_ia32_AddrModeS(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return (attr->data.tp == ia32_AddrModeS);
}
* Returns whether or not the node is an AddrModeD node.
*/
int is_ia32_AddrModeD(const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
return (attr->data.tp == ia32_AddrModeD);
}
* Returns the name of the OUT register at position pos.
*/
const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
- assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
* Returns the index of the OUT register at position pos within its register class.
*/
int get_ia32_out_regnr(const ir_node *node, int pos) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
- assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
* Returns the OUT register at position pos.
*/
const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
- assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
const be_execution_unit_t ***execution_units,
int n_res, unsigned latency)
{
- ia32_attr_t *attr = get_ia32_attr(node);
+ ir_graph *irg = get_irn_irg(node);
+ struct obstack *obst = get_irg_obstack(irg);
+ ia32_attr_t *attr = get_ia32_attr(node);
set_ia32_flags(node, flags);
set_ia32_in_req_all(node, in_reqs);
set_ia32_out_req_all(node, out_reqs);
set_ia32_latency(node, latency);
- set_ia32_n_res(node, n_res);
attr->exec_units = execution_units;
- attr->out_flags = NEW_ARR_D(int, get_irg_obstack(get_irn_irg(node)), n_res);
+ attr->out_flags = NEW_ARR_D(int, obst, n_res);
memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
- memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
+ attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
+ memset(attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
ir_node *get_ia32_result_proj(const ir_node *node)
***************************************************************************************/
/* default compare operation to compare attributes */
-int ia32_compare_attr(ia32_attr_t *a, ia32_attr_t *b) {
+int ia32_compare_attr(const ia32_attr_t *a, const ia32_attr_t *b) {
if (a->data.tp != b->data.tp
|| a->data.imm_tp != b->data.imm_tp)
return 1;
}
/* copies the ia32 attributes */
-static void ia32_copy_attr(const ir_node *old_node, ir_node *new_node) {
- ia32_attr_t *attr_old = get_ia32_attr(old_node);
- ia32_attr_t *attr_new = get_ia32_attr(new_node);
+static void ia32_copy_attr(const ir_node *old_node, ir_node *new_node)
+{
+ ir_graph *irg = get_irn_irg(new_node);
+ struct obstack *obst = get_irg_obstack(irg);
+ const ia32_attr_t *attr_old = get_ia32_attr_const(old_node);
+ ia32_attr_t *attr_new = get_ia32_attr(new_node);
/* copy the attributes */
memcpy(attr_new, attr_old, get_op_attr_size(get_irn_op(old_node)));
/* copy out flags */
attr_new->out_flags =
- DUP_ARR_D(int, get_irg_obstack(get_irn_irg(new_node)), attr_old->out_flags);
+ DUP_ARR_D(int, obst, attr_old->out_flags);
+ /* copy register assignments */
+ attr_new->slots =
+ DUP_ARR_D(const arch_register_t*, obst, attr_old->slots);
}
/* Include the generated constructor functions */
/**
* Returns the attributes of an ia32 node.
*/
-ia32_attr_t *get_ia32_attr(const ir_node *node);
+ia32_attr_t *get_ia32_attr(ir_node *node);
const ia32_attr_t *get_ia32_attr_const(const ir_node *node);
*/
const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos);
-/**
- * Sets the number of results.
- */
-void set_ia32_n_res(ir_node *node, int n_res);
-
/**
* Returns the number of results.
*/
unsigned got_lea:1; /**< Indicates whether or not this node already consumed a LEA. */
unsigned need_stackent:1; /**< Set to 1 if node need space on stack. */
-
- unsigned n_res:6; /**< Number of results produced by this node. */
} data;
int *out_flags; /**< flags for each produced value */
const arch_register_t *x87[3]; /**< register slots for x87 register */
- /* must be last, dynamic */
- const arch_register_t *slots[1]; /**< register slots for assigned registers */
+ const arch_register_t **slots; /**< register slots for assigned registers */
};
#endif /* FIRM_BE_IA32_IA32_NODES_ATTR_H */
set_ia32_am_support(res, ia32_am_Source);
#endif
- set_ia32_n_res(res, 2);
-
/* check, which Proj-Keep, we need to add */
i = 0;
if (proj_div == NULL) {
}
/* dump OUT requirements */
- if (attr->n_res > 0) {
+ if (ARR_LEN(attr->slots) > 0) {
reqs = get_mips_out_req_all(n);
dump_reg_req(F, n, reqs, 1);
}
/* dump assigned registers */
slots = get_mips_slots(n);
- if (slots && attr->n_res > 0) {
- for (i = 0; i < attr->n_res; i++) {
+ if (slots && ARR_LEN(attr->slots) > 0) {
+ for (i = 0; i < ARR_LEN(attr->slots); i++) {
if (slots[i]) {
fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
}
mips_attr_t *attr = get_mips_attr(node);
assert(is_mips_irn(node) && "Not an mips node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
mips_attr_t *attr = get_mips_attr(node);
assert(is_mips_irn(node) && "Not an mips node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
mips_attr_t *attr = get_mips_attr(node);
assert(is_mips_irn(node) && "Not an mips node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
}
-/**
- * Sets the number of results.
- */
-void set_mips_n_res(ir_node *node, int n_res) {
- mips_attr_t *attr = get_mips_attr(node);
- attr->n_res = n_res;
-}
-
/**
* Returns the number of results.
*/
int get_mips_n_res(const ir_node *node) {
mips_attr_t *attr = get_mips_attr(node);
- return attr->n_res;
+ return ARR_LEN(attr->slots);
}
/**
const be_execution_unit_t ***execution_units,
int n_res, unsigned latency)
{
- mips_attr_t *attr = get_mips_attr(node);
+ ir_graph *irg = get_irn_irg(node);
+ struct obstack *obst = get_irg_obstack(irg);
+ mips_attr_t *attr = get_mips_attr(node);
- attr->flags = flags;
+ attr->flags = flags;
attr->out_req = out_reqs;
+ attr->in_req = in_reqs;
- attr->n_res = n_res;
- attr->in_req = in_reqs;
-
- memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
+ attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
+ memset(attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
static
-int mips_compare_attr(mips_attr_t *a, mips_attr_t *b)
+int mips_compare_attr(const mips_attr_t *a, const mips_attr_t *b)
{
if(a->tv != b->tv)
return 1;
return 1;
if(a->flags != b->flags)
return 1;
- if(a->n_res != b->n_res)
+ if(ARR_LEN(a->slots) != ARR_LEN(b->slots))
return 1;
if(a->switch_default_pn != b->switch_default_pn)
return 1;
*/
const arch_register_t *get_mips_out_reg(const ir_node *node, int pos);
-/**
- * Sets the number of results.
- */
-void set_mips_n_res(ir_node *node, int n_res);
-
/**
* Returns the number of results.
*/
typedef struct _mips_attr_t {
arch_irn_flags_t flags; /**< indicating if spillable, rematerializeable ... etc. */
- int n_res; /**< number of results for this node */
tarval *tv; /**< contains the immediate value */
ir_entity *symconst;
const arch_register_req_t **in_req; /**< register requirements for arguments */
const arch_register_req_t **out_req; /**< register requirements for results */
- /* must be last, dynamically allocated */
- const arch_register_t *slots[1]; /**< register slots for assigned registers */
+ const arch_register_t **slots; /**< register slots for assigned registers */
} mips_attr_t;
#endif
}
int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_ppc32_irn(irn);
+ if(!is_ppc32_irn(irn))
+ return -1;
+
+ return 1;
}
/**
}
/* dump OUT requirements */
- if (attr->n_res > 0) {
+ if (ARR_LEN(attr->slots) > 0) {
reqs = get_ppc32_out_req_all(n);
dump_reg_req(F, n, reqs, 1);
}
/* dump assigned registers */
slots = get_ppc32_slots(n);
- if (slots && attr->n_res > 0) {
- for (i = 0; i < attr->n_res; i++) {
+ if (slots && ARR_LEN(attr->slots) > 0) {
+ for (i = 0; i < ARR_LEN(attr->slots); i++) {
if (slots[i]) {
fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
}
ppc32_attr_t *attr = get_ppc32_attr(node);
assert(is_ppc32_irn(node) && "Not an ppc node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
ppc32_attr_t *attr = get_ppc32_attr(node);
assert(is_ppc32_irn(node) && "Not an ppc node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
ppc32_attr_t *attr = get_ppc32_attr(node);
assert(is_ppc32_irn(node) && "Not an ppc node.");
- assert(pos < attr->n_res && "Invalid OUT position.");
+ assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
}
-/**
- * Sets the number of results.
- */
-void set_ppc32_n_res(ir_node *node, int n_res) {
- ppc32_attr_t *attr = get_ppc32_attr(node);
- attr->n_res = n_res;
-}
-
/**
* Returns the number of results.
*/
int get_ppc32_n_res(const ir_node *node) {
ppc32_attr_t *attr = get_ppc32_attr(node);
- return attr->n_res;
+ return ARR_LEN(attr->slots);
}
/**
const arch_register_req_t **in_reqs, const arch_register_req_t **out_reqs,
const be_execution_unit_t ***execution_units,
int n_res, unsigned latency) {
- ppc32_attr_t *attr = get_ppc32_attr(node);
+ ir_graph *irg = get_irn_irg(node);
+ struct obstack *obst = get_irg_obstack(irg);
+ ppc32_attr_t *attr = get_ppc32_attr(node);
attr->flags = flags;
attr->in_req = in_reqs;
attr->out_req = out_reqs;
- attr->n_res = n_res;
attr->content_type = ppc32_ac_None;
attr->offset_mode = ppc32_ao_Illegal;
attr->data.empty = NULL;
- memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
+ attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
+ memset(attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
*/
const arch_register_t *get_ppc32_out_reg(const ir_node *node, int pos);
-/**
- * Sets the number of results.
- */
-void set_ppc32_n_res(ir_node *node, int n_res);
-
/**
* Returns the number of results.
*/
typedef struct _ppc32_attr_t {
arch_irn_flags_t flags; /**< indicating if spillable, rematerializeable ... etc. */
- int n_res; /**< number of results for this node */
const arch_register_req_t **in_req; /**< register requirements for arguments */
const arch_register_req_t **out_req; /**< register requirements for results */
void* empty;
} data;
- /* must be last, dynamically allocated */
- const arch_register_t *slots[1]; /**< register slots for assigned registers */
+ const arch_register_t **slots; /**< register slots for assigned registers */
} ppc32_attr_t;
#endif
$n_res = "20"; # hacky....
}
$temp = "\top_$op = new_ir_op(cur_opcode + iro_$op, \"$op\", op_pin_state_".$n{"state"}.", ".$n{"op_flags"};
- $temp .= "|M, ".translate_arity($arity).", 0, sizeof(${attr_type}) + $n_res * sizeof(arch_register_t *), &ops);\n";
+ $temp .= "|M, ".translate_arity($arity).", 0, sizeof(${attr_type}), &ops);\n";
push(@obst_new_irop, $temp);
push(@obst_new_irop, "\tset_op_tag(op_$op, &$arch\_op_tag);\n");
push(@obst_enum_op, "\tiro_$op,\n");
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