if(!mode_is_data(get_irn_mode(node)))
return;
- reg = arch_get_irn_register(arch_env, node);
+ reg = arch_get_irn_register(arch_env, node);
if(reg == NULL) {
panic("No register assigned at %+F\n", node);
}
arity = get_irn_arity(node);
for(i = 0; i < arity; ++i) {
ir_node *in = get_irn_n(node, i);
+
+ if(!mode_is_data(get_irn_mode(in)))
+ continue;
+
const arch_register_t *reg =
arch_get_irn_register(env->arch_env, in);
if(reg == env->reg) {
foreach_out_edge(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
+
+ if(!mode_is_data(get_irn_mode(proj)))
+ continue;
+
const arch_register_t *reg =
arch_get_irn_register(env->arch_env, proj);
if(reg == env->reg) {
}
}
} else {
- const arch_register_t *reg =
- arch_get_irn_register(env->arch_env, node);
- if(reg == env->reg) {
- current_state = node;
- DBG((dbg, LEVEL_3, "\t... current_state <- %+F\n", current_state));
+ if(mode_is_data(get_irn_mode(node))) {
+ const arch_register_t *reg =
+ arch_get_irn_register(env->arch_env, node);
+ if(reg == env->reg) {
+ current_state = node;
+ DBG((dbg, LEVEL_3, "\t... current_state <- %+F\n", current_state));
+ }
}
}
}
if (is_ia32_irn(irn)) {
const arch_register_t **slots;
slots = get_ia32_slots(irn);
+ assert(pos < get_ia32_n_res(irn));
reg = slots[pos];
} else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
{
collect_fpu_mode_nodes_env_t *env = data;
+ if(!mode_is_data(get_irn_mode(node)))
+ return;
+
const arch_register_t *reg = arch_get_irn_register(env->arch_env, node);
if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
ARR_APP1(ir_node*, env->state_nodes, node);
fldz => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
emit => '. fldz',
attr_type => "ia32_x87_attr_t",
},
fld1 => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fld1',
attr_type => "ia32_x87_attr_t",
},
fldpi => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldpi',
attr_type => "ia32_x87_attr_t",
},
fldln2 => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldln2',
attr_type => "ia32_x87_attr_t",
},
fldlg2 => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldlg2',
attr_type => "ia32_x87_attr_t",
},
fldl2t => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldll2t',
attr_type => "ia32_x87_attr_t",
},
fldl2e => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldl2e',
attr_type => "ia32_x87_attr_t",
},
keep_float_node_alive(state, pred);
}
- DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
- arch_get_irn_register(sim->arch_env, node)->name));
+ DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
} else {
out_idx = x87_on_stack(state, arch_register_get_index(out));