}
}
-int arch_get_allocatable_regs(const arch_env_t *env, const ir_node *irn, int pos, bitset_t *bs)
+int arch_get_allocatable_regs(const ir_node *irn, int pos, bitset_t *bs)
{
const arch_irn_ops_t *ops = get_irn_ops(irn);
const arch_register_req_t *req = ops->get_irn_reg_req(irn, pos);
- (void)env; // TODO remove parameter
if(req->type == arch_register_req_type_none) {
bitset_clear_all(bs);
/**
* Get the number of allocatable registers concerning
* a register class for an operand of a node.
- * @param env The environment.
* @param irn The node.
* @param pos The position of the node's operand.
* @param bs The bitset all allocatable registers shall be put into.
* has registers.
* @return The amount of registers allocatable for that operand.
*/
-extern int arch_get_allocatable_regs(const arch_env_t *env, const ir_node *irn, int pos, bitset_t *bs);
+int arch_get_allocatable_regs(const ir_node *irn, int pos, bitset_t *bs);
/**
* Put all registers which shall not be ignored by the register
static void ou_optimize(unit_t *ou) {
int i;
qnode_t *curr = NULL, *tmp;
- const arch_env_t *aenv = ou->co->aenv;
const arch_register_class_t *cls = ou->co->cls;
bitset_pos_t idx;
bitset_t *pos_regs = bitset_alloca(cls->n_regs);
/* init queue */
INIT_LIST_HEAD(&ou->queue);
- arch_get_allocatable_regs(aenv, ou->nodes[0], -1, pos_regs);
+ arch_get_allocatable_regs(ou->nodes[0], -1, pos_regs);
/* exclude ignore colors */
bitset_andnot(pos_regs, ou->co->cenv->ignore_colors);