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..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\ia32 \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\ia32 \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\ia32 \
"..\ir\be\ia32\gen_ia32_emitter.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
"..\ir\be\ia32\gen_ia32_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
+
+"..\ir\be\ia32\gen_ia32_machine.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
+ $(BuildCmds)
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SOURCE=..\ir\be\ia32\ia32_x87.c
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# Begin Custom Build - Translate Spec: $(InputPath)
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BuildCmds= \
..\ir\be\scripts\generate_emitter.pl $(InputPath) ..\ir\be\arm \
..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\arm \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\arm \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\arm \
"..\ir\be\arm\gen_arm_emitter.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
"..\ir\be\arm\gen_arm_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
+
+"..\ir\be\arm\gen_arm_machine.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
+ $(BuildCmds)
+
+"..\ir\be\arm\gen_arm_machine.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
+ $(BuildCmds)
# End Custom Build
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-USERDEP__ARM_S="..\ir\be\scripts\generate_emitter.pl" "..\ir\be\scripts\generate_new_opcodes.pl" "..\ir\be\scripts\generate_regalloc_if.pl"
+USERDEP__ARM_S="..\ir\be\scripts\generate_emitter.pl" "..\ir\be\scripts\generate_new_opcodes.pl" "..\ir\be\scripts\generate_regalloc_if.pl" "..\ir\be\scripts\generate_machine.pl"
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InputPath="..\ir\be\arm\arm_spec.pl"
..\ir\be\scripts\generate_emitter.pl $(InputPath) ..\ir\be\arm \
..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\arm \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\arm \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\arm \
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"..\ir\be\arm\gen_arm_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
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+"..\ir\be\arm\gen_arm_machine.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
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SOURCE=..\ir\be\arm\gen_arm_new_nodes.c.inl
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SOURCE=..\ir\be\ppc32\gen_ppc32_new_nodes.c.inl
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-USERDEP__PPC32="..\ir\be\scripts\generate_emitter.pl" "..\ir\be\scripts\generate_new_opcodes.pl" "..\ir\be\scripts\generate_regalloc_if.pl"
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# Begin Custom Build - Translate Spec: $(InputPath)
InputPath=..\ir\be\ppc32\ppc32_spec.pl
..\ir\be\scripts\generate_emitter.pl $(InputPath) ..\ir\be\ppc32 \
..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\ppc32 \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\ppc32 \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\ppc32 \
"..\ir\be\ppc32\gen_ppc32_emitter.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
"..\ir\be\ppc32\gen_ppc32_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
+
+"..\ir\be\ppc32\gen_ppc32_machine.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
+ $(BuildCmds)
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+"..\ir\be\ppc32\gen_ppc32_machine.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
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# End Custom Build
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InputPath=..\ir\be\ppc32\ppc32_spec.pl
..\ir\be\scripts\generate_emitter.pl $(InputPath) ..\ir\be\ppc32 \
..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\ppc32 \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\ppc32 \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\ppc32 \
"..\ir\be\ppc32\gen_ppc32_emitter.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
"..\ir\be\ppc32\gen_ppc32_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
+
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InputPath=..\ir\be\mips\mips_spec.pl
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..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\mips \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\mips \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\mips \
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"..\ir\be\mips\gen_mips_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
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..\ir\be\scripts\generate_new_opcodes.pl $(InputPath) ..\ir\be\mips \
..\ir\be\scripts\generate_regalloc_if.pl $(InputPath) ..\ir\be\mips \
+ ..\ir\be\scripts\generate_machine.pl $(InputPath) ..\ir\be\mips \
"..\ir\be\mips\gen_mips_emitter.c" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
"..\ir\be\mips\gen_mips_regalloc_if_t.h" : $(SOURCE) "$(INTDIR)" "$(OUTDIR)"
$(BuildCmds)
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