/* insert into set of spills if not already there */
spill.spill = node;
- res = set_find(env->spills, &spill, sizeof(spill), hash);
+ res = set_find(env->spills, &spill, sizeof(spill), hash);
if(res == NULL) {
spill.spillslot = set_count(env->spills);
- spill.mode = mode;
+ spill.mode = mode;
spill.alignment = align;
- res = set_insert(env->spills, &spill, sizeof(spill), hash);
+ res = set_insert(env->spills, &spill, sizeof(spill), hash);
} else {
assert(res->mode == mode);
assert(res->alignment == align);
}
spill.spillslot = set_count(env->spills);
- spill.mode = mode;
+ spill.mode = mode;
spill.alignment = align;
- res = set_insert(env->spills, &spill, sizeof(spill), hash);
+ res = set_insert(env->spills, &spill, sizeof(spill), hash);
// collect attached spills and mem-phis
arity = get_irn_arity(node);
}
// add an affinity edge
- affinty_edge = obstack_alloc(&env->obst, sizeof(affinty_edge[0]));
+ affinty_edge = obstack_alloc(&env->obst, sizeof(affinty_edge[0]));
affinty_edge->affinity = get_block_execfreq(exec_freq, get_nodes_block(arg));
- affinty_edge->slot1 = res->spillslot;
- affinty_edge->slot2 = arg_spill->spillslot;
+ affinty_edge->slot1 = res->spillslot;
+ affinty_edge->slot2 = arg_spill->spillslot;
ARR_APP1(affinity_edge_t*, env->affinity_edges, affinty_edge);
}
return res;
}
+static int my_values_interfere2(be_irg_t *birg, const ir_node *a,
+ const ir_node *b)
+{
+ be_lv_t *lv = be_get_birg_liveness(birg);
+
+ int a2b = _value_dominates(a, b);
+ int b2a = _value_dominates(b, a);
+
+ /* If there is no dominance relation, they do not interfere. */
+ if((a2b | b2a) > 0) {
+ const ir_edge_t *edge;
+ ir_node *bb;
+
+ /*
+ * Adjust a and b so, that a dominates b if
+ * a dominates b or vice versa.
+ */
+ if(b2a) {
+ const ir_node *t = a;
+ a = b;
+ b = t;
+ }
+
+ bb = get_nodes_block(b);
+
+ /*
+ * If a is live end in b's block it is
+ * live at b's definition (a dominates b)
+ */
+ if(be_is_live_end(lv, bb, a))
+ return 1;
+
+ /*
+ * Look at all usages of a.
+ * If there's one usage of a in the block of b, then
+ * we check, if this use is dominated by b, if that's true
+ * a and b interfere. Note that b must strictly dominate the user,
+ * since if b is the last user of in the block, b and a do not
+ * interfere.
+ * Uses of a not in b's block can be disobeyed, because the
+ * check for a being live at the end of b's block is already
+ * performed.
+ */
+ foreach_out_edge(a, edge) {
+ const ir_node *user = get_edge_src_irn(edge);
+ if(is_Sync(user)) {
+ const ir_edge_t *edge2;
+ foreach_out_edge(user, edge2) {
+ const ir_node *user2 = get_edge_src_irn(edge2);
+ assert(!is_Sync(user2));
+ if(get_nodes_block(user2) == bb && !is_Phi(user2) &&
+ _value_strictly_dominates(b, user2))
+ return 1;
+ }
+ } else {
+ if(get_nodes_block(user) == bb && !is_Phi(user) &&
+ _value_strictly_dominates(b, user))
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * same as values_interfere but with special handling for Syncs
+ */
+static int my_values_interfere(be_irg_t *birg, ir_node *a, ir_node *b)
+{
+ if(is_Sync(a)) {
+ int i, arity = get_irn_arity(a);
+ for(i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(a, i);
+ if(my_values_interfere(birg, in, b))
+ return 1;
+ }
+ return 0;
+ } else if(is_Sync(b)) {
+ int i, arity = get_irn_arity(b);
+ for(i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(b, i);
+ /* a is not a sync, so no need for my_values_interfere */
+ if(my_values_interfere2(birg, a, in))
+ return 1;
+ }
+ return 0;
+ }
+
+ return my_values_interfere2(birg, a, b);
+}
+
/**
* A greedy coalescing algorithm for spillslots:
* 1. Sort the list of affinity edges
if (is_NoMem(spill2))
continue;
- if (values_interfere(env->birg, spill1, spill2)) {
+ if (my_values_interfere(env->birg, spill1, spill2)) {
DBG((dbg, DBG_INTERFERENCES, "Slot %d and %d interfere\n", i, i2));
bitset_set(interferences[i], i2);
bitset_set(interferences[i2], i);
}
}
+
+static void assign_spill_entity(const arch_env_t *arch_env, ir_node *node, ir_entity *entity)
+{
+ if(is_NoMem(node))
+ return;
+ if(is_Sync(node)) {
+ int i, arity;
+
+ arity = get_irn_arity(node);
+ for(i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ assert(!is_Phi(in));
+
+ assign_spill_entity(arch_env, in, entity);
+ }
+ return;
+ }
+
+ arch_set_frame_entity(arch_env, node, entity);
+}
+
/**
* Create stack entities for the spillslots and assign them to the spill and
* reload nodes.
}
}
} else {
- if(!is_NoMem(node))
- arch_set_frame_entity(arch_env, node, slot->entity);
+ assign_spill_entity(arch_env, node, slot->entity);
}
}
} else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
&& is_ia32_use_frame(node)) {
if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = get_mode_size_bytes(mode);
+ const ir_mode *mode = get_ia32_ls_mode(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ int align = get_mode_size_bytes(mode);
+
+ if(attr->data.need_64bit_stackent) {
+ mode = mode_Ls;
+ }
be_node_needs_frame_entity(env, node, mode, align);
} else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
|| is_ia32_vfld(node)) {
* Set output modes for GCC
*/
static const tarval_mode_info mo_integer = {
- TVO_DECIMAL,
- NULL,
+ TVO_HEX,
+ "0x",
NULL,
};
(void)i;
(void)j;
+#if 1
if(is_Proj(sel)) {
ir_node *pred = get_Proj_pred(sel);
if(is_Cmp(pred)) {
return 0;
}
}
+#endif
/* check the Phi nodes */
for (phi = phi_list; phi; phi = get_irn_link(phi)) {
unsigned got_lea:1; /**< Indicates whether or not this node already consumed a LEA. */
unsigned need_stackent:1; /**< Set to 1 if node need space on stack. */
+ unsigned need_64bit_stackent:1; /**< needs a 64bit stack entity (see double->unsigned int conv) */
} data;
int *out_flags; /**< flags for each produced value */
TestCMov => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
- ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
latency => 2,
vfCmpCMov => {
irn_flags => "R",
- reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
latency => 10,
- units => [ "VFP" ],
+ units => [ "VFP", "GP" ],
mode => $mode_gp,
attr_type => "ia32_x87_attr_t",
},
CmpSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
TestSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fild%XM %AM',
+ emit => '. fild%M %AM',
attr_type => "ia32_x87_attr_t",
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fist%XM %AM',
+ emit => '. fist%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fistp%XM %AM',
+ emit => '. fistp%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
/**
* @file
- * @brief This file implements the IR transformation from firm into ia32-Firm.
+ * @brief This file implements the IR transformation from firm into
+ * ia32-Firm.
* @author Christian Wuerdig, Matthias Braun
* @version $Id$
*/
assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
+ assert(mode_needs_gp_reg(get_irn_mode(node)));
if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
/* a mode_b value, we have to compare it against 0 */
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
+ ir_mode *mode = get_irn_mode(node);
ir_node *fist, *load;
/* do a fist */
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_am_flavour(fist, ia32_am_B);
- set_ia32_ls_mode(fist, mode_Iu);
+
+ assert(get_mode_size_bits(mode) <= 32);
+ /* exception we can only store signed 32 bit integers, so for unsigned
+ we store a 64bit (signed) integer and load the lower bits */
+ if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
+ set_ia32_ls_mode(fist, mode_Ls);
+ } else {
+ set_ia32_ls_mode(fist, mode_Is);
+ }
SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
/* do a Load */
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_flavour(load, ia32_am_B);
- set_ia32_ls_mode(load, mode_Iu);
+ set_ia32_ls_mode(load, mode_Is);
SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
+ ir_mode *mode = get_irn_mode(op);
+ ir_mode *store_mode;
ir_node *fild, *store;
ir_node *res;
int src_bits;
- /* first convert to 32 bit if necessary */
+ /* first convert to 32 bit signed if necessary */
src_bits = get_mode_size_bits(src_mode);
if (src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
+ new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
+ src_mode);
set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ mode = mode_Is;
} else if (src_bits < 32) {
new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ mode = mode_Is;
}
+ assert(get_mode_size_bits(mode) == 32);
+
/* do a store */
store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
set_ia32_am_flavour(store, ia32_am_OB);
set_ia32_ls_mode(store, mode_Iu);
+ /* exception for 32bit unsigned, do a 64bit spill+load */
+ if(!mode_is_signed(mode)) {
+ ir_node *in[2];
+ /* store a zero */
+ ir_node *zero_const = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 0);
+
+ ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
+ zero_const, nomem);
+
+ arch_set_irn_register(env_cg->arch_env, zero_const, &ia32_gp_regs[REG_GP_NOREG]);
+
+ set_ia32_use_frame(zero_store);
+ set_ia32_op_type(zero_store, ia32_AddrModeD);
+ add_ia32_am_offs_int(zero_store, 4);
+ set_ia32_ls_mode(zero_store, mode_Iu);
+
+ in[0] = zero_store;
+ in[1] = store;
+
+ store = new_rd_Sync(dbgi, irg, block, 2, in);
+ store_mode = mode_Ls;
+ } else {
+ store_mode = mode_Is;
+ }
+
/* do a fild */
fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_am_flavour(fild, ia32_am_OB);
- set_ia32_ls_mode(fild, mode_Iu);
+ set_ia32_ls_mode(fild, store_mode);
res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
double value = 4294967295;
int main(void) {
- float res = (double) (randn % (unsigned int) value);
+ double res = (double) (randn % (unsigned int) value);
printf("Res: %f\n", res);
return 0;
}
projects / libfirm / commitdiff