#include "../bemodule.h"
#include "../beblocksched.h"
#include "../beirg_t.h"
+#include "../begnuas.h"
#include "pset.h"
#define DEBUG_MODULE "firm.be.ppc.isa"
int isleaf;
-pset *symbol_pset = NULL;
/* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
static set *cur_reg_set = NULL;
*/
static void ppc32_emit_and_done(void *self) {
ppc32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->isa->out;
-
- if (cg->emit_decls) {
- ppc32_gen_decls(out);
- cg->emit_decls = 0;
- }
+ ir_graph *irg = cg->irg;
dump_ir_block_graph_sched(irg, "-ppc-finished");
- ppc32_gen_routine(out, irg, cg);
+ ppc32_gen_routine(cg, irg);
cur_reg_set = NULL;
/* de-allocate code generator */
del_set(cg->reg_set);
free(self);
-
- if(symbol_pset)
- {
- del_pset(symbol_pset);
- symbol_pset = NULL;
- }
}
int is_direct_entity(ir_entity *ent);
-/**
- * Collects all SymConsts which need to be accessed "indirectly"
- *
- * @param node the firm node
- * @param env the debug module
- */
-void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
- if(get_irn_op(node) == op_SymConst)
- {
- ir_entity *ent = get_SymConst_entity(node);
- if(!is_direct_entity(ent))
- pset_insert_ptr(symbol_pset, ent);
- }
-}
-
static void *ppc32_cg_init(be_irg_t *birg);
static const arch_code_generator_if_t ppc32_code_gen_if = {
cg->blk_sched = NULL;
FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- {
- int i;
- cg->emit_decls = 1;
- symbol_pset = pset_new_ptr(8);
- for(i=0; i<get_irp_n_irgs(); i++)
- {
- cg->irg = get_irp_irg(i);
- irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
- }
- cg->irg = birg->irg;
- }
-
cur_reg_set = cg->reg_set;
-
ppc32_irn_ops.cg = cg;
return (arch_code_generator_t *)cg;
*****************************************************************/
static ppc32_isa_t ppc32_isa_template = {
- &ppc32_isa_if,
- &ppc32_gp_regs[REG_R1], // stack pointer
- &ppc32_gp_regs[REG_R31], // base pointer
- -1, // stack is decreasing
- 0, // num codegens... ??
- NULL
+ {
+ &ppc32_isa_if, /* isa interface */
+ &ppc32_gp_regs[REG_R1], /* stack pointer */
+ &ppc32_gp_regs[REG_R31], /* base pointer */
+ -1, /* stack is decreasing */
+ NULL, /* main environment */
+ },
+ { NULL, }, /* emitter environment */
+ NULL /* symbol set */
};
+/**
+ * Collects all SymConsts which need to be accessed "indirectly"
+ *
+ * @param node the firm node
+ * @param env the symbol set
+ */
+static void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
+ pset *symbol_set = env;
+
+ if (is_SymConst(node)) {
+ ir_entity *ent = get_SymConst_entity(node);
+ mark_entity_visited(ent);
+ if (! is_direct_entity(ent))
+ pset_insert_ptr(symbol_set, ent);
+ }
+}
+
/**
* Initializes the backend ISA and opens the output file.
*/
static void *ppc32_init(FILE *file_handle) {
static int inited = 0;
ppc32_isa_t *isa;
+ int i;
- if(inited)
+ if (inited)
return NULL;
isa = xmalloc(sizeof(*isa));
memcpy(isa, &ppc32_isa_template, sizeof(*isa));
- isa->out = file_handle;
+ be_emit_init_env(&isa->emit, file_handle);
ppc32_register_init(isa);
ppc32_create_opcodes();
inited = 1;
+ isa->symbol_set = pset_new_ptr(8);
+ for (i = 0; i < get_irp_n_irgs(); ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ irg_walk_blkwise_graph(irg, NULL, ppc32_collect_symconsts_walk, isa->symbol_set);
+ }
+
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
+
return isa;
}
+static void ppc32_dump_indirect_symbols(ppc32_isa_t *isa) {
+ ir_entity *ent;
+ foreach_pset(isa->symbol_set, ent) {
+ const char *ld_name = get_entity_ld_name(ent);
+ be_emit_irprintf(&isa->emit, ".non_lazy_symbol_pointer\n%s:\n\t.indirect_symbol _%s\n\t.long 0\n\n", ld_name, ld_name);
+ be_emit_write_line(&isa->emit);
+ }
+}
/**
* Closes the output file and frees the ISA structure.
*/
static void ppc32_done(void *self) {
+ ppc32_isa_t *isa = self;
+
+ be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+ be_gas_emit_switch_section(&isa->emit, GAS_SECTION_DATA);
+ ppc32_dump_indirect_symbols(isa);
+
+ be_emit_destroy_env(&isa->emit);
+ del_pset(isa->symbol_set);
+
free(self);
}
#include "bearch_ppc32.h"
#include "ppc32_nodes_attr.h"
#include "../be.h"
+#include "../beemitter.h"
+#include "pset.h"
#include "set.h"
typedef struct _ppc32_isa_t ppc32_isa_t;
ir_graph *irg; /**< current irg */
const arch_env_t *arch_env; /**< the arch env */
set *reg_set; /**< set to memorize registers for FIRM nodes (e.g. phi) */
- int emit_decls; /**< flag indicating if decls were already emitted */
ppc32_isa_t *isa; /**< the isa instance */
const be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
unsigned area_size; /**< size of call area for the current irg */
struct _ppc32_isa_t {
- const arch_isa_if_t *impl;
- const arch_register_t *sp; /**< The stack pointer register. */
- const arch_register_t *bp; /**< The base pointer register. */
- const int stack_dir; /**< -1 for decreasing, 1 for increasing. */
- int num_codegens;
- FILE *out; /**< output file */
+ arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
+ be_emit_env_t emit; /**< An emitter environment for the GAS emitter. */
+ pset *symbol_set; /**< A set containing the indirect symbols. */
};
#include "irop_t.h"
#include "irnode_t.h"
#include "irargs_t.h"
+#include "error.h"
#include "../besched_t.h"
#include "../benode_t.h"
#define SNPRINTF_BUF_LEN 128
-static const arch_env_t *arch_env = NULL;
static char printbuf[SNPRINTF_BUF_LEN];
-static char printbuf2[SNPRINTF_BUF_LEN];
extern int isleaf;
* | | | |
* |_| |_|
*************************************************************/
-
-const char *ppc32_rlwimi_emit_helper(const ir_node *n, ppc32_emit_env_t *env) {
- rlwimi_const_t *rlwimi_const = get_ppc32_rlwimi_const(n);
- snprintf(printbuf, SNPRINTF_BUF_LEN, "%i, %i, %i", rlwimi_const->shift,
- rlwimi_const->maskA, rlwimi_const->maskB);
- return printbuf;
-}
-
-
-/**
- * Return a const or symconst as string.
- */
-static const char *node_const_to_str(ir_node *n) {
- const char *buf;
- switch(get_ppc32_type(n))
- {
- case ppc32_ac_Const:
- tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
- buf=printbuf;
- break;
- case ppc32_ac_SymConst:
- buf=get_id_str(get_ppc32_symconst_ident(n));
- break;
- case ppc32_ac_Offset:
- snprintf(printbuf, SNPRINTF_BUF_LEN, "%i", get_ppc32_offset(n));
- return printbuf;
- default:
- assert(0 && "node_const_to_str(): Illegal offset type");
- return 0;
- }
- switch(get_ppc32_offset_mode(n))
- {
- case ppc32_ao_None:
- return buf;
- case ppc32_ao_Lo16:
- snprintf(printbuf2, SNPRINTF_BUF_LEN, "lo16(%s)", buf);
- return printbuf2;
- case ppc32_ao_Hi16:
- snprintf(printbuf2, SNPRINTF_BUF_LEN, "hi16(%s)", buf);
- return printbuf2;
- case ppc32_ao_Ha16:
- snprintf(printbuf2, SNPRINTF_BUF_LEN, "ha16(%s)", buf);
- return printbuf2;
- default:
- assert(0 && "node_const_to_str(): Illegal offset mode");
- return 0;
- }
-}
-
-/**
- * Returns node's offset as string.
- */
-static const char *node_offset_to_str(ir_node *n) {
- const char *buf;
- if(get_ppc32_type(n)==ppc32_ac_None) return "0";
- switch(get_ppc32_type(n))
- {
- case ppc32_ac_Const:
- tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
- buf=printbuf;
- break;
- case ppc32_ac_SymConst:
- buf=get_id_str(get_ppc32_symconst_ident(n));
- break;
- case ppc32_ac_Offset:
- snprintf(printbuf, SNPRINTF_BUF_LEN, "%i", get_ppc32_offset(n));
- return printbuf;
- default:
- assert(0 && "node_offset_to_str(): Illegal offset type");
- return 0;
- }
- switch(get_ppc32_offset_mode(n))
- {
- case ppc32_ao_None:
- return buf;
- case ppc32_ao_Lo16:
- snprintf(printbuf2, SNPRINTF_BUF_LEN, "lo16(%s)", buf);
- return printbuf2;
- case ppc32_ao_Hi16:
- snprintf(printbuf2, SNPRINTF_BUF_LEN, "hi16(%s)", buf);
- return printbuf2;
- case ppc32_ao_Ha16:
- snprintf(printbuf2, SNPRINTF_BUF_LEN, "ha16(%s)", buf);
- return printbuf2;
- default:
- assert(0 && "node_offset_to_str(): Illegal offset mode");
- return 0;
- }
-}
-
-/* We always pass the ir_node which is a pointer. */
-static int ppc32_get_arg_type(const lc_arg_occ_t *occ) {
- return lc_arg_type_ptr;
-}
-
-
/**
* Returns the register at in position pos.
*/
-static const arch_register_t *get_in_reg(ir_node *irn, int pos) {
+static const arch_register_t *get_in_reg(const arch_env_t *arch_env, const ir_node *irn, int pos) {
ir_node *op;
const arch_register_t *reg = NULL;
/**
* Returns the register at out position pos.
*/
-static const arch_register_t *get_out_reg(ir_node *irn, int pos) {
+static const arch_register_t *get_out_reg(const arch_env_t *arch_env, const ir_node *irn, int pos) {
ir_node *proj;
const arch_register_t *reg = NULL;
if (get_irn_mode(irn) != mode_T) {
reg = arch_get_irn_register(arch_env, irn);
- }
- else if (is_ppc32_irn(irn)) {
+ } else if (is_ppc32_irn(irn)) {
reg = get_ppc32_out_reg(irn, pos);
- }
- else {
+ } else {
const ir_edge_t *edge;
foreach_out_edge(irn, edge) {
}
/**
- * Returns the number of the in register at position pos.
+ * Emit the name of the source register at given input position.
*/
-int get_ppc32_reg_nr(ir_node *irn, int pos, int in_out) {
- const arch_register_t *reg;
-
- if (in_out == 1) {
- reg = get_in_reg(irn, pos);
- }
- else {
- reg = get_out_reg(irn, pos);
- }
-
- return arch_register_get_index(reg);
+void ppc32_emit_source_register(ppc32_emit_env_t *env, const ir_node *node, int pos) {
+ const arch_register_t *reg = get_in_reg(env->arch_env, node, pos);
+ be_emit_string(env->emit, arch_register_get_name(reg));
}
/**
- * Returns the name of the in register at position pos.
+ * Emit the name of the destination register at given output position.
*/
-const char *get_ppc32_reg_name(ir_node *irn, int pos, int in_out) {
- const arch_register_t *reg;
+void ppc32_emit_dest_register(ppc32_emit_env_t *env, const ir_node *node, int pos) {
+ const arch_register_t *reg = get_out_reg(env->arch_env, node, pos);
+ be_emit_string(env->emit, arch_register_get_name(reg));
+}
- if (in_out == 1) {
- reg = get_in_reg(irn, pos);
- }
- else {
- reg = get_out_reg(irn, pos);
- }
+void ppc32_emit_rlwimi_helper(ppc32_emit_env_t *env, const ir_node *n) {
+ rlwimi_const_t *rlwimi_const = get_ppc32_rlwimi_const(n);
- return arch_register_get_name(reg);
+ be_emit_irprintf(env->emit, "%i, %i, %i", rlwimi_const->shift,
+ rlwimi_const->maskA, rlwimi_const->maskB);
}
/**
- * Get the register name for a node.
+ * Emit a const or symconst.
*/
-static int ppc32_get_reg_name(lc_appendable_t *app,
- const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
-{
+void ppc32_emit_immediate(ppc32_emit_env_t *env, const ir_node *n) {
const char *buf;
- ir_node *X = arg->v_ptr;
- int nr = occ->width - 1;
-
- if (!X)
- return lc_arg_append(app, occ, "(null)", 6);
- if (occ->conversion == 'S') {
- buf = get_ppc32_reg_name(X, nr, 1);
+ switch (get_ppc32_type(n)) {
+ case ppc32_ac_Const:
+ tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
+ buf = printbuf;
+ break;
+ case ppc32_ac_SymConst:
+ buf = get_id_str(get_ppc32_symconst_ident(n));
+ break;
+ case ppc32_ac_Offset:
+ be_emit_irprintf(env->emit, "%i", get_ppc32_offset(n));
+ return;
+ default:
+ assert(0 && "node_const_to_str(): Illegal offset type");
+ return;
}
- else { /* 'D' */
- buf = get_ppc32_reg_name(X, nr, 0);
+ switch (get_ppc32_offset_mode(n)) {
+ case ppc32_ao_None:
+ be_emit_string(env->emit, buf);
+ return;
+ case ppc32_ao_Lo16:
+ be_emit_irprintf(env->emit, "lo16(%s)", buf);
+ return;
+ case ppc32_ao_Hi16:
+ be_emit_irprintf(env->emit, "hi16(%s)", buf);
+ return;
+ case ppc32_ao_Ha16:
+ be_emit_irprintf(env->emit, "ha16(%s)", buf);
+ return;
+ default:
+ assert(0 && "node_const_to_str(): Illegal offset mode");
+ return;
}
-
-// lc_appendable_chadd(app, '%');
- return lc_arg_append(app, occ, buf, strlen(buf));
}
/**
- * Returns the tarval or offset of an ppc node as a string.
+ * Emits a node's offset.
*/
-static int ppc32_const_to_str(lc_appendable_t *app,
- const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
-{
+void ppc32_emit_offset(ppc32_emit_env_t *env, const ir_node *n) {
const char *buf;
- ir_node *X = arg->v_ptr;
-
- if (!X)
- return lc_arg_append(app, occ, "(null)", 6);
-
- if (occ->conversion == 'C') {
- buf = node_const_to_str(X);
- }
- else { /* 'O' */
- buf = node_offset_to_str(X);
+ if (get_ppc32_type(n) == ppc32_ac_None) {
+ be_emit_char(env->emit, '0');
+ return;
}
- return lc_arg_append(app, occ, buf, strlen(buf));
-}
-
-/**
- * Determines the SSE suffix depending on the mode.
- */
-static int ppc32_get_mode_suffix(lc_appendable_t *app,
- const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
-{
- ir_node *X = arg->v_ptr;
-
- if (!X)
- return lc_arg_append(app, occ, "(null)", 6);
-
- if (get_mode_size_bits(get_irn_mode(X)) == 32)
- return lc_appendable_chadd(app, 's');
- else
- return lc_appendable_chadd(app, 'd');
-}
-
-/**
- * Return the ppc printf arg environment.
- * We use the firm environment with some additional handlers.
- */
-const lc_arg_env_t *ppc32_get_arg_env(void) {
- static lc_arg_env_t *env = NULL;
-
- static const lc_arg_handler_t ppc32_reg_handler = { ppc32_get_arg_type, ppc32_get_reg_name };
- static const lc_arg_handler_t ppc32_const_handler = { ppc32_get_arg_type, ppc32_const_to_str };
- static const lc_arg_handler_t ppc32_mode_handler = { ppc32_get_arg_type, ppc32_get_mode_suffix };
-
- if(env == NULL) {
- /* extend the firm printer */
- env = firm_get_arg_env();
- //lc_arg_new_env();
-
- lc_arg_register(env, "ppc:sreg", 'S', &ppc32_reg_handler);
- lc_arg_register(env, "ppc:dreg", 'D', &ppc32_reg_handler);
- lc_arg_register(env, "ppc:cnst", 'C', &ppc32_const_handler);
- lc_arg_register(env, "ppc:offs", 'O', &ppc32_const_handler);
- lc_arg_register(env, "ppc:mode", 'M', &ppc32_mode_handler);
+ switch (get_ppc32_type(n)) {
+ case ppc32_ac_Const:
+ tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
+ buf = printbuf;
+ break;
+ case ppc32_ac_SymConst:
+ buf = get_id_str(get_ppc32_symconst_ident(n));
+ break;
+ case ppc32_ac_Offset:
+ be_emit_irprintf(env->emit, "%i", get_ppc32_offset(n));
+ return;
+ default:
+ assert(0 && "node_offset_to_str(): Illegal offset type");
+ return;
+ }
+ switch (get_ppc32_offset_mode(n)) {
+ case ppc32_ao_None:
+ be_emit_string(env->emit, buf);
+ return;
+ case ppc32_ao_Lo16:
+ be_emit_irprintf(env->emit, "lo16(%s)", buf);
+ return;
+ case ppc32_ao_Hi16:
+ be_emit_irprintf(env->emit, "hi16(%s)", buf);
+ return;
+ case ppc32_ao_Ha16:
+ be_emit_irprintf(env->emit, "ha16(%s)", buf);
+ return;
+ default:
+ assert(0 && "node_offset_to_str(): Illegal offset mode");
+ return;
}
-
- return env;
}
/**
/**
* Emits code for a unconditional jump.
*/
-static void emit_Jmp(const ir_node *irn, ppc32_emit_env_t *env) {
- FILE *F = env->out;
- ir_node *block;
+static void emit_Jmp(ppc32_emit_env_t *env, const ir_node *irn) {
+ ir_node *block = get_nodes_block(irn);
- block = get_nodes_block(irn);
- if(get_irn_link(irn) != get_irn_link(block))
- ir_fprintf(F, "\tb %s\t\t\t/* Branch(%+F) */\n", get_cfop_target(irn, printbuf), get_irn_link(irn));
- else
- ir_fprintf(F, "\t\t\t\t\t\t/* fallthrough(%+F) */\n", get_irn_link(irn));
+ if (get_irn_link(irn) != get_irn_link(block)) {
+ be_emit_irprintf(env->emit, "\tb %s", get_cfop_target(irn, printbuf));
+ } else {
+ be_emit_irprintf(env->emit, "/* fallthrough(%+F) */", get_irn_link(irn));
+ }
+ be_emit_finish_line_gas(env->emit, irn);
}
/**
* Emits code for a call
*/
-static void emit_be_Call(const ir_node *irn, ppc32_emit_env_t *env) {
- FILE *F = env->out;
+static void emit_be_Call(ppc32_emit_env_t *env, const ir_node *irn) {
ir_entity *call_ent = be_Call_get_entity(irn);
- if(call_ent)
- {
- ir_fprintf(F, "\tbl %s\t\t\t/* Branch and link(%+F) */\n", get_entity_name(call_ent), irn);
- }
- else
- {
- ir_node *node = get_irn_n(irn, be_pos_Call_ptr);
- lc_efprintf(ppc32_get_arg_env(), F, "\tmtlr %1D\t\t\t/* Move to link register */\n", node);
- ir_fprintf(F, "\tblrl\t\t\t/* Branch to link register and link(%+F) */\n", irn);
- }
+ if (call_ent) {
+ mark_entity_visited(call_ent);
+ be_emit_irprintf(env->emit, "\tbl %s", get_entity_ld_name(call_ent));
+ } else {
+ be_emit_cstring(env->emit, "\tmtlr ");
+ ppc32_emit_source_register(env, irn, be_pos_Call_ptr);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Move to link register and link */\n");
+ be_emit_write_line(env->emit);
+ be_emit_cstring(env->emit, "\tblrl");
+ }
+ be_emit_finish_line_gas(env->emit, irn);
}
-char *branchops[8] = { 0, "beq", "blt", "ble", "bgt", "bge", "bne", "b" };
-
-static void emit_ppc32_Branch(const ir_node *n, ppc32_emit_env_t *env) {
- FILE *F = env->out;
- int projnum = get_ppc32_proj_nr(n);
+static void emit_ppc32_Branch(ppc32_emit_env_t *env, const ir_node *irn) {
+ static const char *branchops[8] = { 0, "beq", "blt", "ble", "bgt", "bge", "bne", "b" };
+ int projnum = get_ppc32_proj_nr(irn);
- const ir_edge_t *edge = get_irn_out_edge_first(n);
+ const ir_edge_t *edge = get_irn_out_edge_first(irn);
ir_node *proj = get_edge_src_irn(edge);
int opind;
- if(get_Proj_proj(proj) == pn_Cond_true)
+ if (get_Proj_proj(proj) == pn_Cond_true)
opind = projnum;
else
- opind = 7-projnum;
+ opind = 7 - projnum;
assert(opind>=0 && opind<8);
- if(opind)
- {
+ if (opind){
get_cfop_target(proj, printbuf);
- lc_efprintf(ppc32_get_arg_env(), F, "\t%-8s%1S, %s\t\t\t/* Branch(%1S) to %s */\n",
- branchops[opind], n, printbuf, n, printbuf);
+ be_emit_irprintf(env->emit, "\t%8s", branchops[opind]);
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ be_emit_string(env->emit, printbuf);
+ be_emit_finish_line_gas(env->emit, irn);
}
- edge = get_irn_out_edge_next(n, edge);
-
- if(edge)
- {
- ir_node *irn = get_edge_src_irn(edge);
- lc_efprintf(ppc32_get_arg_env(), F, "\tb %s\t\t\t/* Branch(%+F) */\n",
- get_cfop_target(irn, printbuf), get_irn_link(irn));
+ edge = get_irn_out_edge_next(irn, edge);
+ if (edge) {
+ ir_node *blk = get_edge_src_irn(edge);
+ be_emit_cstring(env->emit, "\tb ");
+ be_emit_string(env->emit, get_cfop_target(blk, printbuf));
+ be_emit_finish_line_gas(env->emit, irn);
}
}
-static void emit_ppc32_LoopCopy(const ir_node *n, ppc32_emit_env_t *env) {
- FILE *F = env->out;
- fprintf(F, "LOOP_%ld:\n", get_irn_node_nr(n));
- lc_efprintf(ppc32_get_arg_env(), F, "\tlwzu %5D, 4(%2S)\t\t\t/* Load with update */\n",n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tstwu %5D, 4(%3S)\t\t\t/* Store with update */\n",n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tbdnz LOOP_%i\t\t\t/* Branch with decrement if CTR != 0 */\n",
- get_irn_node_nr(n));
+static void emit_ppc32_LoopCopy(ppc32_emit_env_t *env, const ir_node *irn) {
+ be_emit_irprintf(env->emit, "LOOP_%ld:\n", get_irn_node_nr(irn));
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tlwzu ");
+ ppc32_emit_dest_register(env, irn, 4);
+ be_emit_cstring(env->emit, ", 4(");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_char(env->emit, ')');
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Load with update */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tstwu ");
+ ppc32_emit_dest_register(env, irn, 4);
+ be_emit_cstring(env->emit, ", 4(");
+ ppc32_emit_source_register(env, irn, 2);
+ be_emit_char(env->emit, ')');
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Store with update */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_irprintf(env->emit, "\tbdnz LOOP_%i", get_irn_node_nr(irn));
+ be_emit_finish_line_gas(env->emit, irn);
}
-static void emit_ppc32_Switch(const ir_node *n, ppc32_emit_env_t *env) {
- FILE *F = env->out;
- ir_node *proj,*defproj=NULL;
+static void emit_ppc32_Switch(ppc32_emit_env_t *env, const ir_node *irn) {
+ ir_node *proj, *defproj = NULL;
int pn;
const ir_edge_t* edge;
- foreach_out_edge(n, edge) {
+ foreach_out_edge(irn, edge) {
proj = get_edge_src_irn(edge);
assert(is_Proj(proj) && "Only proj allowed at Switch");
- if(get_irn_mode(proj) != mode_X) continue;
+ if (get_irn_mode(proj) != mode_X) continue;
pn = get_Proj_proj(proj);
/* check for default proj */
- if (pn == get_ppc32_proj_nr(n)) {
+ if (pn == get_ppc32_proj_nr(irn)) {
assert(defproj == NULL && "found two defProjs at Switch");
defproj = proj;
- }
- else
- {
-
- lc_efprintf(ppc32_get_arg_env(), F, "\taddis %2S, 0, hi16(%i)\t\t\t/* Load upper immediate */\n",n,pn);
- lc_efprintf(ppc32_get_arg_env(), F, "\tori %2S, %2S, lo16(%i)\t\t\t/* Load lower immediate */\n",n,n,pn);
- lc_efprintf(ppc32_get_arg_env(), F, "\tcmp %3S, %1S, %2S\t\t\t/* Compare */\n",n,n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tbeq %3S, %s\t\t\t/* Branch if equal */\n",
- n,get_cfop_target(proj, printbuf));
+ } else {
+ be_emit_cstring(env->emit, "\taddis ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_irprintf(env->emit, ", 0, hi16(%i)", pn);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Load upper immediate */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tori ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_irprintf(env->emit, ", lo16(%i)", pn);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Load lower immediate */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tcmp ");
+ ppc32_emit_source_register(env, irn, 2);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Compare */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tbeq ");
+ ppc32_emit_source_register(env, irn, 2);
+ be_emit_irprintf(env->emit, ", %s", get_cfop_target(proj, printbuf));
+ be_emit_cstring(env->emit, "/* Branch if equal */\n");
+ be_emit_write_line(env->emit);
}
}
assert(defproj != NULL && "didn't find defProj at Switch");
- lc_efprintf(ppc32_get_arg_env(), F, "\tb %s\t\t\t/* Default case */\n", get_cfop_target(defproj, printbuf));
+ be_emit_irprintf(env->emit, "\tb %s", get_cfop_target(defproj, printbuf));
+ be_emit_finish_line_gas(env->emit, irn);
}
/**
* Emits code for a backend Copy node
*/
-static void emit_be_Copy(const ir_node *n, ppc32_emit_env_t *env) {
- FILE *F = env->out;
- const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, n, 0);
-
- if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
- {
- lc_efprintf(ppc32_get_arg_env(), F, "\tmr %1D, %1S\t\t\t/* Move register */\n",n,n);
- }
- else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
- {
- lc_efprintf(ppc32_get_arg_env(), F, "\tfmr %1D, %1S\t\t\t/* Move register */\n",n,n);
- }
- else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition])
- {
- lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf %1D, %1S\t\t\t/* Move register */\n",n,n);
- }
- else assert(0 && "Illegal register class for Copy");
+static void emit_be_Copy(ppc32_emit_env_t *env,const ir_node *irn) {
+ const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, irn, 0);
+
+ if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
+ be_emit_cstring(env->emit, "\tmr ");
+ } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
+ be_emit_cstring(env->emit, "\tfmr ");
+ } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
+ be_emit_cstring(env->emit, "\tmcrf ");
+ } else {
+ assert(0 && "Illegal register class for Copy");
+ panic("ppc32 Emitter: Illegal register class for Copy");
+ }
+ ppc32_emit_dest_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_finish_line_gas(env->emit, irn);
}
/**
* Emits code for a backend Perm node
*/
-static void emit_be_Perm(const ir_node *n, ppc32_emit_env_t *env) {
- FILE *F = env->out;
- const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, n, 0);
-
- if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
- {
- lc_efprintf(ppc32_get_arg_env(), F, "\txor %1S, %1S, %2S\t\t\t/* Swap %1S, %2S with XOR */\n",n,n,n,n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\txor %2S, %1S, %2S\t\t\t/* (continued) */\n",n,n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\txor %1S, %1S, %2S\t\t\t/* (continued) */\n",n,n,n);
- }
- else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
- {
- lc_efprintf(ppc32_get_arg_env(), F, "\tfmr f0, %1S\t\t\t/* Swap %1S, %2S with moves */\n",n,n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tfmr %1S, %2S\t\t\t/* (continued) */\n",n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tfmr %2S, f0\t\t\t/* (continued) */\n",n);
- }
- else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition])
- {
- lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf cr7, %1S\t\t\t/* Swap %1S, %2S with moves */\n",n,n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf %1S, %2S\t\t\t/* (continued) */\n",n,n);
- lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf %2S, cr7\t\t\t/* (continued) */\n",n);
- }
- else assert(0 && "Illegal register class for Perm");
-
+static void emit_be_Perm(ppc32_emit_env_t *env, const ir_node *irn) {
+ const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, irn, 0);
+
+ if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
+ be_emit_cstring(env->emit, "\txor ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Swap with XOR */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\txor ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* (continued) */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\txor ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
+ be_emit_cstring(env->emit, "\tfmr f0, ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Swap with moves */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tfmr ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* (continued) */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tfmr ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_cstring(env->emit, ", f0");
+ } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
+ be_emit_cstring(env->emit, "\tmcrf cr7, ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* Swap with moves */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tmcrf ");
+ ppc32_emit_source_register(env, irn, 0);
+ be_emit_cstring(env->emit, ", ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_pad_comment(env->emit);
+ be_emit_cstring(env->emit, "/* (continued) */\n");
+ be_emit_write_line(env->emit);
+
+ be_emit_cstring(env->emit, "\tmcrf ");
+ ppc32_emit_source_register(env, irn, 1);
+ be_emit_cstring(env->emit, ", cr7");
+ } else {
+ assert(0 && "Illegal register class for Perm");
+ panic("ppc32 Emitter: Illegal register class for Perm");
+ }
+ be_emit_finish_line_gas(env->emit, irn);
}
/**
* Emits code for a proj -> node
*/
-static void emit_Proj(const ir_node *irn, ppc32_emit_env_t *env) {
+static void emit_Proj(ppc32_emit_env_t *env, const ir_node *irn) {
ir_node *pred = get_Proj_pred(irn);
if (get_irn_op(pred) == op_Start) {
- switch(get_Proj_proj(irn)) {
- case pn_Start_X_initial_exec:
- emit_Jmp(irn, env);
- break;
- default:
- break;
+ if (get_Proj_proj(irn) == pn_Start_X_initial_exec) {
+ emit_Jmp(env, irn);
}
}
}
-static void emit_be_IncSP(const ir_node *irn, ppc32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
+static void emit_be_IncSP(ppc32_emit_env_t *env, const ir_node *irn) {
int offs = be_get_IncSP_offset(irn);
- fprintf(F, "\t\t\t\t\t/* ignored IncSP with %d */\n", -offs);
+ be_emit_irprintf(env->emit, "\t/* ignored IncSP with %d */", -offs);
+ be_emit_finish_line_gas(env->emit, irn);
// if (offs) {
// assert(offs<=0x7fff);
* |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
*
***********************************************************************************/
+/**
+ * The type of a emitter function.
+ */
+typedef void (emit_func)(ppc32_emit_env_t *env, const ir_node *irn);
+
+/**
+ * Set a node emitter. Make it a bit more type safe.
+ */
+static INLINE void set_emitter(ir_op *op, emit_func ppc32_emit_node) {
+ op->ops.generic = (op_func)ppc32_emit_node;
+}
static void ppc32_register_emitters(void) {
/* first clear generic function pointers */
/* register generated emitter functions */
ppc32_register_spec_emitters();
-#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
-
- EMIT(ppc32_Branch);
- EMIT(ppc32_LoopCopy);
- EMIT(ppc32_Switch);
- EMIT(be_Call);
- EMIT(Jmp);
- EMIT(Proj);
- EMIT(be_IncSP);
- EMIT(be_Copy);
- EMIT(be_Perm);
-// EMIT(Spill);
-// EMIT(Reload);
+ set_emitter(op_ppc32_Branch, emit_ppc32_Branch);
+ set_emitter(op_ppc32_LoopCopy, emit_ppc32_LoopCopy);
+ set_emitter(op_ppc32_Switch, emit_ppc32_Switch);
+ set_emitter(op_be_Call, emit_be_Call);
+ set_emitter(op_Jmp, emit_Jmp);
+ set_emitter(op_Proj, emit_Proj);
+ set_emitter(op_be_IncSP, emit_be_IncSP);
+ set_emitter(op_be_Copy, emit_be_Copy);
+ set_emitter(op_be_Perm, emit_be_Perm);
+// set_emitter(op_Spill, emit_Spill);
+// set_emitter(op_Reload, emit_Reload);
}
/**
* Emits code for a node.
*/
-static void ppc32_emit_node(ir_node *irn, void *env) {
- ppc32_emit_env_t *emit_env = env;
- FILE *F = emit_env->out;
- ir_op *op = get_irn_op(irn);
- DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
-
- DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
+static void ppc32_emit_node(ppc32_emit_env_t *env, const ir_node *irn) {
+ ir_op *op = get_irn_op(irn);
if (op->ops.generic) {
- void (*emit)(ir_node *, void *) = (void (*)(ir_node *, void *))op->ops.generic;
- (*emit)(irn, env);
- }
- else {
- ir_fprintf(F, "\t\t\t\t\t/* %+F */\n", irn);
+ emit_func *emit = (emit_func *)op->ops.generic;
+ (*emit)(env, irn);
+ } else {
+ be_emit_cstring(env->emit, "\t/* TODO */");
+ be_emit_finish_line_gas(env->emit, irn);
}
}
* Walks over the nodes in a block connected by scheduling edges
* and emits code for each node.
*/
-static void ppc32_gen_block(ir_node *block, void *env) {
+static void ppc32_gen_block(ppc32_emit_env_t *env, const ir_node *block) {
ir_node *irn;
if (! is_Block(block))
return;
- fprintf(((ppc32_emit_env_t *)env)->out, "BLOCK_%ld:\n", get_irn_node_nr(block));
+ be_emit_irprintf(env->emit, "BLOCK_%ld:\n", get_irn_node_nr(block));
+ be_emit_write_line(env->emit);
sched_foreach(block, irn) {
- ppc32_emit_node(irn, env);
+ ppc32_emit_node(env, irn);
}
}
/**
* Emits code for function start.
*/
-void ppc32_emit_start(FILE *F, ir_graph *irg, ppc32_emit_env_t *env) {
+static void ppc32_emit_start(ppc32_emit_env_t *env, ir_graph *irg) {
const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
int framesize = get_type_size_bytes(get_irg_frame_type(env->cg->irg));
- if(! strcmp(irg_name, "main")) // XXX: underscore hack
- {
- fprintf(F, "\t.text\n");
- fprintf(F, "\t.globl _main\n");
- fprintf(F, "\t.align 4\n");
- fprintf(F, "_main:\n");
- }
- else
- {
- fprintf(F, "\t.text\n");
- fprintf(F, "\t.globl %s\n", irg_name);
- fprintf(F, "\t.align 4\n");
- fprintf(F, "%s:\n", irg_name);
+ if(! strcmp(irg_name, "main")) { // XXX: underscore hack
+ irg_name = "_main";
}
- if(framesize > 24)
- {
- fprintf(F, "\tmflr r0\n");
- fprintf(F, "\tstw r0, 8(r1)\n");
- fprintf(F, "\tstwu r1, -%i(r1)\n", framesize);
- }
- else
- {
- fprintf(F, "\t\t\t\t\t/* set new frame (%d) omitted */\n", framesize);
- }
+ be_emit_irprintf(env->emit, "\t.text\n\t.globl %s\n\t.align 4\n%s:\n", irg_name, irg_name);
+ if (framesize > 24) {
+ be_emit_cstring(env->emit, "\tmflr r0\n");
+ be_emit_cstring(env->emit, "\tstw r0, 8(r1)\n");
+ be_emit_irprintf(env->emit, "\tstwu r1, -%i(r1)\n", framesize);
+ } else {
+ be_emit_irprintf(env->emit, "\t/* set new frame (%d) omitted */\n", framesize);
+ }
+ be_emit_write_line(env->emit);
-/* if(!isleaf)
- {
+/* if(!isleaf) {
// store link register in linkage area (TODO: if needed)
- fprintf(F, "\tmflr r0\n");
- fprintf(F, "\tstwu r0, -4(r1)\n"); // stw r0, 8(SP)
+ be_emit_cstring(env->emit, "\tmflr r0\n");
+ be_emit_cstring(env->emit, "\tstwu r0, -4(r1)\n"); // stw r0, 8(SP)
+ be_emit_write_line(env->emit);
}*/
}
/**
* Emits code for function end
*/
-void ppc32_emit_end(FILE *F, ir_graph *irg, ppc32_emit_env_t *env) {
+static void ppc32_emit_end(ppc32_emit_env_t *env, ir_graph *irg) {
int framesize = get_type_size_bytes(get_irg_frame_type(env->cg->irg));
-/* if(!isleaf)
- {
+/* if(!isleaf) {
// restore link register
- fprintf(F, "\tlwz r0, 0(r1)\n");
- fprintf(F, "\taddi r1, r1, 4\n");
- fprintf(F, "\tmtlr r0\n");
+ be_emit_cstring(env->emit, "\tlwz r0, 0(r1)\n");
+ be_emit_cstring(env->emit, "\taddi r1, r1, 4\n");
+ be_emit_cstring(env->emit, "\tmtlr r0\n");
+ be_emit_write_line(env->emit);
}*/
- if(framesize > 24)
- {
- fprintf(F, "\tlwz r1, 0(r1)\n");
- fprintf(F, "\tlwz r0, 8(r1)\n");
- fprintf(F, "\tmtlr r0\n");
- }
- fprintf(F, "\tblr\n\n");
+ if(framesize > 24) {
+ be_emit_cstring(env->emit, "\tlwz r1, 0(r1)\n");
+ be_emit_cstring(env->emit, "\tlwz r0, 8(r1)\n");
+ be_emit_cstring(env->emit, "\tmtlr r0\n");
+ be_emit_write_line(env->emit);
+ }
+ be_emit_cstring(env->emit, "\tblr\n\n");
+ be_emit_write_line(env->emit);
}
/**
/**
* Main driver: generates code for one routine
*/
-void ppc32_gen_routine(FILE *F, ir_graph *irg, const ppc32_code_gen_t *cg) {
+void ppc32_gen_routine(const ppc32_code_gen_t *cg, ir_graph *irg)
+{
ppc32_emit_env_t emit_env;
ir_node *block;
int i, n;
- emit_env.out = F;
+ emit_env.emit = &cg->isa->emit;
emit_env.arch_env = cg->arch_env;
emit_env.cg = cg;
FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ppc.emit");
- /* set the global arch_env (needed by print hooks) */
- arch_env = cg->arch_env;
-
ppc32_register_emitters();
- ppc32_emit_start(F, irg, &emit_env);
+ ppc32_emit_start(&emit_env, irg);
irg_block_walk_graph(irg, ppc32_gen_labels, NULL, &emit_env);
n = ARR_LEN(cg->blk_sched);
/* set here the link. the emitter expects to find the next block here */
set_irn_link(block, next_bl);
- ppc32_gen_block(block, &emit_env);
+ ppc32_gen_block(&emit_env, block);
}
- ppc32_emit_end(F, irg, &emit_env);
+ ppc32_emit_end(&emit_env, irg);
}
#ifndef FIRM_BE_PPC32_PPC32_EMITTER_H
#define FIRM_BE_PPC32_PPC32_EMITTER_H
+#include "firm_types.h"
#include "irargs_t.h" // this also inlucdes <libcore/lc_print.h>
-#include "irnode.h"
#include "debug.h"
#include "../bearch_t.h"
#include "bearch_ppc32_t.h"
typedef struct _emit_env_t {
- FILE *out;
- const arch_env_t *arch_env;
- const ppc32_code_gen_t *cg;
+ be_emit_env_t *emit; /**< environment for the generic GAS emitter. */
+ const arch_env_t *arch_env; /**< the architecture environment */
+ const ppc32_code_gen_t *cg; /**< the code generator object */
DEBUG_ONLY(firm_dbg_module_t *mod;)
} ppc32_emit_env_t;
-const lc_arg_env_t *ppc32_get_arg_env(void);
-
-void equalize_dest_src(FILE *F, ir_node *n);
-
-int get_ppc32_reg_nr(ir_node *irn, int posi, int in_out);
-const char *get_ppc32_in_reg_name(ir_node *irn, int pos);
-
-void ppc32_gen_routine(FILE *F, ir_graph *irg, const ppc32_code_gen_t *cg);
-
-const char *ppc32_rlwimi_emit_helper(const ir_node *n, ppc32_emit_env_t *env);
+void ppc32_gen_routine(const ppc32_code_gen_t *cg, ir_graph *irg);
+void ppc32_emit_source_register(ppc32_emit_env_t *env, const ir_node *node, int pos);
+void ppc32_emit_dest_register(ppc32_emit_env_t *env, const ir_node *node, int pos);
+void ppc32_emit_offset(ppc32_emit_env_t *env, const ir_node *n);
+void ppc32_emit_immediate(ppc32_emit_env_t *env, const ir_node *n);
+void ppc32_emit_rlwimi_helper(ppc32_emit_env_t *env, const ir_node *n);
#endif
# the cpu architecture (ia32, ia64, mips, sparc, ppc32, ...)
$arch = "ppc32";
+$new_emit_syntax = 1;
# this strings mark the beginning and the end of a comment in emit
$comment_string = "/*";
]
); # %reg_classes
+%emit_templates = (
+ S1 => "${arch}_emit_source_register(env, node, 0);",
+ S2 => "${arch}_emit_source_register(env, node, 1);",
+ S3 => "${arch}_emit_source_register(env, node, 2);",
+ D1 => "${arch}_emit_dest_register(env, node, 0);",
+ D2 => "${arch}_emit_dest_register(env, node, 1);",
+ D3 => "${arch}_emit_dest_register(env, node, 2);",
+ O => "${arch}_emit_offset(env, node);",
+ C => "${arch}_emit_immediate(env, node);",
+ RLWIMI => "${arch}_emit_rlwimi_helper(env, node);",
+);
+
#--------------------------------------------------#
# _ #
# (_) #
"irn_flags" => "R",
"comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. add %D1, %S1, %S2 /* Add(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. add %D1, %S1, %S2',
},
"Addi" => {
"comment" => "construct Add: Addi(a, const) = Addi(const, a) = a + const",
"reg_req" => { "in" => [ "!r0" ], "out" => [ "gp" ] },
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. addi %D1, %S1, %C /* Addi(%S1, %C) -> %D1, (%A1, const) */',
+ "emit" => '. addi %D1, %S1, %C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "construct Mul: Mullw(a, b) = Mullw(b, a) = lo32(a * b)",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. mullw %D1, %S1, %S2 /* Mullw(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. mullw %D1, %S1, %S2',
},
"Mulhw" => {
"irn_flags" => "R",
"comment" => "construct Mul: Mulhw(a, b) = Mulhw(b, a) = hi32(a * b)",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. mulhw %D1, %S1, %S2 /* Mulhw(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. mulhw %D1, %S1, %S2',
},
"Mulhwu" => {
"irn_flags" => "R",
"comment" => "construct Mul: Mulhwu(a, b) = Mulhwu(b, a) = hi32(a * b)",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. mulhwu %D1, %S1, %S2 /* Mulhwu(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. mulhwu %D1, %S1, %S2',
},
#"Mul_i" => {
# "irn_flags" => "R",
# "comment" => "construct Mul: Mul(a, const) = Mul(const, a) = a * const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. mul %S1, %C, %D1 /* signed Mul(%C, %S1) -> %D1, (%A1, const) */',
+# "emit" => '. mul %S1, %C, %D1',
#},
"And" => {
"irn_flags" => "R",
"comment" => "construct And: And(a, b) = And(b, a) = a AND b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. and %D1, %S1, %S2 /* And(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. and %D1, %S1, %S2',
},
#"And_i" => {
# "irn_flags" => "R",
# "comment" => "construct And: And(a, const) = And(const, a) = a AND const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. and %S1, %C, %D1 /* And(%C, %S1) -> %D1, (%A1, const) */',
+# "emit" => '. and %S1, %C, %D1',
#},
"Or" => {
"irn_flags" => "R",
"comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. or %D1, %S1, %S2 /* Or(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. or %D1, %S1, %S2',
},
#"Or_i" => {
# "irn_flags" => "R",
# "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. or %S1, %C, %D1 /* Or(%C, %S1) -> %D1, (%A1, const) */',
+# "emit" => '. or %S1, %C, %D1',
#},
"Xor" => {
"irn_flags" => "R",
"comment" => "construct Xor: Xor(a, b) = Xor(b, a) = a XOR b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. xor %D1, %S1, %S2 /* Xor(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. xor %D1, %S1, %S2',
},
#"Xor_i" => {
# "irn_flags" => "R",
# "comment" => "construct Xor: Xor(a, const) = Xor(const, a) = a EOR const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. xor %S1, %C, %D1 /* Xor(%C, %S1) -> %D1, (%A1, const) */',
+# "emit" => '. xor %S1, %C, %D1',
#},
# not commutative operations
"irn_flags" => "R",
"comment" => "construct Sub: Sub(a, b) = a - b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. sub %D1, %S1, %S2 /* Sub(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. sub %D1, %S1, %S2',
},
#"Sub_i" => {
# "irn_flags" => "R",
# "comment" => "construct Sub: Sub(a, const) = a - const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. subl %S1, %C, %D1 /* Sub(%S1, %C) -> %D1, (%A1, const) */',
+# "emit" => '. subl %S1, %C, %D1',
#},
"Slw" => {
"irn_flags" => "R",
"comment" => "construct Shl: Shl(a, b) = a << b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. slw %D1, %S1, %S2 /* Shl(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. slw %D1, %S1, %S2',
},
#"Shl_i" => {
# "irn_flags" => "R",
# "comment" => "construct Shl: Shl(a, const) = a << const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. shl %S1, %C, %D1 /* Shl(%S1, %C) -> %D1, (%A1, const) */',
+# "emit" => '. shl %S1, %C, %D1',
#},
"Srw" => {
"irn_flags" => "R",
"comment" => "construct Shr: Srw(a, b): c = a >> b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. srw %D1, %S1, %S2 /* Srw(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. srw %D1, %S1, %S2',
},
#"Shr_i" => {
# "irn_flags" => "R",
# "comment" => "construct Shr: Shr(a, const) = a >> const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. shr %S1, %C, %D1 /* Shr(%S1, %C) -> %D1, (%A1, const) */',
+# "emit" => '. shr %S1, %C, %D1',
#},
"Sraw" => {
"irn_flags" => "R",
"comment" => "construct Shrs: Sraw(a, b): c = a >> b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. sraw %D1, %S1, %S2 /* Sraw(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. sraw %D1, %S1, %S2',
},
"Srawi" => {
"irn_flags" => "R",
"comment" => "construct Shrs: Srawi(a, const): c = a >> const",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. sraw %D1, %S1, %C /* Sraw(%S1, %C) -> %D1, (%A1, const) */',
+ "emit" => '. sraw %D1, %S1, %C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "construct ???: Rlwnm(a, b): c = a ROTL b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. rlwnm %D1, %S1, %S2 /* Rlwnm(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. rlwnm %D1, %S1, %S2',
},
"Rlwinm" => {
"irn_flags" => "R",
"comment" => "construct ???: Rlwinm(a, b_const, c_const, d_const): (m = MASK(c, d)) e = (a ROTL b) & m",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. rlwinm %D1, %S1, %ppc32_rlwimi_emit_helper /* Rlwinm(%S1, %ppc32_rlwimi_emit_helper) -> %D1, (%A1) */',
+ "emit" => '. rlwinm %D1, %S1, %RLWIMI',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "construct Minus: Neg(a) = -a",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. neg %D1, %S1 /* Neg(%S1) -> %D1, (%A1) */',
+ "emit" => '. neg %D1, %S1',
},
"Not" => {
"irn_flags" => "R",
"comment" => "construct Not: Not(a) = !a",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. nor %D1, %S1, %S1 /* Not(%S1) -> %D1, (%A1) */',
+ "emit" => '. nor %D1, %S1, %S1',
},
"Extsb" => {
"irn_flags" => "R",
"comment" => "construct Sign extension of byte: Extsb(char a) = (int) a",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. extsb %D1, %S1 /* Extsb(%S1) -> %D1, (%A1) */',
+ "emit" => '. extsb %D1, %S1',
},
"Extsh" => {
"irn_flags" => "R",
"comment" => "construct Sign extension of halfword: Extsh(char a) = (short) a",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. extsh %D1, %S1 /* Extsh(%S1) -> %D1, (%A1) */',
+ "emit" => '. extsh %D1, %S1',
},
"Divw" => {
"irn_flags" => "R",
"comment" => "construct Div (signed): Div(a, b) = a div b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. divw %D1, %S1, %S2 /* Div(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. divw %D1, %S1, %S2',
},
"Divwu" => {
"irn_flags" => "R",
"comment" => "construct Div (unsigned): Div(a, b) = a div b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. divwu %D1, %S1, %S2 /* Div(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. divwu %D1, %S1, %S2',
},
"Mtctr" => {
"irn_flags" => "R",
"comment" => "construct Mtctr: Ctr = a",
"reg_req" => { "in" => [ "gp" ], "out" => [ "count" ] },
- "emit" => '. mtctr %S1 /* Mtctr(%S1) -> %D1, (%A1) */',
+ "emit" => '. mtctr %S1',
},
"irn_flags" => "R",
"comment" => "load constant (16bit with sign extension)",
"reg_req" => { "out" => [ "gp" ] },
- "emit" => '. addi %D1, 0, %C /* lower 16 bit of %C (sign extended) -> %D1 */',
+ "emit" => '. addi %D1, 0, %C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "load the constant to higher 16 bit of register",
"reg_req" => { "out" => [ "gp" ] },
- "emit" => '. addis %D1, 0, %C /* %C << 16 -> %D1 */',
+ "emit" => '. addis %D1, 0, %C',
"attr" => "ppc32_attr_offset_mode om, tarval *tv, ident *id",
"init_attr" =>
'
"irn_flags" => "R",
"comment" => "ors constant with register",
"reg_req" => { "in" => [ "gp"], "out" => [ "gp" ] },
- "emit" => '. ori %D1, %S1, %C /* Ori(%S1,%C) -> %D1 */',
+ "emit" => '. ori %D1, %S1, %C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "ands constant with register with cr0 update",
"reg_req" => { "in" => [ "gp"], "out" => [ "gp", "cr0" ] },
- "emit" => '. andi. %D1, %S1,%C /* Andi(%S1,%C) -> %D1 (%D2 changed) */',
+ "emit" => '. andi. %D1, %S1,%C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "construct Cmp: Cmp(a, b) = Flags in crX",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "condition" ] },
- "emit" => '. cmp %D1, 0, %S1, %S2 /* Cmp(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. cmp %D1, 0, %S1, %S2',
},
"Cmpi" => {
"irn_flags" => "R",
"comment" => "construct Cmp immediate: Cmpi(a, const) = Flags in crX",
"reg_req" => { "in" => [ "gp" ], "out" => [ "condition" ] },
- "emit" => '. cmpi %D1, 0, %S1, %C /* Cmpi(%S1, %C) -> %D1, (%A1) */',
+ "emit" => '. cmpi %D1, 0, %S1, %C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "construct Cmp logical: Cmpl(a, b) = Flags in crX",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "condition" ] },
- "emit" => '. cmpl %D1, 0, %S1, %S2 /* Cmpl(%S1, %S2) -> %D1, (%A1, %A2) */',
+ "emit" => '. cmpl %D1, 0, %S1, %S2',
},
"Cmpli" => {
"irn_flags" => "R",
"comment" => "construct Cmp logical immediate: Cmpli(a, const) = Flags in crX",
"reg_req" => { "in" => [ "gp" ], "out" => [ "condition" ] },
- "emit" => '. cmpli %D1, 0, %S1, %C /* Cmpli(%S1, %C) -> %D1, (%A1) */',
+ "emit" => '. cmpli %D1, 0, %S1, %C',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Load (byte unsigned): Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. lbz %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
+ "emit" => '. lbz %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Load (halfword unsigned): Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. lhz %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
+ "emit" => '. lhz %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Load (halfword signed): Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. lha %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
+ "emit" => '. lha %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Load (word): Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. lwz %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, (%A1) */',
+ "emit" => '. lwz %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Load with update (word): Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "gp", "in_r1", "none"] },
- "emit" => '. lwzu %D1, %O(%S1) /* Load(%O(%S1)) -> %D1, %S1 += %O, (%A1) */',
+ "emit" => '. lwzu %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Store: Store (byte) (ptr, val, mem) = ST ptr,val",
"reg_req" => { "in" => [ "!r0", "gp", "none" ] },
- "emit" => '. stb %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "emit" => '. stb %S2, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Store: Store (halfword) (ptr, val, mem) = ST ptr,val",
"reg_req" => { "in" => [ "!r0", "gp", "none" ] },
- "emit" => '. sth %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "emit" => '. sth %S2, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Store: Store (word) (ptr, val, mem) = ST ptr,val",
"reg_req" => { "in" => [ "!r0", "gp", "none" ] },
- "emit" => '. stw %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "emit" => '. stw %S2, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"irn_flags" => "R",
"comment" => "construct FP Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fadd %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */',
+ "emit" => '. fadd %D1, %S1, %S2',
},
"fAdds" => {
"irn_flags" => "R",
"comment" => "construct FP Add (single): Add(a, b) = Add(b, a) = a + b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fadds %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */',
+ "emit" => '. fadds %D1, %S1, %S2',
},
"fMul" => {
"op_flags" => "C",
"comment" => "construct FP Mul: Mul(a, b) = Mul(b, a) = a * b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fmul %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */',
+ "emit" => '. fmul %D1, %S1, %S2',
},
"fMuls" => {
"op_flags" => "C",
"comment" => "construct FP Mul (single): Mul(a, b) = Mul(b, a) = a * b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fmuls %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */',
+ "emit" => '. fmuls %D1, %S1, %S2',
},
"fNeg" => {
"comment" => "construct FP Negation: fNeg(a) = -a",
"reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
- "emit" => '. fneg %D1, %S1 /* FP fNeg(%S1) -> %D1 */',
+ "emit" => '. fneg %D1, %S1',
},
"irn_flags" => "R",
"comment" => "construct FP Max: Max(a, b) = Max(b, a) = a > b ? a : b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fmax %S1, %S2, %D1 /* FP Max(%S1, %S2) -> %D1 */',
+ "emit" => '. fmax %S1, %S2, %D1',
},
"fMin" => {
"irn_flags" => "R",
"comment" => "construct FP Min: Min(a, b) = Min(b, a) = a < b ? a : b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fmin %S1, %S2, %D1 /* FP Min(%S1, %S2) -> %D1 */',
+ "emit" => '. fmin %S1, %S2, %D1',
},
# not commutative operations
"irn_flags" => "R",
"comment" => "construct FP Sub: Sub(a, b) = a - b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fsub %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */',
+ "emit" => '. fsub %D1, %S1, %S2',
},
"fSubs" => {
"irn_flags" => "R",
"comment" => "construct FP Sub (single): Sub(a, b) = a - b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fsub %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */',
+ "emit" => '. fsubs %D1, %S1, %S2',
},
"fDiv" => {
"comment" => "construct FP Div: Div(a, b) = a / b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fdiv %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */',
+ "emit" => '. fdiv %D1, %S1, %S2',
},
"fDivs" => {
"comment" => "construct FP Div (single): Div(a, b) = a / b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
- "emit" => '. fdivs %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */',
+ "emit" => '. fdivs %D1, %S1, %S2',
},
"fMinus" => {
"irn_flags" => "R",
"comment" => "construct FP Minus: fMinus(a) = -a",
"reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
- "emit" => '. fneg %D1, %S1 /* FP fMinus(%S1) -> %D1 */',
+ "emit" => '. fneg %D1, %S1',
},
"fCtiw" => {
"irn_flags" => "R",
"comment" => "construct FP Convert to integer word: fCtiw(a) = (int) a",
"reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
- "emit" => '. fctiw %D1, %S1 /* FP fCtiw(%S1) -> %D1 */',
+ "emit" => '. fctiw %D1, %S1',
},
"fRsp" => {
"irn_flags" => "R",
"comment" => "construct FP Round to single: fRsp(a) = (float) a",
"reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
- "emit" => '. frsp %D1, %S1 /* FP fRsp(%S1) -> %D1 */',
+ "emit" => '. frsp %D1, %S1',
},
"fAbs" => {
"irn_flags" => "R",
"comment" => "construct FP Abs: fAbs(a) = |a|",
"reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
- "emit" => '. fabs %D1, %S1 /* FP fAbs(%S1) -> %D1 */',
+ "emit" => '. fabs %D1, %S1',
},
"fCmpu" => {
"irn_flags" => "R",
"comment" => "construct FP Cmp unordered: fCmpu(a, b) = a ? b",
"reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "condition" ] },
- "emit" => '. fcmpu %D1, %S1, %S2 /* FP fCmpu(%S1, %S2) -> %D1 */',
+ "emit" => '. fcmpu %D1, %S1, %S2',
},
# other operations
# "irn_flags" => "R",
# "comment" => "represents a FP constant",
# "reg_req" => { "out" => [ "fp" ] },
-# "emit" => '. fmov %C, %D1 /* Mov fConst into register */',
+# "emit" => '. fmov %C, %D1',
# "cmp_attr" =>
#'
# /* TODO: compare fConst attributes */
"state" => "exc_pinned",
"comment" => "construct FP Load (double): Load(ptr, mem) = LD ptr",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "fp", "none" ] },
- "emit" => '. lfd %D1, %O(%S1) /* Load(%O(%S1)) -> %D1 */',
+ "emit" => '. lfd %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct FP Load (single): Load(ptr, mem) = LD ptr",
"reg_req" => { "in" => [ "!r0", "none" ], "out" => [ "fp","none" ] },
- "emit" => '. lfs %D1, %O(%S1) /* Load(%O(%S1)) -> %D1 */',
+ "emit" => '. lfs %D1, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Store (double): Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { "in" => [ "!r0", "fp", "none" ] },
- "emit" => '. stfd %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "emit" => '. stfd %S2, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
"state" => "exc_pinned",
"comment" => "construct Store (single): Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { "in" => [ "!r0", "fp", "none" ] },
- "emit" => '. stfs %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "emit" => '. stfs %S2, %O(%S1)',
"cmp_attr" =>
'
return (attr_a->data.constant_tarval != attr_b->data.constant_tarval);
#include "gen_ppc32_regalloc_if.h"
-extern pset *symbol_pset;
extern ir_op *get_op_Mulh(void);
int is_direct_entity(ir_entity *ent);
* or false, if the address must be loaded first
*/
int is_direct_entity(ir_entity *ent) {
- return get_entity_visibility(ent)!=visibility_external_allocated;
+ return get_entity_visibility(ent) != visibility_external_allocated;
/* visibility vis = get_entity_visibility(ent);
if(is_Method_type(get_entity_type(ent)))
{
set_ppc32_symconst_ident(node, id_symconst);
set_ppc32_offset_mode(node, ppc32_ao_Lo16);
node = new_rd_Proj(env->dbg, env->irg, env->block, node, env->mode, pn_Load_res);
-// pset_insert_ptr(symbol_pset, ent);
}
break;
}
projects / libfirm / commitdiff