*/
extern arch_irn_flags_t arch_irn_get_flags(const arch_env_t *env, const ir_node *irn);
-#define arch_irn_is_ignore(env, irn) ((arch_irn_get_flags(env, irn) & arch_irn_flags_ignore) != 0)
+#define arch_irn_is(env, irn, flag) ((arch_irn_get_flags(env, irn) & arch_irn_flags_ ## flag) != 0)
#define arch_irn_has_reg_class(env, irn, pos, cls) \
((cls) == arch_get_irn_reg_class(env, irn, pos))
#define arch_irn_consider_in_reg_alloc(env, cls, irn) \
- (arch_irn_has_reg_class(env, irn, -1, cls) && !arch_irn_is_ignore(env, irn))
+ (arch_irn_has_reg_class(env, irn, -1, cls) && !arch_irn_is(env, irn, ignore))
/**
* Somebody who can be asked about IR nodes.
int co_is_optimizable_root(const copy_opt_t *co, ir_node *irn) {
arch_register_req_t req;
- if (arch_irn_is_ignore(co->aenv, irn))
+ if (arch_irn_is(co->aenv, irn, ignore))
return 0;
if (is_Reg_Phi(irn) || is_Perm_Proj(co->aenv, irn) || is_2addr_code(co->aenv, irn, &req))
assert(0 && "Is buggy and obsolete. Do not use");
- if (arch_irn_is_ignore(co->aenv, irn))
+ if (arch_irn_is(co->aenv, irn, ignore))
return 0;
foreach_out_edge(irn, edge) {
int pos, max;
arch_register_req_t req;
- if (!is_curr_reg_class(co, irn) || arch_irn_is_ignore(co->aenv, irn))
+ if (!is_curr_reg_class(co, irn) || arch_irn_is(co->aenv, irn, ignore))
return;
/* Phis */
firm_dbg_module_t *mod = firm_dbg_register("firm.be.lower");
const arch_register_class_t *cls = arch_get_irn_reg_class(arch_env, other_different, -1);
- if (arch_irn_is_ignore(arch_env, other_different) || ! mode_is_datab(get_irn_mode(other_different))) {
+ if (arch_irn_is(arch_env, other_different, ignore) || ! mode_is_datab(get_irn_mode(other_different))) {
DBG((mod, LEVEL_1, "ignore constraint for %+F because other_irn is ignore or not a datab node\n", irn));
return;
}
void be_main(FILE *file_handle)
{
/* never build code for pseudo irgs */
- set_visit_pseudo_irgs(0);
+ set_visit_pseudo_irgs(0);
be_node_init();
be_main_loop(file_handle);
if (!is_Phi(phi))
break;
- if (arch_irn_is_ignore(raenv->aenv, phi))
+ if (arch_irn_is(raenv->aenv, phi, ignore))
continue;
raenv->cls = arch_get_irn_reg_class(raenv->aenv, phi, -1);
int c_spills=0, c_reloads=0;
pset_foreach(vi->values, irn) {
- if (arch_irn_is_ignore(raenv->aenv, irn) || be_is_Reload(irn)) {
+ if (arch_irn_is(raenv->aenv, irn, ignore) || be_is_Reload(irn)) {
pset_break(vi->values);
return UNSPILLABLE;
}
int pos, max;
var_info_t *vi1, *vi2;
- if (arch_get_irn_reg_class(raenv->aenv, irn, -1) != raenv->cls || arch_irn_is_ignore(raenv->aenv, irn))
+ if (arch_get_irn_reg_class(raenv->aenv, irn, -1) != raenv->cls || arch_irn_is(raenv->aenv, irn, ignore))
return;
vi1 = get_var_info(irn);
if (arch_irn_classify(raenv->aenv, irn) == arch_irn_class_copy) {
ir_node *other = get_irn_n(irn, be_pos_Copy_orig);
- if (! arch_irn_is_ignore(raenv->aenv, other)) {
+ if (! arch_irn_is(raenv->aenv, other, ignore)) {
vi2 = get_var_info(other);
fprintf(raenv->f, "(%d, %d, %d)\n", vi1->var_nr, vi2->var_nr, get_affinity_weight(irn));
for (pos = 0, max = get_irn_arity(irn); pos<max; ++pos) {
arch_get_register_req(raenv->aenv, &req, irn, pos);
- if (arch_register_req_is(&req, should_be_same) && arch_irn_is_ignore(raenv->aenv, req.other_same)) {
+ if (arch_register_req_is(&req, should_be_same) && arch_irn_is(raenv->aenv, req.other_same, ignore)) {
vi2 = get_var_info(req.other_same);
fprintf(raenv->f, "(%d, %d, %d)\n", vi1->var_nr, vi2->var_nr, get_affinity_weight(irn));
ir_node *spill;
DBG((dbg, DBG_SPILL, "Removing %+F before %+F in %+F\n", irn, sched_next(irn), get_nodes_block(irn)));
- spill = get_irn_n(irn, be_pos_Reload_mem);
+ if (be_is_Reload(irn))
+ spill = get_irn_n(irn, be_pos_Reload_mem);
/* remove reload */
set_irn_n(irn, 0, new_Bad());
sched_remove(irn);
- /* if spill not used anymore, remove it too
- * test of regclass is necessary since spill may be a phi-M */
- if (get_irn_n_edges(spill) == 0 && bel->cls == arch_get_irn_reg_class(bel->arch, spill, -1)) {
- set_irn_n(spill, 0, new_Bad());
- sched_remove(spill);
+ if (be_is_Reload(irn)) {
+ /* if spill not used anymore, remove it too
+ * test of regclass is necessary since spill may be a phi-M */
+ if (get_irn_n_edges(spill) == 0 && bel->cls == arch_get_irn_reg_class(bel->arch, spill, -1)) {
+ set_irn_n(spill, 0, new_Bad());
+ sched_remove(spill);
+ }
}
}
}