}
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int TEMPLATE_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- return get_mode_size_bytes(mode);
-}
-
static void TEMPLATE_lower_for_target(void)
{
lower_builtins(0, NULL);
return &p;
}
-static ir_graph **TEMPLATE_get_backend_irg_list(const void *self,
- ir_graph ***irgs)
-{
- (void) self;
- (void) irgs;
- return NULL;
-}
-
static asm_constraint_flags_t TEMPLATE_parse_asm_constraint(const char **c)
{
(void) c;
TEMPLATE_done,
NULL, /* handle intrinsics */
TEMPLATE_get_call_abi,
- TEMPLATE_get_reg_class_alignment,
TEMPLATE_get_backend_params,
- TEMPLATE_get_backend_irg_list,
NULL, /* mark remat */
TEMPLATE_parse_asm_constraint,
TEMPLATE_is_valid_clobber,
}
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- return get_mode_size_bytes(mode);
-}
-
static void amd64_lower_for_target(void)
{
size_t i, n_irgs = get_irp_n_irgs();
return &p;
}
-static ir_graph **amd64_get_backend_irg_list(const void *self,
- ir_graph ***irgs)
-{
- (void) self;
- (void) irgs;
- return NULL;
-}
-
static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
{
(void) c;
amd64_done,
NULL, /* handle intrinsics */
amd64_get_call_abi,
- amd64_get_reg_class_alignment,
amd64_get_backend_params,
- amd64_get_backend_irg_list,
NULL, /* mark remat */
amd64_parse_asm_constraint,
amd64_is_valid_clobber,
free(self);
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- (void) cls;
- /* ARM is a 32 bit CPU, no need for other alignment */
- return 4;
-}
-
-/**
- * Return irp irgs in the desired order.
- */
-static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
-{
- (void) self;
- (void) irg_list;
- return NULL;
-}
-
/**
* Allows or disallows the creation of Psi nodes for the given Phi nodes.
* @return 1 if allowed, 0 otherwise
arm_done,
NULL, /* handle_intrinsics */
NULL,
- arm_get_reg_class_alignment,
arm_get_libfirm_params,
- arm_get_irg_list,
NULL, /* mark remat */
arm_parse_asm_constraint,
arm_is_valid_clobber,
void (*get_call_abi)(const void *self, ir_type *call_type,
be_abi_call_t *abi);
- /**
- * Get the necessary alignment for storing a register of given class.
- * @param self The isa object.
- * @param cls The register class.
- * @return The alignment in bytes.
- */
- int (*get_reg_class_alignment)(const arch_register_class_t *cls);
-
/**
* A "static" function, returns the frontend settings
* needed for this backend.
*/
const backend_params *(*get_params)(void);
- /**
- * Return an ordered list of irgs where code should be generated for.
- * If NULL is returned, all irg will be taken into account and they will be
- * generated in an arbitrary order.
- * @param self The isa object.
- * @param irgs A flexible array ARR_F of length 0 where the backend can
- * append the desired irgs.
- * @return A flexible array ARR_F containing all desired irgs in the
- * desired order.
- */
- ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs);
-
/**
* mark node as rematerialized
*/
#define arch_env_handle_intrinsics(env) \
do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
#define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((env), (tp), (abi)))
-#define arch_env_get_reg_class_alignment(env,cls) ((env)->impl->get_reg_class_alignment((cls)))
#define arch_env_get_params(env) ((env)->impl->get_params())
#define arch_env_get_allowed_execution_units(env,irn) ((env)->impl->get_allowed_execution_units((irn)))
#define arch_env_get_machine(env) ((env)->impl->get_machine(env))
-#define arch_env_get_backend_irg_list(env,irgs) ((env)->impl->get_backend_irg_list((env), (irgs)))
#define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
#define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
#define arch_env_mark_remat(env,node) \
be_main_env_t env;
char prof_filename[256];
be_irg_t *birgs;
- ir_graph **irg_list, **backend_irg_list;
arch_env_t *arch_env;
be_timing = (be_options.timing == BE_TIME_ON);
arch_env = env.arch_env;
- /* backend may provide an ordered list of irgs where code should be
- * generated for */
- irg_list = NEW_ARR_F(ir_graph *, 0);
- backend_irg_list = arch_env_get_backend_irg_list(arch_env, &irg_list);
-
/* we might need 1 birg more for instrumentation constructor */
- num_birgs = backend_irg_list ? ARR_LEN(backend_irg_list) : get_irp_n_irgs();
+ num_birgs = get_irp_n_irgs();
birgs = ALLOCAN(be_irg_t, num_birgs + 1);
be_info_init();
/* First: initialize all birgs */
for (i = 0; i < num_birgs; ++i) {
- ir_graph *irg = backend_irg_list ? backend_irg_list[i] : get_irp_irg(i);
+ ir_graph *irg = get_irp_irg(i);
initialize_birg(&birgs[i], irg, &env);
}
arch_env_handle_intrinsics(arch_env);
- DEL_ARR_F(irg_list);
/*
Get the filename for the profiling data.
}
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- int bytes = get_mode_size_bytes(mode);
-
- if (mode_is_float(mode) && bytes > 8)
- return 16;
- return bytes;
-}
-
-/**
- * Return irp irgs in the desired order.
- */
-static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
-{
- (void) self;
- (void) irg_list;
- return NULL;
-}
-
static void ia32_mark_remat(ir_node *node)
{
if (is_ia32_irn(node)) {
ia32_done,
ia32_handle_intrinsics,
ia32_get_call_abi,
- ia32_get_reg_class_alignment,
ia32_get_libfirm_params,
- ia32_get_irg_list,
ia32_mark_remat,
ia32_parse_asm_constraint,
ia32_is_valid_clobber,
free(isa);
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int sparc_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- return get_mode_size_bytes(mode);
-}
-
static void sparc_lower_for_target(void)
{
size_t i, n_irgs = get_irp_n_irgs();
return &p;
}
-static ir_graph **sparc_get_backend_irg_list(const void *self,
- ir_graph ***irgs)
-{
- (void) self;
- (void) irgs;
- return NULL;
-}
-
static asm_constraint_flags_t sparc_parse_asm_constraint(const char **c)
{
(void) c;
sparc_done,
NULL, /* handle intrinsics */
NULL,
- sparc_get_reg_class_alignment,
sparc_get_backend_params,
- sparc_get_backend_irg_list,
NULL, /* mark remat */
sparc_parse_asm_constraint,
sparc_is_valid_clobber,