tarval *tv_mode_bits; /**< a tarval containing the number of bits in the lowered modes */
pdeq *waitq; /**< a wait queue of all nodes that must be handled later */
pmap *proj_2_block; /**< a map from ProjX to its destination blocks */
+ ir_mode *high_signed; /**< doubleword signed type */
+ ir_mode *high_unsigned; /**< doubleword unsigned type */
+ ir_mode *low_signed; /**< word signed type */
+ ir_mode *low_unsigned; /**< word unsigned type */
ident *first_id; /**< .l for little and .h for big endian */
ident *next_id; /**< .h for little and .l for big endian */
const lwrdw_param_t *params; /**< transformation parameter */
if (! entry->mtd) {
int n_param = 1, n_res = 1;
- if (imode == env->params->high_signed || imode == env->params->high_unsigned)
+ if (imode == env->high_signed || imode == env->high_unsigned)
n_param = 2;
- if (omode == env->params->high_signed || omode == env->params->high_unsigned)
+ if (omode == env->high_signed || omode == env->high_unsigned)
n_res = 2;
/* create a new one */
/* set param types and result types */
n_param = 0;
- if (imode == env->params->high_signed) {
+ if (imode == env->high_signed) {
set_method_param_type(mtd, n_param++, tp_u);
set_method_param_type(mtd, n_param++, tp_s);
- } else if (imode == env->params->high_unsigned) {
+ } else if (imode == env->high_unsigned) {
set_method_param_type(mtd, n_param++, tp_u);
set_method_param_type(mtd, n_param++, tp_u);
} else {
} /* if */
n_res = 0;
- if (omode == env->params->high_signed) {
+ if (omode == env->high_signed) {
set_method_res_type(mtd, n_res++, tp_u);
set_method_res_type(mtd, n_res++, tp_s);
- } else if (omode == env->params->high_unsigned) {
+ } else if (omode == env->high_unsigned) {
set_method_res_type(mtd, n_res++, tp_u);
set_method_res_type(mtd, n_res++, tp_u);
} else {
node_entry_t *link;
int i, idx;
- if (mode == lenv->params->high_signed ||
- mode == lenv->params->high_unsigned) {
+ if (mode == lenv->high_signed ||
+ mode == lenv->high_unsigned) {
/* ok, found a node that will be lowered */
link = OALLOCZ(&lenv->obst, node_entry_t);
ir_node *pred = get_Conv_op(node);
mode = get_irn_mode(pred);
- if (mode == lenv->params->high_signed ||
- mode == lenv->params->high_unsigned) {
+ if (mode == lenv->high_signed ||
+ mode == lenv->high_unsigned) {
/* must lower this node either but don't need a link */
lenv->flags |= MUST_BE_LOWERED;
} /* if */
dbg_info *dbg = get_irn_dbg_info(node);
int idx;
ir_graph *irg = current_ir_graph;
- ir_mode *low_mode = env->params->low_unsigned;
+ ir_mode *low_mode = env->low_unsigned;
tv = get_Const_tarval(node);
*/
static void lower_Load(ir_node *node, ir_mode *mode, lower_env_t *env)
{
- ir_mode *low_mode = env->params->low_unsigned;
+ ir_mode *low_mode = env->low_unsigned;
ir_graph *irg = current_ir_graph;
ir_node *adr = get_Load_ptr(node);
ir_node *mem = get_Load_mem(node);
case pn_Div_res: /* Result of computation. */
idx = get_irn_idx(proj);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irn, env->params->low_unsigned, 0);
+ env->entries[idx]->low_word = new_r_Proj(irn, env->low_unsigned, 0);
env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
break;
default:
case pn_Mod_res: /* Result of computation. */
idx = get_irn_idx(proj);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irn, env->params->low_unsigned, 0);
+ env->entries[idx]->low_word = new_r_Proj(irn, env->low_unsigned, 0);
env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
break;
default:
case pn_DivMod_res_div: /* Result of Div. */
idx = get_irn_idx(proj);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(resDiv, env->params->low_unsigned, 0);
+ env->entries[idx]->low_word = new_r_Proj(resDiv, env->low_unsigned, 0);
env->entries[idx]->high_word = new_r_Proj(resDiv, mode, 1);
break;
case pn_DivMod_res_mod: /* Result of Mod. */
idx = get_irn_idx(proj);
- env->entries[idx]->low_word = new_r_Proj(resMod, env->params->low_unsigned, 0);
+ env->entries[idx]->low_word = new_r_Proj(resMod, env->low_unsigned, 0);
env->entries[idx]->high_word = new_r_Proj(resMod, mode, 1);
break;
default:
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irn, env->params->low_unsigned, 0);
- env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irn, env->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
} /* lower_Binop */
/**
/* The shift count is always mode_Iu in firm, so there is no need for lowering */
in[2] = get_binop_right(node);
- assert(get_irn_mode(in[2]) != env->params->high_signed
- && get_irn_mode(in[2]) != env->params->high_unsigned);
+ assert(get_irn_mode(in[2]) != env->high_signed
+ && get_irn_mode(in[2]) != env->high_unsigned);
dbg = get_irn_dbg_info(node);
block = get_nodes_block(node);
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irn, env->params->low_unsigned, 0);
- env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irn, env->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
} /* lower_Shiftop */
/**
get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shr_left(node);
- ir_mode *low_unsigned = env->params->low_unsigned;
+ ir_mode *low_unsigned = env->low_unsigned;
ir_node *c;
long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
int idx = get_irn_idx(left);
left = new_r_Conv(block, left, low_unsigned);
if (shf_cnt > 0) {
- ir_mode *low_unsigned = env->params->low_unsigned;
c = new_r_Const_long(irg, low_unsigned, shf_cnt);
env->entries[idx]->low_word = new_r_Shr(block, left, c,
low_unsigned);
left = new_r_Conv(block, left, mode);
idx = get_irn_idx(node);
- mode_l = env->params->low_unsigned;
+ mode_l = env->low_unsigned;
if (shf_cnt > 0) {
c = new_r_Const_long(irg, mode_l, shf_cnt);
env->entries[idx]->high_word = new_r_Shl(block, left, c, mode);
get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) {
ir_node *block = get_nodes_block(node);
ir_node *left = get_Shrs_left(node);
- ir_mode *low_unsigned = env->params->low_unsigned;
+ ir_mode *low_unsigned = env->low_unsigned;
long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
int idx = get_irn_idx(left);
ir_node *left_unsigned = left;
if (is_Rotl(node)) {
ir_mode *mode = get_irn_op_mode(node);
- if (mode == lenv->params->high_signed ||
- mode == lenv->params->high_unsigned) {
+ if (mode == lenv->high_signed ||
+ mode == lenv->high_unsigned) {
ir_node *right = get_Rotl_right(node);
ir_node *left, *shl, *shr, *or, *block, *sub, *c;
ir_mode *omode, *rmode;
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_r_Proj(irn, env->params->low_unsigned, 0);
- env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
+ env->entries[idx]->low_word = new_r_Proj(irn, env->low_unsigned, 0);
+ env->entries[idx]->high_word = new_r_Proj(irn, mode, 1);
} /* lower_Unop */
/**
idx = get_irn_idx(node);
assert(idx < env->n_entries);
irg = current_ir_graph;
- env->entries[idx]->low_word = constr_rd(dbg, block, lop_l, rop_l, env->params->low_unsigned);
+ env->entries[idx]->low_word = constr_rd(dbg, block, lop_l, rop_l, env->low_unsigned);
env->entries[idx]->high_word = constr_rd(dbg, block, lop_h, rop_h, mode);
} /* lower_Binop_logical */
idx = get_irn_idx(node);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Not(dbg, block, op_l, env->params->low_unsigned);
+ env->entries[idx]->low_word = new_rd_Not(dbg, block, op_l, env->low_unsigned);
env->entries[idx]->high_word = new_rd_Not(dbg, block, op_h, mode);
} /* lower_Not */
if (is_Const(right) && is_Const_null(right)) {
if (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) {
/* x ==/!= 0 ==> or(low,high) ==/!= 0 */
- ir_mode *mode = env->params->low_unsigned;
+ ir_mode *mode = env->low_unsigned;
ir_node *low = new_r_Conv(block, lentry->low_word, mode);
ir_node *high = new_r_Conv(block, lentry->high_word, mode);
ir_node *or = new_rd_Or(dbg, block, low, high, mode);
ir_node *block = get_nodes_block(node);
dbg_info *dbg = get_irn_dbg_info(node);
node_entry_t *entry = env->entries[idx];
- ir_mode *low_unsigned = env->params->low_unsigned;
+ ir_mode *low_unsigned = env->low_unsigned;
ir_mode *low_signed
- = mode_is_signed(omode) ? env->params->low_signed : low_unsigned;
+ = mode_is_signed(omode) ? env->low_signed : low_unsigned;
assert(idx < env->n_entries);
if (mode_is_int(imode) || mode_is_reference(imode)) {
- if (imode == env->params->high_signed
- || imode == env->params->high_unsigned) {
+ if (imode == env->high_signed
+ || imode == env->high_unsigned) {
/* a Conv from Lu to Ls or Ls to Lu */
int op_idx = get_irn_idx(op);
node_entry_t *op_entry = env->entries[op_idx];
op = entry->low_word;
/* simple case: create a high word */
- if (omode != env->params->low_unsigned)
+ if (omode != env->low_unsigned)
op = new_rd_Conv(dbg, block, op, omode);
set_Conv_op(node, op);
} else if (omode == mode_b) {
/* llu ? true : false <=> (low|high) ? true : false */
- ir_mode *mode = env->params->low_unsigned;
+ ir_mode *mode = env->low_unsigned;
ir_node *or = new_rd_Or(dbg, block, entry->low_word, entry->high_word,
mode);
set_Conv_op(node, or);
{
mode = get_irn_mode(node);
- if (mode == env->params->high_signed
- || mode == env->params->high_unsigned) {
+ if (mode == env->high_signed
+ || mode == env->high_unsigned) {
lower_Conv_to_Ll(node, env);
} else {
ir_mode *mode = get_irn_mode(get_Conv_op(node));
- if (mode == env->params->high_signed
- || mode == env->params->high_unsigned) {
+ if (mode == env->high_signed
+ || mode == env->high_unsigned) {
lower_Conv_from_Ll(node, env);
}
}
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned)
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned)
++n_param;
} /* if */
} /* for */
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned)
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned)
++n_res;
} /* if */
} /* for */
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed) {
+ if (mode == env->high_signed) {
set_method_param_type(res, n_param++, tp_u);
set_method_param_type(res, n_param++, tp_s);
- } else if (mode == env->params->high_unsigned) {
+ } else if (mode == env->high_unsigned) {
set_method_param_type(res, n_param++, tp_u);
set_method_param_type(res, n_param++, tp_u);
} else {
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed) {
+ if (mode == env->high_signed) {
set_method_res_type(res, n_res++, tp_u);
set_method_res_type(res, n_res++, tp_s);
- } else if (mode == env->params->high_unsigned) {
+ } else if (mode == env->high_unsigned) {
set_method_res_type(res, n_res++, tp_u);
set_method_res_type(res, n_res++, tp_u);
} else {
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed || mode == env->params->high_unsigned) {
+ if (mode == env->high_signed || mode == env->high_unsigned) {
if (id != NULL) {
lid = id_mangle(id, env->first_id);
set_method_param_ident(res, n_param, lid);
ir_node *pred = get_Return_res(node, i);
ir_mode *mode = get_irn_op_mode(pred);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned) {
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned) {
idx = get_irn_idx(pred);
if (! env->entries[idx]->low_word) {
/* not ready yet, wait */
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned)
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned)
++j;
} /* if */
} /* for */
idx = get_irn_idx(proj);
if (env->entries[idx]) {
- ir_mode *low_mode = env->params->low_unsigned;
+ ir_mode *low_mode = env->low_unsigned;
mode = get_irn_mode(proj);
- if (mode == env->params->high_signed) {
- mode = env->params->low_signed;
+ if (mode == env->high_signed) {
+ mode = env->low_signed;
} else {
- mode = env->params->low_unsigned;
+ mode = env->low_unsigned;
} /* if */
dbg = get_irn_dbg_info(proj);
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned) {
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned) {
need_lower = 1;
break;
} /* if */
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned) {
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned) {
need_lower = 1;
++j;
} /* if */
idx = get_irn_idx(proj);
if (env->entries[idx]) {
ir_mode *mode = get_irn_mode(proj);
- ir_mode *low_mode = env->params->low_unsigned;
+ ir_mode *low_mode = env->low_unsigned;
dbg_info *dbg;
- if (mode == env->params->high_signed) {
- mode = env->params->low_signed;
+ if (mode == env->high_signed) {
+ mode = env->low_signed;
} else {
- mode = env->params->low_unsigned;
+ mode = env->low_unsigned;
} /* if */
dbg = get_irn_dbg_info(proj);
{
int idx = get_irn_idx(node);
ir_graph *irg = get_irn_irg(node);
- ir_mode *low_mode = env->params->low_unsigned;
+ ir_mode *low_mode = env->low_unsigned;
env->entries[idx]->low_word = new_r_Unknown(irg, low_mode);
env->entries[idx]->high_word = new_r_Unknown(irg, mode);
*/
static void lower_Phi(ir_node *phi, ir_mode *mode, lower_env_t *env)
{
- ir_mode *mode_l = env->params->low_unsigned;
+ ir_mode *mode_l = env->low_unsigned;
ir_graph *irg = get_irn_irg(phi);
ir_node *block, *unk_l, *unk_h, *phi_l, *phi_h;
ir_node **inl, **inh;
idx = get_irn_idx(mux);
assert(idx < env->n_entries);
- env->entries[idx]->low_word = new_rd_Mux(dbg, block, sel, false_l, true_l, env->params->low_unsigned);
+ env->entries[idx]->low_word = new_rd_Mux(dbg, block, sel, false_l, true_l, env->low_unsigned);
env->entries[idx]->high_word = new_rd_Mux(dbg, block, sel, false_h, true_h, mode);
} /* lower_Mux */
*/
static void lower_ASM(ir_node *asmn, ir_mode *mode, lower_env_t *env)
{
- ir_mode *his = env->params->high_signed;
- ir_mode *hiu = env->params->high_unsigned;
+ ir_mode *his = env->high_signed;
+ ir_mode *hiu = env->high_unsigned;
int i;
ir_node *n;
ir_node *arg = get_Cmp_left(cmp);
mode = get_irn_mode(arg);
- if (mode == lenv->params->high_signed ||
- mode == lenv->params->high_unsigned) {
+ if (mode == lenv->high_signed ||
+ mode == lenv->high_unsigned) {
ir_node *res = lower_boolean_Proj_Cmp(proj, cmp, lenv);
if (res == NULL) {
if (func) {
mode = get_irn_op_mode(node);
- if (mode == lenv->params->high_signed)
- mode = lenv->params->low_signed;
+ if (mode == lenv->high_signed)
+ mode = lenv->low_signed;
else
- mode = lenv->params->low_unsigned;
+ mode = lenv->low_unsigned;
DB((dbg, LEVEL_1, " %+F\n", node));
func(node, mode, lenv);
*
* @param mtp the method type
*/
-static int mtp_must_to_lowered(ir_type *mtp, lower_env_t *env)
+static int mtp_must_be_lowered(ir_type *mtp, lower_env_t *env)
{
int i, n_params;
if (is_Primitive_type(tp)) {
ir_mode *mode = get_type_mode(tp);
- if (mode == env->params->high_signed ||
- mode == env->params->high_unsigned)
+ if (mode == env->high_signed ||
+ mode == env->high_unsigned)
return 1;
} /* if */
} /* for */
return 0;
-} /* mtp_must_to_lowered */
+}
+
+static void setup_modes(lower_env_t *env)
+{
+ unsigned size_bits = env->params->doubleword_size;
+ ir_mode *doubleword_signed = NULL;
+ ir_mode *doubleword_unsigned = NULL;
+ int n_modes = get_irp_n_modes();
+ ir_mode_arithmetic arithmetic;
+ unsigned modulo_shift;
+ int i;
+
+ /* search for doubleword modes... */
+ for (i = 0; i < n_modes; ++i) {
+ ir_mode *mode = get_irp_mode(i);
+ if (!mode_is_int(mode))
+ continue;
+ if (get_mode_size_bits(mode) != size_bits)
+ continue;
+ if (mode_is_signed(mode)) {
+ if (doubleword_signed != NULL) {
+ /* sigh - the lowerer should really just lower all mode with
+ * size_bits it finds. Unfortunately this required a bigger
+ * rewrite. */
+ panic("multiple double word signed modes found");
+ }
+ doubleword_signed = mode;
+ } else {
+ if (doubleword_unsigned != NULL) {
+ /* sigh - the lowerer should really just lower all mode with
+ * size_bits it finds. Unfortunately this required a bigger
+ * rewrite. */
+ panic("multiple double word unsigned modes found");
+ }
+ doubleword_unsigned = mode;
+ }
+ }
+ if (doubleword_signed == NULL || doubleword_unsigned == NULL) {
+ panic("Couldn't find doubleword modes");
+ }
+
+ arithmetic = get_mode_arithmetic(doubleword_signed);
+ modulo_shift = get_mode_modulo_shift(doubleword_signed);
+
+ assert(get_mode_size_bits(doubleword_unsigned) == size_bits);
+ assert(size_bits % 2 == 0);
+ assert(get_mode_sign(doubleword_signed) == 1);
+ assert(get_mode_sign(doubleword_unsigned) == 0);
+ assert(get_mode_sort(doubleword_signed) == irms_int_number);
+ assert(get_mode_sort(doubleword_unsigned) == irms_int_number);
+ assert(get_mode_arithmetic(doubleword_unsigned) == arithmetic);
+ assert(get_mode_modulo_shift(doubleword_unsigned) == modulo_shift);
+
+ /* try to guess a sensible modulo shift for the new mode.
+ * (This is IMO another indication that this should really be a node
+ * attribute instead of a mode thing) */
+ if (modulo_shift == size_bits) {
+ modulo_shift = modulo_shift / 2;
+ } else if (modulo_shift == 0) {
+ /* fine */
+ } else {
+ panic("Don't know what new modulo shift to use for lowered doubleword mode");
+ }
+ size_bits /= 2;
+
+ /* produce lowered modes */
+ env->high_signed = doubleword_signed;
+ env->high_unsigned = doubleword_unsigned;
+ env->low_signed = new_ir_mode("WS", irms_int_number, size_bits, 1,
+ arithmetic, modulo_shift);
+ env->low_unsigned = new_ir_mode("WU", irms_int_number, size_bits, 0,
+ arithmetic, modulo_shift);
+}
/*
* Do the lowering.
if (! param)
return;
- if (! param->enable)
- return;
-
FIRM_DBG_REGISTER(dbg, "firm.lower.dw");
- assert(2 * get_mode_size_bits(param->low_signed) == get_mode_size_bits(param->high_signed));
- assert(2 * get_mode_size_bits(param->low_unsigned) == get_mode_size_bits(param->high_unsigned));
- assert(get_mode_size_bits(param->low_signed) == get_mode_size_bits(param->low_unsigned));
+ memset(&lenv, 0, sizeof(lenv));
+ lenv.params = param;
+ setup_modes(&lenv);
/* create the necessary maps */
if (! intrinsic_fkt)
/* create a primitive unsigned and signed type */
if (! tp_u)
- tp_u = get_type_for_mode(param->low_unsigned);
+ tp_u = get_type_for_mode(lenv.low_unsigned);
if (! tp_s)
- tp_s = get_type_for_mode(param->low_signed);
+ tp_s = get_type_for_mode(lenv.low_signed);
/* create method types for the created binop calls */
if (! binop_tp_u) {
set_method_res_type(unop_tp_s, 1, tp_s);
} /* if */
- lenv.tv_mode_bytes = new_tarval_from_long(get_mode_size_bytes(param->low_unsigned), param->low_unsigned);
- lenv.tv_mode_bits = new_tarval_from_long(get_mode_size_bits(param->low_unsigned), param->low_unsigned);
+ lenv.tv_mode_bytes = new_tarval_from_long(param->doubleword_size/(2*8), lenv.low_unsigned);
+ lenv.tv_mode_bits = new_tarval_from_long(param->doubleword_size/2, lenv.low_unsigned);
lenv.waitq = new_pdeq();
- lenv.params = param;
lenv.first_id = new_id_from_chars(param->little_endian ? ".l" : ".h", 2);
lenv.next_id = new_id_from_chars(param->little_endian ? ".h" : ".l", 2);
ent = get_irg_entity(irg);
mtp = get_entity_type(ent);
- if (mtp_must_to_lowered(mtp, &lenv)) {
+ if (mtp_must_be_lowered(mtp, &lenv)) {
ir_type *ltp = lower_mtp(mtp, &lenv);
lenv.flags |= MUST_BE_LOWERED;
set_entity_type(ent, ltp);
current_ir_graph = rem;
} /* lower_dw_ops */
-struct pass_t {
- ir_prog_pass_t pass;
- const lwrdw_param_t *param;
-};
-
-/**
- * Creates a wrapper around lower_dw_ops().
- */
-static int pass_wrapper(ir_prog *irp, void *context)
-{
- struct pass_t *pass = context;
-
- (void)irp;
- lower_dw_ops(pass->param);
- return 0;
-}
-
-ir_prog_pass_t *lower_dw_ops_pass(const char *name, const lwrdw_param_t *param)
-{
- struct pass_t *pass = XMALLOCZ(struct pass_t);
-
- pass->param = param;
- return def_prog_pass_constructor(
- &pass->pass, name ? name : "lower_dw", pass_wrapper);
-} /* lower_dw_ops_pass */
-
/* Default implementation. */
ir_entity *def_create_intrinsic_fkt(ir_type *method, const ir_op *op,
const ir_mode *imode, const ir_mode *omode,