#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
+#include "../beblocksched.h"
+#include "../beirg_t.h"
#include "be.h"
#include "../beabi.h"
#include "../bemachine.h"
* |___/
**************************************************/
-
-typedef struct {
- ir_node *start;
- ir_node *end;
- unsigned cnt;
-} anchor;
-
-/**
- * Ext-Block walker: create a block schedule
- */
-static void create_block_list(ir_extblk *blk, void *env) {
- anchor *list = env;
- int i, n;
-
- for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
- ir_node *block = get_extbb_block(blk, i);
-
- set_irn_link(block, NULL);
- if (list->start)
- set_irn_link(list->end, block);
- else
- list->start = block;
-
- list->end = block;
- list->cnt += 1;
- }
-}
-
-/* return the scheduled block at position pos */
-ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
- if (0 <= pos && pos < ARR_LEN(cg->bl_list))
- return cg->bl_list[pos];
- return NULL;
-}
-
-/* return the number of scheduled blocks */
-int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
- return ARR_LEN(cg->bl_list);
-}
-
-/* set a block schedule number */
-void mips_set_block_sched_nr(ir_node *block, int nr) {
- set_irn_link(block, INT_TO_PTR(nr));
-}
-
-/* get a block schedule number */
-int mips_get_block_sched_nr(ir_node *block) {
- return PTR_TO_INT(get_irn_link(block));
-}
-
-/**
- * Creates a block schedule for the given graph.
- */
-static void mips_create_block_sched(mips_code_gen_t *cg) {
- anchor list;
- ir_node **bl_list, *block;
- unsigned i;
-
- if (cg->bl_list) {
- DEL_ARR_F(cg->bl_list);
- free_survive_dce(cg->bl_list_sdce);
- }
-
- /* calculate the block schedule here */
- compute_extbb(cg->irg);
-
- list.start = NULL;
- list.end = NULL;
- list.cnt = 0;
- irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
-
-
- bl_list = NEW_ARR_F(ir_node *, list.cnt);
- cg->bl_list_sdce = new_survive_dce();
- for (i = 0, block = list.start; block; block = get_irn_link(block)) {
- bl_list[i] = block;
- survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
- i++;
- }
-
- cg->bl_list = bl_list;
-}
-
-#if 0
-typedef struct _wenv_t {
- ir_node *list;
-} wenv_t;
-
-/**
- * Walker: link all CopyB nodes
- */
-static void collect_copyb_nodes(ir_node *node, void *env) {
- wenv_t *wenv = env;
-
- if (is_CopyB(node)) {
- set_irn_link(node, wenv->list);
- wenv->list = node;
- }
-}
-#endif
-
-static void replace_copyb_nodes(mips_code_gen_t *cg) {
-#if 0
- wenv_t env;
- ir_node *copy, *next;
- ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
- const ir_edge_t *edge;
-
- /* build code for all copyB */
- env.list = NULL;
- irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
-
- for (copy = env.list; copy; copy = next) {
- next = get_irn_link(copy);
-
- old_bl = get_nodes_block(copy);
- part_block(copy);
- jmp = get_Block_cfgpred(old_bl, 0);
- new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
-
- new_bl = new_r_Block(cg->irg, 1, &new_jmp);
- set_nodes_block(jmp, new_bl);
-
- mem = gen_code_for_CopyB(new_bl, copy);
-
- /* fix copyB's out edges */
- foreach_out_edge(copy, edge) {
- ir_node *succ = get_edge_src_irn(edge);
-
- assert(is_Proj(succ));
- switch (get_Proj_proj(succ)) {
- case pn_CopyB_M_regular:
- case pn_CopyB_M_except:
- exchange(succ, mem);
- break;
- default:
- exchange(succ, get_irg_bad(cg->irg));
- }
- }
- }
-#endif
- (void) cg;
-}
-
/**
* Transforms the standard firm graph into
* a mips firm graph
*/
static void mips_prepare_graph(void *self) {
mips_code_gen_t *cg = self;
- int bl_nr, n;
- // replace all copyb nodes in the block with a loop
- // and mips store/load nodes
- replace_copyb_nodes(cg);
+ /* do local optimizations */
+ optimize_graph_df(cg->irg);
- // Calculate block schedule
- mips_create_block_sched(cg);
-
- /* enter the block number into every blocks link field */
- for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
- ir_node *bl = mips_get_sched_block(cg, bl_nr);
- mips_set_block_sched_nr(bl, bl_nr);
- }
+ /* TODO: we often have dead code reachable through out-edges here. So for
+ * now we rebuild edges (as we need correct user count for code selection)
+ */
+#if 1
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+#endif
// walk the graph and transform firm nodes into mips nodes where possible
mips_transform_graph(cg);
dump_ir_block_graph_sched(cg->irg, "-transformed");
+
+ /* do local optimizations (mainly CSE) */
+ optimize_graph_df(cg->irg);
+
+ /* do code placement, to optimize the position of constants */
+ place_code(cg->irg);
+
+ be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
}
/**
mips_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
+ /* create block schedule, this also removes empty blocks which might
+ * produce critical edges */
+ cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
+
dump_ir_block_graph_sched(irg, "-mips-finished");
}
/* de-allocate code generator */
del_set(cg->reg_set);
- if (cg->bl_list) {
- DEL_ARR_F(cg->bl_list);
- free_survive_dce(cg->bl_list_sdce);
- }
free(cg);
}
const arch_env_t *arch_env = be_get_birg_arch_env(birg);
mips_isa_t *isa = (mips_isa_t *) arch_env;
mips_code_gen_t *cg = xmalloc(sizeof(*cg));
+ memset(cg, 0, sizeof(*cg));
cg->impl = &mips_code_gen_if;
cg->irg = be_get_birg_irg(birg);
cg->arch_env = arch_env;
cg->isa = isa;
cg->birg = birg;
- cg->bl_list = NULL;
cur_reg_set = cg->reg_set;
extern const arch_isa_if_t mips_isa_if;
-/** return the scheduled block at position pos */
-ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos);
-
-/** return the number of scheduled blocks */
-int mips_get_sched_n_blocks(const mips_code_gen_t *cg);
-
-/** set a block schedule number */
-void mips_set_block_sched_nr(ir_node *block, int nr);
-
-/** get a block schedule number */
-int mips_get_block_sched_nr(ir_node *block);
-
int mips_is_Load(const ir_node *node);
int mips_is_Store(const ir_node *node);
set *reg_set; /**< set to memorize registers for FIRM nodes (e.g. phi) */
mips_isa_t *isa; /**< the isa instance */
be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
- ir_node **bl_list; /**< The block schedule list. */
- survive_dce_t *bl_list_sdce; /**< survive dce environment for the block schedule list */
+ ir_node **block_schedule;
};
struct mips_isa_t {
int offset = be_get_IncSP_offset(node);
if(offset == 0) {
- be_emit_cstring("\t/* omitted IncSP with 0 */");
- be_emit_finish_line_gas(node);
return;
}
mips_emit_func_prolog(irg);
- dump_ir_block_graph_sched(irg, "-kaputtelist");
-
- for (i = 0, n = mips_get_sched_n_blocks(cg); i < n; ++i) {
- ir_node *block = mips_get_sched_block(cg, i);
+ n = ARR_LEN(cg->block_schedule);
+ for (i = 0; i < n; ++i) {
+ ir_node *block = cg->block_schedule[i];
mips_gen_block(block);
}
# NOTE: Last entry of each class is the largest Firm-Mode a register can hold\
%reg_classes = (
"gp" => [
- { name => "zero", type => 4+2 }, # always zero
+ { name => "zero", type => 4 }, # always zero
{ name => "at", type => 4 }, # reserved for assembler
{ name => "v0", realname => "2", type => 1 }, # first return value
{ name => "v1", realname => "3", type => 1 }, # second return value
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_entity *entity;
+ const arch_register_t **slots;
ir_node *lui, *or_const, *or;
if(get_SymConst_kind(node) != symconst_addr_ent) {
MIPS_IMM_SYMCONST_LO, entity, 0);
or = new_rd_mips_or(dbgi, irg, block, lui, or_const);
+ slots = get_mips_slots(or_const);
+ slots[0] = &mips_gp_regs[REG_GP_NOREG];
+
return or;
}
*
*********************************************************/
-static ir_node *gen_Bad(ir_node *node)
+typedef ir_node *(*mips_transform_func) (ir_node *node);
+
+static void register_transformer(ir_op *op, mips_transform_func func)
{
- panic("Unexpected node %+F found in mips transform phase.", node);
- return NULL;
+ assert(op->ops.generic == NULL);
+ op->ops.generic = (op_func) func;
}
static void register_transformers(void)
{
clear_irp_opcodes_generic_func();
- op_Add->ops.generic = (op_func) gen_Add;
- op_Sub->ops.generic = (op_func) gen_Sub;
- op_And->ops.generic = (op_func) gen_And;
- op_Or->ops.generic = (op_func) gen_Or;
- op_Eor->ops.generic = (op_func) gen_Eor;
- op_Shl->ops.generic = (op_func) gen_Shl;
- op_Shr->ops.generic = (op_func) gen_Shr;
- op_Shrs->ops.generic = (op_func) gen_Shrs;
- op_Not->ops.generic = (op_func) gen_Not;
- op_Minus->ops.generic = (op_func) gen_Minus;
- op_Div->ops.generic = (op_func) gen_Div;
- op_Mod->ops.generic = (op_func) gen_Mod;
- op_DivMod->ops.generic = (op_func) gen_DivMod;
- op_Abs->ops.generic = (op_func) gen_Abs;
- op_Load->ops.generic = (op_func) gen_Load;
- op_Store->ops.generic = (op_func) gen_Store;
- op_Cond->ops.generic = (op_func) gen_Cond;
- op_Conv->ops.generic = (op_func) gen_Conv;
- op_Const->ops.generic = (op_func) gen_Const;
- op_SymConst->ops.generic = (op_func) gen_SymConst;
- op_Unknown->ops.generic = (op_func) gen_Unknown;
- op_Proj->ops.generic = (op_func) gen_Proj;
- op_Phi->ops.generic = (op_func) gen_Phi;
-
- op_Raise->ops.generic = (op_func) gen_Bad;
- op_Sel->ops.generic = (op_func) gen_Bad;
- op_InstOf->ops.generic = (op_func) gen_Bad;
- op_Cast->ops.generic = (op_func) gen_Bad;
- op_Free->ops.generic = (op_func) gen_Bad;
- op_Tuple->ops.generic = (op_func) gen_Bad;
- op_Id->ops.generic = (op_func) gen_Bad;
- op_Confirm->ops.generic = (op_func) gen_Bad;
- op_Filter->ops.generic = (op_func) gen_Bad;
- op_CallBegin->ops.generic = (op_func) gen_Bad;
- op_EndReg->ops.generic = (op_func) gen_Bad;
- op_EndExcept->ops.generic = (op_func) gen_Bad;
+ register_transformer(op_Add, gen_Add);
+ register_transformer(op_Sub, gen_Sub);
+ register_transformer(op_And, gen_And);
+ register_transformer(op_Or, gen_Or);
+ register_transformer(op_Eor, gen_Eor);
+ register_transformer(op_Shl, gen_Shl);
+ register_transformer(op_Shr, gen_Shr);
+ register_transformer(op_Shrs, gen_Shrs);
+ register_transformer(op_Not, gen_Not);
+ register_transformer(op_Minus, gen_Minus);
+ register_transformer(op_Div, gen_Div);
+ register_transformer(op_Mod, gen_Mod);
+ register_transformer(op_DivMod, gen_DivMod);
+ register_transformer(op_Abs, gen_Abs);
+ register_transformer(op_Load, gen_Load);
+ register_transformer(op_Store, gen_Store);
+ register_transformer(op_Cond, gen_Cond);
+ register_transformer(op_Conv, gen_Conv);
+ register_transformer(op_Const, gen_Const);
+ register_transformer(op_SymConst, gen_SymConst);
+ register_transformer(op_Unknown, gen_Unknown);
+ register_transformer(op_Proj, gen_Proj);
+ register_transformer(op_Phi, gen_Phi);
}
void mips_transform_graph(mips_code_gen_t *cg)