"init_attr" => " attr->data.op_flav = dm_flav;",
"cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
"emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
+' if (mode_is_signed(get_ia32_res_mode(n))) {
4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
else {
if (get_irn_op(irn) == op_Div) {
set_Proj_proj(proj, pn_DivMod_res_div);
- in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
+ in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
}
else {
set_Proj_proj(proj, pn_DivMod_res_mod);
- in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
+ in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
}
be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
- set_ia32_res_mode(res, mode_Is);
+ set_ia32_res_mode(res, mode);
return res;
}
FORCE_x87(env->cg);
}
- new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+ new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+ am_offs = get_ia32_am_offs(node);
- if (am_offs = get_ia32_am_offs(node)) {
+ if (am_offs) {
am_flav |= ia32_O;
add_ia32_am_offs(new_op, am_offs);
}