cls = & ia32_reg_classes[c];
for(r = 0; r < cls->n_regs; ++r) {
const arch_register_t *temp_reg = arch_register_for_index(cls, r);
cls = & ia32_reg_classes[c];
for(r = 0; r < cls->n_regs; ++r) {
const arch_register_t *temp_reg = arch_register_for_index(cls, r);
memset(constraint, 0, sizeof(constraint[0]));
constraint->same_as = -1;
memset(constraint, 0, sizeof(constraint[0]));
constraint->same_as = -1;
/* a memory constraint: no need to do anything in backend about it
* (the dependencies are already respected by the memory edge of
* the node) */
/* a memory constraint: no need to do anything in backend about it
* (the dependencies are already respected by the memory edge of
* the node) */
panic("can only specify same constraint on input");
sscanf(c, "%d%n", &same_as, &p);
panic("can only specify same constraint on input");
sscanf(c, "%d%n", &same_as, &p);
res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
} else {
res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
} else {
val = get_tarval_long(offset);
} else {
ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
val = get_tarval_long(offset);
} else {
ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
/* we need full 32bits for symconsts */
return NULL;
}
/* unfortunately the assembler/linker doesn't support -symconst */
/* we need full 32bits for symconsts */
return NULL;
}
/* unfortunately the assembler/linker doesn't support -symconst */