fixed number of register classes (for now, the use_fpu magic did not work)
fixed creation of ARM constants
[r14484]
arm_code_gen_t *cg = self;
arm_register_transformers();
arm_code_gen_t *cg = self;
arm_register_transformers();
- irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
+ irg_walk_blkwise_graph(cg->irg, NULL, arm_move_consts, cg);
+ irg_walk_blkwise_graph(cg->irg, NULL, arm_transform_node, cg);
static int arm_get_n_reg_class(const void *self) {
const arm_isa_t *isa = self;
static int arm_get_n_reg_class(const void *self) {
const arm_isa_t *isa = self;
+ /* ARGH! is called BEFORE transform */
+ return 2;
return isa->cg->have_fp ? 2 : 1;
}
return isa->cg->have_fp ? 2 : 1;
}
* Returns the necessary byte alignment for storing a register of given class.
*/
static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
* Returns the necessary byte alignment for storing a register of given class.
*/
static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
- ir_mode *mode = arch_register_class_mode(cls);
- return get_mode_size_bytes(mode);
+ /* ARM is a 32 bit CPU, no need for other alignment */
+ return 4;
}
static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
}
static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {