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fix bug introduced in refactoring: displacement only modam used wrong modrm byte
author
Matthias Braun
<matze@braunis.de>
Mon, 21 Sep 2009 14:37:17 +0000
(14:37 +0000)
committer
Matthias Braun
<matze@braunis.de>
Mon, 21 Sep 2009 14:37:17 +0000
(14:37 +0000)
[r26568]
ir/be/ia32/ia32_emitter.c
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diff --git
a/ir/be/ia32/ia32_emitter.c
b/ir/be/ia32/ia32_emitter.c
index
c1aa742
..
9f7a20a
100644
(file)
--- a/
ir/be/ia32/ia32_emitter.c
+++ b/
ir/be/ia32/ia32_emitter.c
@@
-2250,14
+2250,6
@@
static void build_reg_map(void)
reg_gp_map[REG_EDI] = 0x7;
}
reg_gp_map[REG_EDI] = 0x7;
}
-/** The mod encoding of the ModR/M */
-enum Mod {
- MOD_IND = 0x00, /**< [reg1] */
- MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
- MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
- MOD_REG = 0xC0 /**< reg1 */
-};
-
#define GET_MODE(code) ((code) & 0xC0)
/** Sign extension bit values for binops */
#define GET_MODE(code) ((code) & 0xC0)
/** Sign extension bit values for binops */
@@
-2266,6
+2258,14
@@
enum SignExt {
SIGNEXT_IMM = 2, /**< sign extended immediate */
};
SIGNEXT_IMM = 2, /**< sign extended immediate */
};
+/** The mod encoding of the ModR/M */
+enum Mod {
+ MOD_IND = 0x00, /**< [reg1] */
+ MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
+ MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
+ MOD_REG = 0xC0 /**< reg1 */
+};
+
/** create R/M encoding for ModR/M */
#define ENC_RM(x) (x)
/** create REG encoding for ModR/M */
/** create R/M encoding for ModR/M */
#define ENC_RM(x) (x)
/** create REG encoding for ModR/M */
@@
-2481,8
+2481,8
@@
static void bemit_mod_am(unsigned reg, const ir_node *node)
sib |= ENC_INDEX(reg_gp_map[reg_index->index]);
if (has_base) {
sib |= ENC_INDEX(reg_gp_map[reg_index->index]);
if (has_base) {
- const arch_register_t *reg = arch_get_irn_register(base);
- sib |= ENC_BASE(reg_gp_map[reg->index]);
+ const arch_register_t *
base_
reg = arch_get_irn_register(base);
+ sib |= ENC_BASE(reg_gp_map[
base_
reg->index]);
} else {
/* use the EBP encoding if NO base register */
sib |= 0x05;
} else {
/* use the EBP encoding if NO base register */
sib |= 0x05;
@@
-2499,8
+2499,8
@@
static void bemit_mod_am(unsigned reg, const ir_node *node)
/* R/M set to ESP means SIB in 32bit mode */
modrm |= ENC_RM(0x04);
} else if (has_base) {
/* R/M set to ESP means SIB in 32bit mode */
modrm |= ENC_RM(0x04);
} else if (has_base) {
- const arch_register_t *reg = arch_get_irn_register(base);
- if (reg->index == REG_ESP) {
+ const arch_register_t *
base_
reg = arch_get_irn_register(base);
+ if (
base_
reg->index == REG_ESP) {
/* for the above reason we are forced to emit a sib when base is
* ESP. Only the base is used, index must be ESP too, which means no
* index. */
/* for the above reason we are forced to emit a sib when base is
* ESP. Only the base is used, index must be ESP too, which means no
* index. */
@@
-2509,19
+2509,17
@@
static void bemit_mod_am(unsigned reg, const ir_node *node)
/* we are forced to emit a 8bit offset as EBP base without
offset is a special case for SIB without base register */
/* we are forced to emit a 8bit offset as EBP base without
offset is a special case for SIB without base register */
- } else if (reg->index == REG_EBP && emitoffs == 0) {
+ } else if (
base_
reg->index == REG_EBP && emitoffs == 0) {
assert(GET_MODE(modrm) == MOD_IND);
emitoffs = 8;
modrm |= MOD_IND_BYTE_OFS;
}
assert(GET_MODE(modrm) == MOD_IND);
emitoffs = 8;
modrm |= MOD_IND_BYTE_OFS;
}
- modrm |= ENC_RM(reg_gp_map[reg->index]);
+
+ modrm |= ENC_RM(reg_gp_map[base_reg->index]);
} else {
/* only displacement: Use EBP + disp encoding in 32bit mode */
} else {
/* only displacement: Use EBP + disp encoding in 32bit mode */
- if (emitoffs == 0) {
- emitoffs = 8;
- modrm = MOD_IND_BYTE_OFS;
- }
- modrm |= ENC_RM(0x05);
+ emitoffs = 32;
+ modrm = ENC_RM(0x05);
}
modrm |= ENC_REG(reg);
}
modrm |= ENC_REG(reg);