-4. idivl %S2\t\t\t/* signed Mod(%S1, %S2) -> %D1, (%A2, %A3, %4) */
- }
- else {
-4. divl %S2\t\t\t/* unsigned Mod(%S1, %S2) -> %D1, (%A2, %A3, %A4) */
- }
-',
- "args" => [
- { "type" => "ir_node *", "name" => "dividend" },
- { "type" => "ir_node *", "name" => "divisor" },
- { "type" => "ir_node *", "name" => "mem" },
- { "type" => "divmod_flavour_t", "name" => "dm_flav" }, # flavours (flavour_Div, flavour_Mod, flavour_DivMod)
- { "type" => "ir_mode *", "name" => "mode" },
- ],
- "rd_constructor" =>
-" ir_node *res;
- ir_node *in[4];
- asmop_attr *attr;
-
- if (!op_ia32_DivMod) assert(0);
-
- in[1] = divisor;
- in[3] = mem;
-
- if (mode_is_signed(mode)) {
- ir_node *cltd;
- /* in signed mode , we need to sign extend the dividend */
- cltd = new_rd_ia32_Cltd(db, current_ir_graph, block, divisor, mode_T);
- in[0] = new_rd_Proj(db, current_ir_graph, block, cltd, mode_Is, pn_EAX);
- in[2] = new_rd_Proj(db, current_ir_graph, block, cltd, mode_Is, pn_EDX);