X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=win32%2Fvc2010%2Ffirm.vcxproj;h=cf2489f1772e2ad715fcd56a434d07865fab3b05;hb=ac1d48fe48c45e62769a1a4824fe5099e7a22aa6;hp=7ed43fec0c5982730fb0ca275d60867ac563504e;hpb=74d5a9023b48f346eead323a74e28297659e34b7;p=libfirm
diff --git a/win32/vc2010/firm.vcxproj b/win32/vc2010/firm.vcxproj
index 7ed43fec0..cf2489f17 100644
--- a/win32/vc2010/firm.vcxproj
+++ b/win32/vc2010/firm.vcxproj
@@ -1,999 +1,747 @@
-
-
-
-
- DebugJTEST
- Win32
-
-
- Debug
- Win32
-
-
- Release
- Win32
-
-
-
- {7375BFCA-376F-4CB1-BBE6-7C88374BDBD9}
- firm
-
-
-
- DynamicLibrary
- false
- MultiByte
-
-
- DynamicLibrary
- false
- MultiByte
-
-
- DynamicLibrary
- false
- MultiByte
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- <_ProjectFileVersion>10.0.30319.1
- $(Configuration)\
- $(Configuration)\
- bui..\..\win32\$(Configuration)\
- bui..\..\win32\$(Configuration)\
- $(Configuration)\
- $(Configuration)\
-
-
-
- /WL %(AdditionalOptions)
- MaxSpeed
- OnlyExplicitInline
- $(FirmRoot)/ir;$(FirmRoot)/ir/obstack;$(FirmRoot)/win32;$(FirmRoot)/ir/adt;$(FirmRoot)/ir/ana;$(FirmRoot)/ir/common;$(FirmRoot)/ir/debug;$(FirmRoot)/ir/ident;$(FirmRoot)/ir/ir;$(FirmRoot)/ir/opt;$(FirmRoot)/ir/stat;$(FirmRoot)/ir/tr;$(FirmRoot)/ir/tv;$(FirmRoot)/ir/arch;$(FirmRoot)/ir/lower;$(FirmRoot)/ir/be;$(FirmRoot)/ir/libcore;$(FirmRoot)/include/libfirm;$(FirmRoot)/include/libfirm/adt;%(AdditionalIncludeDirectories)
- NDEBUG;WIN32;_LIB;FIRM_BUILD;FIRM_DLL;_CRT_SECURE_NO_DEPRECATE;inline=_inline;%(PreprocessorDefinitions)
- true
- MultiThreaded
- true
- .\Release/firm.pch
- $(IntDir)
- $(IntDir)
- $(IntDir)
- Level3
- true
- ProgramDatabase
- Default
-
-
- NDEBUG;%(PreprocessorDefinitions)
- 0x0407
-
-
- ..\..\ipd\lib\firm.lib
- true
-
-
- true
- .\Release/firm.bsc
-
-
- winmm.lib;%(AdditionalDependencies)
-
-
-
-
- /WL %(AdditionalOptions)
- Disabled
- $(FirmRoot)/ir;$(FirmRoot)/ir/obstack;$(FirmRoot)/win32;$(FirmRoot)/ir/adt;$(FirmRoot)/ir/ana;$(FirmRoot)/ir/common;$(FirmRoot)/ir/debug;$(FirmRoot)/ir/ident;$(FirmRoot)/ir/ir;$(FirmRoot)/ir/opt;$(FirmRoot)/ir/stat;$(FirmRoot)/ir/tr;$(FirmRoot)/ir/tv;$(FirmRoot)/ir/arch;$(FirmRoot)/ir/lower;$(FirmRoot)/ir/be;$(FirmRoot)/ir/libcore;$(FirmRoot)/include/libfirm;$(FirmRoot)/include/libfirm/adt;%(AdditionalIncludeDirectories)
- NO_DEBUG;WIN32;_LIB;FIRM_BUILD;FIRM_DLL;_CRT_SECURE_NO_DEPRECATE;inline=_inline;%(PreprocessorDefinitions)
- true
- EnableFastChecks
- MultiThreadedDebug
- .\Debug/firm.pch
- $(IntDir)
- $(IntDir)
- $(IntDir)
- Level3
- true
- EditAndContinue
- Default
-
-
- _DEBUG;%(PreprocessorDefinitions)
- 0x0407
-
-
- ..\..\ipd\lib\firm_g.lib
- true
-
-
- true
- .\Debug/firm.bsc
-
-
- winmm.lib;%(AdditionalDependencies)
-
-
-
-
- /WL %(AdditionalOptions)
- Disabled
- $(FirmRoot);$(FirmRoot)/ir/obstack;$(FirmRoot)/win32;$(FirmRoot)/ir/adt;$(FirmRoot)/ir/ana;$(FirmRoot)/ir/common;$(FirmRoot)/ir/debug;$(FirmRoot)/ir/ident;$(FirmRoot)/ir/ir;$(FirmRoot)/ir/opt;$(FirmRoot)/ir/stat;$(FirmRoot)/ir/tr;$(FirmRoot)/ir/tv;$(FirmRoot)/ir/arch;$(FirmRoot)/ir/lower;$(FirmRoot)/ir/be;$(FirmRoot)/ir/libcore;$(FirmRoot)/include/libfirm;$(FirmRoot)/include/libfirm/adt;%(AdditionalIncludeDirectories)
- _DEBUG;WIN32;_LIB;FIRM_BUILD;FIRM_DLL;_CRT_SECURE_NO_DEPRECATE;inline=_inline;%(PreprocessorDefinitions)
- true
- EnableFastChecks
- MultiThreadedDebug
- .\Debug/firm.pch
- $(IntDir)
- $(IntDir)
- $(IntDir)
- Level3
- true
- EditAndContinue
- Default
-
-
- _DEBUG;%(PreprocessorDefinitions)
- 0x0407
-
-
- ..\..\ipd\lib\firm_g.lib
- true
-
-
- true
- .\Debug/firm.bsc
-
-
- winmm.lib;%(AdditionalDependencies)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ia32
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\ia32\gen_ia32_emitter.c;$(FirmRoot)\ir\be\ia32\gen_ia32_emitter.h;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.c.inl;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.h;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.c;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.h;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.c;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ia32
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\ia32\gen_ia32_emitter.c;$(FirmRoot)\ir\be\ia32\gen_ia32_emitter.h;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.c.inl;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.h;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.c;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.h;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.c;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ia32
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ia32
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\ia32\gen_ia32_emitter.c;$(FirmRoot)\ir\be\ia32\gen_ia32_emitter.h;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.c.inl;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.h;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.c;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.h;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.c;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.h;%(Outputs)
-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\arm
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\arm\gen_arm_emitter.c;$(FirmRoot)\ir\be\arm\gen_arm_emitter.h;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.c.inl;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.h;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.c;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.h;$(FirmRoot)\ir\be\arm\gen_arm_machine.c;$(FirmRoot)\ir\be\arm\gen_arm_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\arm
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\arm\gen_arm_emitter.c;$(FirmRoot)\ir\be\arm\gen_arm_emitter.h;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.c.inl;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.h;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.c;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.h;$(FirmRoot)\ir\be\arm\gen_arm_machine.c;$(FirmRoot)\ir\be\arm\gen_arm_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\arm
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\arm
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\arm\gen_arm_emitter.c;$(FirmRoot)\ir\be\arm\gen_arm_emitter.h;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.c.inl;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.h;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.c;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.h;$(FirmRoot)\ir\be\arm\gen_arm_machine.c;$(FirmRoot)\ir\be\arm\gen_arm_machine.h;%(Outputs)
-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\ppc32\gen_ppc32_emitter.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_emitter.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_new_nodes.c.inl;$(FirmRoot)\ir\be\ppc32\gen_ppc32_new_nodes.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_regalloc_if.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_regalloc_if.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_machine.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\ppc32\gen_ppc32_emitter.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_emitter.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_new_nodes.c.inl;$(FirmRoot)\ir\be\ppc32\gen_ppc32_new_nodes.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_regalloc_if.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_regalloc_if.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_machine.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ppc32
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\ppc32\gen_ppc32_emitter.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_emitter.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_new_nodes.c.inl;$(FirmRoot)\ir\be\ppc32\gen_ppc32_new_nodes.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_regalloc_if.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_regalloc_if.h;$(FirmRoot)\ir\be\ppc32\gen_ppc32_machine.c;$(FirmRoot)\ir\be\ppc32\gen_ppc32_machine.h;%(Outputs)
-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\mips
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\mips\gen_mips_emitter.c;$(FirmRoot)\ir\be\mips\gen_mips_emitter.h;$(FirmRoot)\ir\be\mips\gen_mips_new_nodes.c.inl;$(FirmRoot)\ir\be\mips\gen_mips_new_nodes.h;$(FirmRoot)\ir\be\mips\gen_mips_regalloc_if.c;$(FirmRoot)\ir\be\mips\gen_mips_regalloc_if.h;$(FirmRoot)\ir\be\mips\gen_mips_machine.c;$(FirmRoot)\ir\be\mips\gen_mips_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\mips
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\mips\gen_mips_emitter.c;$(FirmRoot)\ir\be\mips\gen_mips_emitter.h;$(FirmRoot)\ir\be\mips\gen_mips_new_nodes.c.inl;$(FirmRoot)\ir\be\mips\gen_mips_new_nodes.h;$(FirmRoot)\ir\be\mips\gen_mips_regalloc_if.c;$(FirmRoot)\ir\be\mips\gen_mips_regalloc_if.h;$(FirmRoot)\ir\be\mips\gen_mips_machine.c;$(FirmRoot)\ir\be\mips\gen_mips_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\mips
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\mips
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\mips\gen_mips_emitter.c;$(FirmRoot)\ir\be\mips\gen_mips_emitter.h;$(FirmRoot)\ir\be\mips\gen_mips_new_nodes.c.inl;$(FirmRoot)\ir\be\mips\gen_mips_new_nodes.h;$(FirmRoot)\ir\be\mips\gen_mips_regalloc_if.c;$(FirmRoot)\ir\be\mips\gen_mips_regalloc_if.h;$(FirmRoot)\ir\be\mips\gen_mips_machine.c;$(FirmRoot)\ir\be\mips\gen_mips_machine.h;%(Outputs)
-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.c.inl;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.c.inl;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.c.inl;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.h;%(Outputs)
-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\sparc
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c.inl;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\sparc
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c.inl;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\sparc
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\sparc
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c.inl;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;%(Outputs)
-
-
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c.inl;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c.inl;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;%(Outputs)
- Translate Spec: %(FullPath)
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64
- $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64
-
- $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs)
- $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c.inl;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;%(Outputs)
-
-
-
- Generating I/O code: %(FullPath)
- python %(FullPath) ..\scrip..\..\ir_spec.py ..\..\ir\ir
- ..\scrip..\..\ir_spec.py;%(AdditionalInputs)
- ..\..\ir\ir\gen_irio_import.inl;..\..\ir\ir\gen_irio_export.inl;..\..\ir\ir\gen_irio_lex.inl;%(Outputs)
- Generating I/O code: %(FullPath)
- python %(FullPath) ..\scrip..\..\ir_spec.py ..\..\ir\ir
- ..\scrip..\..\ir_spec.py;%(AdditionalInputs)
- ..\..\ir\ir\gen_irio_import.inl;..\..\ir\ir\gen_irio_export.inl;..\..\ir\ir\gen_irio_lex.inl;%(Outputs)
- Generating I/O code: %(FullPath)
- python %(FullPath) ..\scrip..\..\ir_spec.py ..\..\ir\ir
- ..\scrip..\..\ir_spec.py;%(AdditionalInputs)
- ..\..\ir\ir\gen_irio_import.inl;..\..\ir\ir\gen_irio_export.inl;..\..\ir\ir\gen_irio_lex.inl;%(Outputs)
-
-
- Translate IR-Spec: %(FullPath)
- python ..\..\scripts\gen_ir.py %(FullPath) ..\..\ir\ir
- ..\..\scripts\gen_ir.py;%(AdditionalInputs)
- ..\..\ir\ir\gen_ir_cons.c.inl;%(Outputs)
- Translate IR-Spec: %(FullPath)
- python ..\..\scripts\gen_ir.py %(FullPath) ..\..\ir\ir
- ..\..\scripts\gen_ir.py;%(AdditionalInputs)
- $(FirmRoot)\ir\ir\gen_ir_cons.c.inl;$(FirmRoot)\ir\ir\gen_irnode.h;$(FirmRoot)\ir\ir\gen_irnode.c.inl;$(FirmRoot)\ir\ir\gen_irop.c.inl;%(Outputs)
- Translate IR-Spec: %(FullPath)
- python ..\..\scripts\gen_ir.py %(FullPath) ..\..\ir\ir
- ..\..\scripts\gen_ir.py;%(AdditionalInputs)
- ..\..\ir\ir\gen_ir_cons.c.inl;%(Outputs)
-
-
-
-
-
-
+
+
+
+
+ Debug
+ Win32
+
+
+ Release
+ Win32
+
+
+
+ {7375BFCA-376F-4CB1-BBE6-7C88374BDBD9}
+ firm
+
+
+
+ DynamicLibrary
+ false
+ MultiByte
+
+
+ DynamicLibrary
+ false
+ MultiByte
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <_ProjectFileVersion>10.0.30319.1
+ $(Configuration)\
+ $(Configuration)\
+ bui..\..\win32\$(Configuration)\
+ bui..\..\win32\$(Configuration)\
+
+
+
+ /WL %(AdditionalOptions)
+ MaxSpeed
+ OnlyExplicitInline
+ $(FirmRoot)/ir;$(FirmRoot)/ir/obstack;$(FirmRoot)/win32;$(FirmRoot)/ir/adt;$(FirmRoot)/ir/ana;$(FirmRoot)/ir/common;$(FirmRoot)/ir/debug;$(FirmRoot)/ir/ident;$(FirmRoot)/ir/ir;$(FirmRoot)/ir/opt;$(FirmRoot)/ir/stat;$(FirmRoot)/ir/tr;$(FirmRoot)/ir/tv;$(FirmRoot)/ir/arch;$(FirmRoot)/ir/lower;$(FirmRoot)/ir/be;$(FirmRoot)/ir/libcore;$(FirmRoot)/include/libfirm;$(FirmRoot)/include/libfirm/adt;%(AdditionalIncludeDirectories)
+ NDEBUG;WIN32;_LIB;FIRM_BUILD;FIRM_DLL;_CRT_SECURE_NO_DEPRECATE;inline=_inline;%(PreprocessorDefinitions)
+ true
+ MultiThreaded
+ true
+ .\Release/firm.pch
+ $(IntDir)
+ $(IntDir)
+ $(IntDir)
+ Level3
+ true
+ ProgramDatabase
+ CompileAsCpp
+
+
+ NDEBUG;%(PreprocessorDefinitions)
+ 0x0407
+
+
+ ..\..\ipd\lib\firm.lib
+ true
+
+
+ true
+ .\Release/firm.bsc
+
+
+ winmm.lib;%(AdditionalDependencies)
+
+
+
+
+ /WL %(AdditionalOptions)
+ Disabled
+ $(FirmRoot)/ir;$(FirmRoot)/ir/obstack;$(FirmRoot)/win32;$(FirmRoot)/ir/adt;$(FirmRoot)/ir/ana;$(FirmRoot)/ir/common;$(FirmRoot)/ir/debug;$(FirmRoot)/ir/ident;$(FirmRoot)/ir/ir;$(FirmRoot)/ir/opt;$(FirmRoot)/ir/stat;$(FirmRoot)/ir/tr;$(FirmRoot)/ir/tv;$(FirmRoot)/ir/arch;$(FirmRoot)/ir/lower;$(FirmRoot)/ir/be;$(FirmRoot)/ir/libcore;$(FirmRoot)/include/libfirm;$(FirmRoot)/include/libfirm/adt;%(AdditionalIncludeDirectories)
+ NO_DEBUG;WIN32;_LIB;FIRM_BUILD;FIRM_DLL;_CRT_SECURE_NO_DEPRECATE;inline=_inline;%(PreprocessorDefinitions)
+ true
+ EnableFastChecks
+ MultiThreadedDebug
+ .\Debug/firm.pch
+ $(IntDir)
+ $(IntDir)
+ $(IntDir)
+ Level3
+ true
+ EditAndContinue
+ CompileAsCpp
+ true
+
+
+ _DEBUG;%(PreprocessorDefinitions)
+ 0x0407
+
+
+ ..\..\ipd\lib\firm_g.lib
+ true
+
+
+ true
+ .\Debug/firm.bsc
+
+
+ winmm.lib;%(AdditionalDependencies)
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Translate Spec: %(FullPath)
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)
+ $(FirmRoot)\ir\be\ia32\gen_ia32_emitter.c;$(FirmRoot)\ir\be\ia32\gen_ia32_emitter.h;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.c;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.h;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.c;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.h;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.c;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.h;$(Outputs)
+
+
+ Translate Spec: %(FullPath)
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\arm
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\arm
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\arm
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\arm
+
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)
+ $(FirmRoot)\ir\be\arm\gen_arm_emitter.c;$(FirmRoot)\ir\be\arm\gen_arm_emitter.h;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.c;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.h;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.c;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.h;$(FirmRoot)\ir\be\arm\gen_arm_machine.c;$(FirmRoot)\ir\be\arm\gen_arm_machine.h;$(Outputs)
+
+
+ Translate Spec: %(FullPath)
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)
+ $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;$(Outputs)
+
+
+ Translate Spec: %(FullPath)
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)
+ $(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;$(Outputs)
+
+
+ Translate Spec: %(FullPath)
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+
+ $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)
+ $(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.h;$(Outputs)
+
+
+ Generating I/O code: %(FullPath)
+ python %(FullPath) $(FirmRoot)\scripts\ir_spec.py $(FirmRoot)\ir\ir
+ $(FirmRoot)\scripts\ir_spec.py;%(AdditionalInputs)
+ $(FirmRoot)\ir\ir\gen_irio_import.inl;$(FirmRoot)\ir\ir\gen_irio_export.inl;$(FirmRoot)\ir\ir\gen_irio_lex.inl;%(Outputs)
+
+
+ Translate IR-Spec: %(FullPath)
+ python %(FullPath) $(FirmRoot) $(FirmRoot)\ir\ir
+ $(FirmRoot)\scripts\gen_ir.py;%(AdditionalInputs)
+ $(FirmRoot)\ir\ir\gen_ir_cons.c.inl;$(FirmRoot)\ir\ir\gen_irnode.h;$(FirmRoot)\ir\ir\gen_irnode.c.inl;$(FirmRoot)\ir\ir\gen_irop.c.inl;%(Outputs)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+