X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=win32%2Fvc2010%2Ffirm.vcxproj;h=cf2489f1772e2ad715fcd56a434d07865fab3b05;hb=6ff57d1b23bad2740da34a362a7169c40fccad1f;hp=edd0339bb9631ae4983edc5de684eebcca432896;hpb=1140301fc5c11fef75f583bc4d94082cfd450fbc;p=libfirm

diff --git a/win32/vc2010/firm.vcxproj b/win32/vc2010/firm.vcxproj
index edd0339bb..cf2489f17 100644
--- a/win32/vc2010/firm.vcxproj
+++ b/win32/vc2010/firm.vcxproj
@@ -1,885 +1,747 @@
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+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\amd64_emitter.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\amd64_new_nodes.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\amd64_transform.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\bearch_amd64.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\amd64_emitter.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\amd64_new_nodes.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\amd64_nodes_attr.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\amd64_transform.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\bearch_amd64_t.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\bearch_sparc.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\sparc_cconv.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\sparc_emitter.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\sparc_new_nodes.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\sparc\sparc_transform.c"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\bearch_sparc_t.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\sparc_cconv.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\sparc_emitter.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\sparc_new_nodes.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\sparc_nodes_attr.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\sparc_transform.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_emitter.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_new_nodes.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_transform.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\bearch_TEMPLATE.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.c"/>
+    <ClCompile Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.c"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_emitter.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_new_nodes.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_nodes_attr.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_transform.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\bearch_TEMPLATE_t.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.h"/>
+    <ClInclude Include="$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.h"/>
+    <CustomBuild Include="$(FirmRoot)\ir\be\ia32\ia32_spec.pl">
+      <Message>Translate Spec: %(FullPath)</Message>
+      <Command>$(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\ia32
+</Command>
+      <AdditionalInputs>$(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\be\ia32\gen_ia32_emitter.c;$(FirmRoot)\ir\be\ia32\gen_ia32_emitter.h;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.c;$(FirmRoot)\ir\be\ia32\gen_ia32_new_nodes.h;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.c;$(FirmRoot)\ir\be\ia32\gen_ia32_regalloc_if.h;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.c;$(FirmRoot)\ir\be\ia32\gen_ia32_machine.h;$(Outputs)</Outputs>
+    </CustomBuild>
+    <CustomBuild Include="$(FirmRoot)\ir\be\arm\arm_spec.pl">
+      <Message>Translate Spec: %(FullPath)</Message>
+      <Command>$(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\arm
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\arm
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\arm
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\arm
+</Command>
+      <AdditionalInputs>$(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\be\arm\gen_arm_emitter.c;$(FirmRoot)\ir\be\arm\gen_arm_emitter.h;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.c;$(FirmRoot)\ir\be\arm\gen_arm_new_nodes.h;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.c;$(FirmRoot)\ir\be\arm\gen_arm_regalloc_if.h;$(FirmRoot)\ir\be\arm\gen_arm_machine.c;$(FirmRoot)\ir\be\arm\gen_arm_machine.h;$(Outputs)</Outputs>
+    </CustomBuild>
+    <CustomBuild Include="$(FirmRoot)\ir\be\amd64\amd64_spec.pl">
+      <Message>Translate Spec: %(FullPath)</Message>
+      <Command>$(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64
+</Command>
+      <AdditionalInputs>$(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;$(Outputs)</Outputs>
+    </CustomBuild>
+    <CustomBuild Include="$(FirmRoot)\ir\be\sparc\sparc_spec.pl">
+      <Message>Translate Spec: %(FullPath)</Message>
+      <Command>$(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\sparc
+</Command>
+      <AdditionalInputs>$(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;$(Outputs)</Outputs>
+    </CustomBuild>
+    <CustomBuild Include="$(FirmRoot)\ir\be\TEMPLATE\TEMPLATE_spec.pl">
+      <Message>Translate Spec: %(FullPath)</Message>
+      <Command>$(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+$(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\TEMPLATE
+</Command>
+      <AdditionalInputs>$(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;$(AdditonalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_emitter.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_new_nodes.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_regalloc_if.h;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.c;$(FirmRoot)\ir\be\TEMPLATE\gen_TEMPLATE_machine.h;$(Outputs)</Outputs>
+    </CustomBuild>
+    <CustomBuild Include="$(FirmRoot)\scripts\gen_ir_io.py">
+      <Message>Generating I/O code: %(FullPath)</Message>
+      <Command>python %(FullPath) $(FirmRoot)\scripts\ir_spec.py $(FirmRoot)\ir\ir</Command>
+      <AdditionalInputs>$(FirmRoot)\scripts\ir_spec.py;%(AdditionalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\ir\gen_irio_import.inl;$(FirmRoot)\ir\ir\gen_irio_export.inl;$(FirmRoot)\ir\ir\gen_irio_lex.inl;%(Outputs)</Outputs>
+    </CustomBuild>
+    <CustomBuild Include="$(FirmRoot)\scripts\gen_ir.py">
+      <Message>Translate IR-Spec: %(FullPath)</Message>
+      <Command>python %(FullPath) $(FirmRoot) $(FirmRoot)\ir\ir</Command>
+      <AdditionalInputs>$(FirmRoot)\scripts\gen_ir.py;%(AdditionalInputs)</AdditionalInputs>
+      <Outputs>$(FirmRoot)\ir\ir\gen_ir_cons.c.inl;$(FirmRoot)\ir\ir\gen_irnode.h;$(FirmRoot)\ir\ir\gen_irnode.c.inl;$(FirmRoot)\ir\ir\gen_irop.c.inl;%(Outputs)</Outputs>
+    </CustomBuild>
+    <None Include="$(FirmRoot)\ir\ir\irflag_t.def"/>
+    <None Include="$(FirmRoot)\ir\libcore\lc_printf_arg_types.def"/>
+    <None Include="$(FirmRoot)\scripts\gen_init.py"/>
+    <None Include="$(FirmRoot)\scripts\ir_spec.py"/>
+    <None Include="$(FirmRoot)\scripts\spec_util.py"/>
+    <None Include="$(FirmRoot)\scripts\statev_sql.py"/>
+    <None Include="$(FirmRoot)\ir\be\scripts\generate_emitter.pl"/>
+    <None Include="$(FirmRoot)\ir\be\scripts\generate_emitter_new.pl"/>
+    <None Include="$(FirmRoot)\ir\be\scripts\generate_machine.pl"/>
+    <None Include="$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl"/>
+    <None Include="$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl"/>
+  </ItemGroup>
+  <ItemGroup>
+    <ResourceCompile Include="..\firmdll.rc"/>
+  </ItemGroup>
+  <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets"/>
+  <ImportGroup Label="ExtensionTargets">
+  </ImportGroup>
+</Project>