X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Flower%2Flower_hl.c;h=70f44f4de25652cbdc13e2bd58f2cf412623d69b;hb=3a47171668b40b487a2a3d3c4e5fa3e3e76301c6;hp=1ea642c31bc05119217e9229625bd169c8e8e32f;hpb=80d22a2b8ed15af53c7134a3025da89ccb1923ca;p=libfirm diff --git a/ir/lower/lower_hl.c b/ir/lower/lower_hl.c index 1ea642c31..70f44f4de 100644 --- a/ir/lower/lower_hl.c +++ b/ir/lower/lower_hl.c @@ -35,11 +35,14 @@ #include "irhooks.h" #include "irgmod.h" #include "irgwalk.h" +#include "irtools.h" +#include "irpass_t.h" /** * Lower a Sel node. Do not touch Sels accessing entities on the frame type. */ -static void lower_sel(ir_node *sel) { +static void lower_sel(ir_node *sel) +{ ir_graph *irg = current_ir_graph; ir_entity *ent; ir_node *newn, *cnst, *index, *ptr, *bl; @@ -77,8 +80,8 @@ static void lower_sel(ir_node *sel) { sym.entity_p = ent; bl = get_nodes_block(sel); - cnst = new_rd_SymConst(dbg, irg, bl, mode, sym, symconst_addr_ent); - newn = new_rd_Add(dbg, irg, bl, ptr, cnst, mode); + cnst = new_rd_SymConst(dbg, irg, mode, sym, symconst_addr_ent); + newn = new_rd_Add(dbg, bl, ptr, cnst, mode); } else { /* not TLS */ @@ -141,12 +144,12 @@ static void lower_sel(ir_node *sel) { assert(irg == current_ir_graph); if (! is_Unknown(lb)) - lb = new_rd_Conv(dbg, irg, bl, copy_const_value(get_irn_dbg_info(sel), lb), mode_Int); + lb = new_rd_Conv(dbg, bl, copy_const_value(get_irn_dbg_info(sel), lb), mode_Int); else lb = NULL; if (! is_Unknown(ub)) - ub = new_rd_Conv(dbg, irg, bl, copy_const_value(get_irn_dbg_info(sel), ub), mode_Int); + ub = new_rd_Conv(dbg, bl, copy_const_value(get_irn_dbg_info(sel), ub), mode_Int); else ub = NULL; @@ -159,35 +162,35 @@ static void lower_sel(ir_node *sel) { assert(ub != NULL && "upper bound has to be set in multi-dim array"); /* Elements in one Dimension */ - elms = new_rd_Sub(dbg, irg, bl, ub, lb, mode_Int); + elms = new_rd_Sub(dbg, bl, ub, lb, mode_Int); } - ind = new_rd_Conv(dbg, irg, bl, get_Sel_index(sel, dim), mode_Int); + ind = new_rd_Conv(dbg, bl, get_Sel_index(sel, dim), mode_Int); /* * Normalize index, id lower bound is set, also assume * lower bound == 0 */ if (lb != NULL) - ind = new_rd_Sub(dbg, irg, bl, ind, lb, mode_Int); + ind = new_rd_Sub(dbg, bl, ind, lb, mode_Int); - n = new_rd_Mul(dbg, irg, bl, ind, last_size, mode_Int); + n = new_rd_Mul(dbg, bl, ind, last_size, mode_Int); /* * see comment above. */ if (i > 0) - last_size = new_rd_Mul(dbg, irg, bl, last_size, elms, mode_Int); + last_size = new_rd_Mul(dbg, bl, last_size, elms, mode_Int); - newn = new_rd_Add(dbg, irg, bl, newn, n, mode); + newn = new_rd_Add(dbg, bl, newn, n, mode); } } else { /* no array type */ ir_mode *idx_mode = get_irn_mode(index); tarval *tv = new_tarval_from_long(get_mode_size_bytes(basemode), idx_mode); - newn = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel), - new_rd_Mul(dbg, irg, bl, index, + newn = new_rd_Add(dbg, bl, get_Sel_ptr(sel), + new_rd_Mul(dbg, bl, index, new_r_Const(irg, tv), idx_mode), mode); @@ -202,22 +205,20 @@ static void lower_sel(ir_node *sel) { /* We need an additional load when accessing methods from a dispatch table. */ tv = new_tarval_from_long(get_entity_offset(ent), mode_Int); cnst = new_rd_Const(dbg, irg, tv); - add = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel), cnst, mode); + add = new_rd_Add(dbg, bl, get_Sel_ptr(sel), cnst, mode); #ifdef DO_CACHEOPT /* cacheopt version */ - newn = new_rd_Load(dbg, irg, bl, get_Sel_mem(sel), sel, ent_mode, 0); + newn = new_rd_Load(dbg, bl, get_Sel_mem(sel), sel, ent_mode, 0); cacheopt_map_addrs_register_node(newn); set_Load_ptr(newn, add); #else /* normal code */ - newn = new_rd_Load(dbg, irg, bl, get_Sel_mem(sel), add, ent_mode, 0); + newn = new_rd_Load(dbg, bl, get_Sel_mem(sel), add, ent_mode, 0); #endif - newn = new_r_Proj(irg, bl, newn, ent_mode, pn_Load_res); + newn = new_r_Proj(newn, ent_mode, pn_Load_res); } else if (get_entity_owner(ent) != get_glob_type()) { int offset; /* replace Sel by add(obj, const(ent.offset)) */ - assert(!(get_entity_allocation(ent) == allocation_static && - (get_entity_n_overwrites(ent) == 0 && get_entity_n_overwrittenby(ent) == 0))); newn = get_Sel_ptr(sel); offset = get_entity_offset(ent); if (offset != 0) { @@ -225,11 +226,11 @@ static void lower_sel(ir_node *sel) { tv = new_tarval_from_long(offset, mode_UInt); cnst = new_r_Const(irg, tv); - newn = new_rd_Add(dbg, irg, bl, newn, cnst, mode); + newn = new_rd_Add(dbg, bl, newn, cnst, mode); } } else { /* global_type */ - newn = new_rd_SymConst_addr_ent(NULL, current_ir_graph, mode, ent, firm_unknown_type); + newn = new_rd_SymConst_addr_ent(NULL, irg, mode, ent, firm_unknown_type); } } /* run the hooks */ @@ -241,7 +242,8 @@ static void lower_sel(ir_node *sel) { /** * Lower a all possible SymConst nodes. */ -static void lower_symconst(ir_node *symc) { +static void lower_symconst(ir_node *symc) +{ ir_node *newn; ir_type *tp; ir_entity *ent; @@ -275,9 +277,6 @@ static void lower_symconst(ir_node *symc) { hook_lower(symc); exchange(symc, newn); break; - case symconst_addr_name: - /* do not rewrite - pass info to back end */ - break; case symconst_addr_ent: /* leave */ break; @@ -315,7 +314,8 @@ static void lower_symconst(ir_node *symc) { * * @param size the size on bits */ -static int is_integral_size(int size) { +static int is_integral_size(int size) +{ /* must be a 2^n */ if (size & (size-1)) return 0; @@ -329,7 +329,8 @@ static int is_integral_size(int size) { * @param proj the Proj(result) node * @param load the Load node */ -static void lower_bitfields_loads(ir_node *proj, ir_node *load) { +static void lower_bitfields_loads(ir_node *proj, ir_node *load) +{ ir_node *sel = get_Load_ptr(load); ir_node *block, *n_proj, *res, *ptr; ir_entity *ent; @@ -373,7 +374,7 @@ static void lower_bitfields_loads(ir_node *proj, ir_node *load) { /* abandon bitfield sel */ ptr = get_Sel_ptr(sel); db = get_irn_dbg_info(sel); - ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr)); + ptr = new_rd_Add(db, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr)); set_Load_ptr(load, ptr); set_Load_mode(load, mode); @@ -382,7 +383,7 @@ static void lower_bitfields_loads(ir_node *proj, ir_node *load) { /* create new proj, switch off CSE or we may get the old one back */ old_cse = get_opt_cse(); set_opt_cse(0); - res = n_proj = new_r_Proj(current_ir_graph, block, load, mode, pn_Load_res); + res = n_proj = new_r_Proj(load, mode, pn_Load_res); set_opt_cse(old_cse); if (mode_is_signed(mode)) { /* signed */ @@ -390,24 +391,20 @@ static void lower_bitfields_loads(ir_node *proj, ir_node *load) { int shift_count_down = bits - bf_bits; if (shift_count_up) { - res = new_r_Shl(current_ir_graph, block, res, - new_Const_long(mode_Iu, shift_count_up), mode); + res = new_r_Shl(block, res, new_Const_long(mode_Iu, shift_count_up), mode); } if (shift_count_down) { - res = new_r_Shrs(current_ir_graph, block, res, - new_Const_long(mode_Iu, shift_count_down), mode); + res = new_r_Shrs(block, res, new_Const_long(mode_Iu, shift_count_down), mode); } } else { /* unsigned */ int shift_count_down = bit_offset; unsigned mask = ((unsigned)-1) >> (bits - bf_bits); if (shift_count_down) { - res = new_r_Shr(current_ir_graph, block, res, - new_Const_long(mode_Iu, shift_count_down), mode); + res = new_r_Shr(block, res, new_Const_long(mode_Iu, shift_count_down), mode); } if (bits != bf_bits) { - res = new_r_And(current_ir_graph, block, res, - new_Const_long(mode, mask), mode); + res = new_r_And(block, res, new_Const_long(mode, mask), mode); } } @@ -419,7 +416,8 @@ static void lower_bitfields_loads(ir_node *proj, ir_node *load) { * * @todo: It adds a load which may produce an exception! */ -static void lower_bitfields_stores(ir_node *store) { +static void lower_bitfields_stores(ir_node *store) +{ ir_node *sel = get_Store_ptr(store); ir_node *ptr, *value; ir_entity *ent; @@ -471,26 +469,23 @@ static void lower_bitfields_stores(ir_node *store) { /* abandon bitfield sel */ ptr = get_Sel_ptr(sel); db = get_irn_dbg_info(sel); - ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr)); + ptr = new_rd_Add(db, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr)); if (neg_mask) { /* there are some bits, normal case */ - irn = new_r_Load(current_ir_graph, block, mem, ptr, mode, 0); - mem = new_r_Proj(current_ir_graph, block, irn, mode_M, pn_Load_M); - irn = new_r_Proj(current_ir_graph, block, irn, mode, pn_Load_res); + irn = new_r_Load(block, mem, ptr, mode, 0); + mem = new_r_Proj(irn, mode_M, pn_Load_M); + irn = new_r_Proj(irn, mode, pn_Load_res); - irn = new_r_And(current_ir_graph, block, irn, - new_Const_long(mode, neg_mask), mode); + irn = new_r_And(block, irn, new_Const_long(mode, neg_mask), mode); if (bit_offset > 0) { - value = new_r_Shl(current_ir_graph, block, value, - new_Const_long(mode_Iu, bit_offset), mode); + value = new_r_Shl(block, value, new_Const_long(mode_Iu, bit_offset), mode); } - value = new_r_And(current_ir_graph, block, value, - new_Const_long(mode, mask), mode); + value = new_r_And(block, value, new_Const_long(mode, mask), mode); - value = new_r_Or(current_ir_graph, block, value, irn, mode); + value = new_r_Or(block, value, irn, mode); } set_Store_mem(store, mem); @@ -501,7 +496,8 @@ static void lower_bitfields_stores(ir_node *store) { /** * Lowers unaligned Loads. */ -static void lower_unaligned_Load(ir_node *load) { +static void lower_unaligned_Load(ir_node *load) +{ (void) load; /* NYI */ } @@ -509,7 +505,8 @@ static void lower_unaligned_Load(ir_node *load) { /** * Lowers unaligned Stores */ -static void lower_unaligned_Store(ir_node *store) { +static void lower_unaligned_Store(ir_node *store) +{ (void) store; /* NYI */ } @@ -517,7 +514,8 @@ static void lower_unaligned_Store(ir_node *store) { /** * lowers IR-nodes, called from walker */ -static void lower_irnode(ir_node *irn, void *env) { +static void lower_irnode(ir_node *irn, void *env) +{ (void) env; switch (get_irn_opcode(irn)) { case iro_Sel: @@ -540,12 +538,13 @@ static void lower_irnode(ir_node *irn, void *env) { default: break; } -} /* lower_irnode */ +} /** * Walker: lowers IR-nodes for bitfield access */ -static void lower_bf_access(ir_node *irn, void *env) { +static void lower_bf_access(ir_node *irn, void *env) +{ (void) env; switch (get_irn_opcode(irn)) { case iro_Proj: @@ -564,15 +563,15 @@ static void lower_bf_access(ir_node *irn, void *env) { default: break; } -} /* lower_bf_access */ +} /* * Replaces SymConsts by a real constant if possible. * Replace Sel nodes by address computation. Also resolves array access. * Handle Bitfields by added And/Or calculations. */ -void lower_highlevel_graph(ir_graph *irg, int lower_bitfields) { - +void lower_highlevel_graph(ir_graph *irg, int lower_bitfields) +{ if (lower_bitfields) { /* First step: lower bitfield access: must be run as long as Sels still * exists. */ @@ -581,21 +580,55 @@ void lower_highlevel_graph(ir_graph *irg, int lower_bitfields) { /* Finally: lower SymConst-Size and Sel nodes, Casts, unaligned Load/Stores. */ irg_walk_graph(irg, NULL, lower_irnode, NULL); -} /* lower_highlevel_graph */ + + set_irg_outs_inconsistent(irg); +} + +struct pass_t { + ir_graph_pass_t pass; + int lower_bitfields; +}; + +/** + * Wrapper for running lower_highlevel_graph() as an ir_graph pass. + */ +static int lower_highlevel_graph_wrapper(ir_graph *irg, void *context) +{ + struct pass_t *pass = context; + + lower_highlevel_graph(irg, pass->lower_bitfields); + return 0; +} /* lower_highlevel_graph_wrapper */ + +ir_graph_pass_t *lower_highlevel_graph_pass(const char *name, int lower_bitfields) +{ + struct pass_t *pass = XMALLOCZ(struct pass_t); + + pass->lower_bitfields = lower_bitfields; + return def_graph_pass_constructor( + &pass->pass, name ? name : "lower_hl", lower_highlevel_graph_wrapper); +} /* lower_highlevel_graph_pass */ /* * does the same as lower_highlevel() for all nodes on the const code irg */ -void lower_const_code(void) { +void lower_const_code(void) +{ walk_const_code(NULL, lower_irnode, NULL); } /* lower_const_code */ +ir_prog_pass_t *lower_const_code_pass(const char *name) +{ + return def_prog_pass(name ? name : "lower_const_code", lower_const_code); +} + /* * Replaces SymConsts by a real constant if possible. * Replace Sel nodes by address computation. Also resolves array access. * Handle Bitfields by added And/Or calculations. */ -void lower_highlevel(int lower_bitfields) { +void lower_highlevel(int lower_bitfields) +{ int i, n; n = get_irp_n_irgs();