X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Flower%2Flower_dw.c;h=6db15f16b5fdb5a64f3cecd0f73e1a3356f87924;hb=f864dbddcf026827e85d49544abbb002841a5405;hp=e7b2f1c495cfbd45e904058e5b4906c8239d1713;hpb=8a7997c0741cf324af31664d26ac9357b967f6cd;p=libfirm diff --git a/ir/lower/lower_dw.c b/ir/lower/lower_dw.c index e7b2f1c49..6db15f16b 100644 --- a/ir/lower/lower_dw.c +++ b/ir/lower/lower_dw.c @@ -57,6 +57,7 @@ #include "pmap.h" #include "pdeq.h" #include "irdump.h" +#include "array_t.h" #include "xmalloc.h" /** A map from mode to a primitive type. */ @@ -277,7 +278,7 @@ static void prepare_links(ir_node *node, void *env) lower_env_t *lenv = env; ir_mode *mode = get_irn_op_mode(node); node_entry_t *link; - int i; + int i, idx; if (mode == lenv->params->high_signed || mode == lenv->params->high_unsigned) { @@ -286,7 +287,17 @@ static void prepare_links(ir_node *node, void *env) memset(link, 0, sizeof(*link)); - lenv->entries[get_irn_idx(node)] = link; + idx = get_irn_idx(node); + if (idx >= lenv->n_entries) { + /* enlarge: this happens only for Rotl nodes which is RARELY */ + int old = lenv->n_entries; + int n_idx = idx + (idx >> 3); + + ARR_RESIZE(node_entry_t *, lenv->entries, n_idx); + memset(&lenv->entries[old], 0, (n_idx - old) * sizeof(lenv->entries[0])); + lenv->n_entries = n_idx; + } + lenv->entries[idx] = link; lenv->flags |= MUST_BE_LOWERED; } else if (is_Conv(node)) { /* Conv nodes have two modes */ @@ -915,7 +926,7 @@ static void lower_Shr(ir_node *node, ir_mode *mode, lower_env_t *env) { tarval *tv = get_Const_tarval(right); if (tarval_is_long(tv) && - get_tarval_long(tv) >= (int) get_mode_size_bits(mode)) { + get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) { ir_node *block = get_nodes_block(node); ir_node *left = get_Shr_left(node); ir_node *c; @@ -950,7 +961,7 @@ static void lower_Shl(ir_node *node, ir_mode *mode, lower_env_t *env) { tarval *tv = get_Const_tarval(right); if (tarval_is_long(tv) && - get_tarval_long(tv) >= (int) get_mode_size_bits(mode)) { + get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) { ir_mode *mode_l; ir_node *block = get_nodes_block(node); ir_node *left = get_Shl_left(node); @@ -987,7 +998,7 @@ static void lower_Shrs(ir_node *node, ir_mode *mode, lower_env_t *env) { tarval *tv = get_Const_tarval(right); if (tarval_is_long(tv) && - get_tarval_long(tv) >= (int) get_mode_size_bits(mode)) { + get_tarval_long(tv) >= (long)get_mode_size_bits(mode)) { ir_node *block = get_nodes_block(node); ir_node *left = get_Shrs_left(node); long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode); @@ -998,8 +1009,11 @@ static void lower_Shrs(ir_node *node, ir_mode *mode, lower_env_t *env) { idx = get_irn_idx(node); if (shf_cnt > 0) { + ir_node *tmp; c = new_r_Const_long(irg, block, mode_Iu, shf_cnt); - env->entries[idx]->low_word = new_r_Shrs(irg, block, left, c, mode); + tmp = new_r_Shrs(irg, block, left, c, mode); + /* low word is expected to have mode_Iu */ + env->entries[idx]->low_word = new_r_Conv(irg, block, tmp, mode_Iu); } else { env->entries[idx]->low_word = left; } /* if */ @@ -1013,32 +1027,86 @@ static void lower_Shrs(ir_node *node, ir_mode *mode, lower_env_t *env) { } /* lower_Shrs */ /** - * Translate a Rot and handle special cases. + * Rebuild Rotl nodes into Or(Shl, Shr) and prepare all nodes. */ -static void lower_Rot(ir_node *node, ir_mode *mode, lower_env_t *env) { - ir_node *right = get_Rot_right(node); +static void prepare_links_and_handle_rotl(ir_node *node, void *env) { + lower_env_t *lenv = env; + + if (is_Rotl(node)) { + ir_mode *mode = get_irn_op_mode(node); + if (mode == lenv->params->high_signed || + mode == lenv->params->high_unsigned) { + ir_node *right = get_Rotl_right(node); + ir_node *left, *shl, *shr, *or, *block, *sub, *c; + ir_mode *omode, *rmode; + ir_graph *irg; + dbg_info *dbg; + optimization_state_t state; + + if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) { + tarval *tv = get_Const_tarval(right); + + if (tarval_is_long(tv) && + get_tarval_long(tv) == (long)get_mode_size_bits(mode)) { + /* will be optimized in lower_Rotl() */ + return; + } + } + + /* replace the Rotl(x,y) by an Or(Shl(x,y), Shr(x,64-y)) and lower those */ + dbg = get_irn_dbg_info(node); + omode = get_irn_mode(node); + left = get_Rotl_left(node); + irg = current_ir_graph; + block = get_nodes_block(node); + shl = new_rd_Shl(dbg, irg, block, left, right, omode); + rmode = get_irn_mode(right); + c = new_Const_long(rmode, get_mode_size_bits(omode)); + sub = new_rd_Sub(dbg, irg, block, c, right, rmode); + shr = new_rd_Shr(dbg, irg, block, left, sub, omode); + + /* optimization must be switched off here, or we will get the Rotl back */ + save_optimization_state(&state); + set_opt_algebraic_simplification(0); + or = new_rd_Or(dbg, irg, block, shl, shr, omode); + restore_optimization_state(&state); + + exchange(node, or); + + /* do lowering on the new nodes */ + prepare_links(shl, env); + prepare_links(c, env); + prepare_links(sub, env); + prepare_links(shr, env); + prepare_links(or, env); + } + } else { + prepare_links(node, env); + } +} - if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) { - tarval *tv = get_Const_tarval(right); +/** + * Translate a special case Rotl(x, sizeof(w)). + */ +static void lower_Rotl(ir_node *node, ir_mode *mode, lower_env_t *env) { + ir_node *right = get_Rotl_right(node); + ir_node *left = get_Rotl_left(node); + ir_node *h, *l; + int idx = get_irn_idx(left); + (void) right; + (void) mode; - if (tarval_is_long(tv) && - get_tarval_long(tv) == (int) get_mode_size_bits(mode)) { - ir_node *left = get_Rot_left(node); - ir_node *h, *l; - int idx = get_irn_idx(left); + assert(get_mode_arithmetic(mode) == irma_twos_complement && + is_Const(right) && tarval_is_long(get_Const_tarval(right)) && + get_tarval_long(get_Const_tarval(right)) == (long)get_mode_size_bits(mode)); - l = env->entries[idx]->low_word; - h = env->entries[idx]->high_word; - idx = get_irn_idx(node); + l = env->entries[idx]->low_word; + h = env->entries[idx]->high_word; + idx = get_irn_idx(node); - env->entries[idx]->low_word = h; - env->entries[idx]->high_word = l; - - return; - } /* if */ - } /* if */ - lower_Shiftop(node, mode, env); -} /* lower_Rot */ + env->entries[idx]->low_word = h; + env->entries[idx]->high_word = l; +} /* lower_Rotl */ /** * Translate an Unop. @@ -1134,7 +1202,7 @@ static void lower_Binop_logical(ir_node *node, ir_mode *mode, lower_env_t *env, env->entries[idx]->high_word = constr_rd(dbg, irg, block, lop_h, rop_h, mode); } /* lower_Binop_logical */ -/** create a logical operation tranformation */ +/** create a logical operation transformation */ #define lower_logical(op) \ static void lower_##op(ir_node *node, ir_mode *mode, lower_env_t *env) { \ lower_Binop_logical(node, mode, env, new_rd_##op); \ @@ -1259,7 +1327,7 @@ static void lower_Cond(ir_node *node, ir_mode *mode, lower_env_t *env) { ir_node *cmp = new_rd_Cmp(dbg, irg, block, or, new_Const_long(mode, 0)); ir_node *proj = new_r_Proj(irg, block, cmp, mode_b, pnc); - exchange(sel, proj); + set_Cond_selector(node, proj); return; } } @@ -2096,58 +2164,50 @@ static void lower_Phi(ir_node *phi, ir_mode *mode, lower_env_t *env) { } /* lower_Phi */ /** - * Translate a Psi. + * Translate a Mux. */ -static void lower_Psi(ir_node *psi, ir_mode *mode, lower_env_t *env) { +static void lower_Mux(ir_node *mux, ir_mode *mode, lower_env_t *env) { ir_graph *irg = current_ir_graph; ir_node *block, *val; - ir_node **valsl, **valsh, **conds; + ir_node *true_l, *true_h, *false_l, *false_h, *sel; dbg_info *dbg; - int idx, i, n_conds = get_Psi_n_conds(psi); + int idx; - /* first create a new in array */ - NEW_ARR_A(ir_node *, valsl, n_conds + 1); - NEW_ARR_A(ir_node *, valsh, n_conds + 1); + val = get_Mux_true(mux); + idx = get_irn_idx(val); + if (env->entries[idx]->low_word) { + /* Values already build */ + true_l = env->entries[idx]->low_word; + true_h = env->entries[idx]->high_word; + } else { + /* still not ready */ + pdeq_putr(env->waitq, mux); + return; + } /* if */ - for (i = 0; i < n_conds; ++i) { - val = get_Psi_val(psi, i); - idx = get_irn_idx(val); - if (env->entries[idx]->low_word) { - /* Values already build */ - valsl[i] = env->entries[idx]->low_word; - valsh[i] = env->entries[idx]->high_word; - } else { - /* still not ready */ - pdeq_putr(env->waitq, psi); - return; - } /* if */ - } /* for */ - val = get_Psi_default(psi); + val = get_Mux_false(mux); idx = get_irn_idx(val); if (env->entries[idx]->low_word) { /* Values already build */ - valsl[i] = env->entries[idx]->low_word; - valsh[i] = env->entries[idx]->high_word; + false_l = env->entries[idx]->low_word; + false_h = env->entries[idx]->high_word; } else { /* still not ready */ - pdeq_putr(env->waitq, psi); + pdeq_putr(env->waitq, mux); return; } /* if */ - NEW_ARR_A(ir_node *, conds, n_conds); - for (i = 0; i < n_conds; ++i) { - conds[i] = get_Psi_cond(psi, i); - } /* for */ + sel = get_Mux_sel(mux); - dbg = get_irn_dbg_info(psi); - block = get_nodes_block(psi); + dbg = get_irn_dbg_info(mux); + block = get_nodes_block(mux); - idx = get_irn_idx(psi); + idx = get_irn_idx(mux); assert(idx < env->n_entries); - env->entries[idx]->low_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsl, mode); - env->entries[idx]->high_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsh, mode); -} /* lower_Psi */ + env->entries[idx]->low_word = new_rd_Mux(dbg, irg, block, sel, false_l, true_l, mode); + env->entries[idx]->high_word = new_rd_Mux(dbg, irg, block, sel, false_h, true_h, mode); +} /* lower_Mux */ /** * check for opcodes that must always be lowered. @@ -2242,7 +2302,7 @@ static void lower_ops(ir_node *node, void *env) int idx = get_irn_idx(node); ir_mode *mode = get_irn_mode(node); - if (mode == mode_b || is_Psi(node)) { + if (mode == mode_b || is_Mux(node) || is_Conv(node)) { int i; for (i = get_irn_arity(node) - 1; i >= 0; --i) { @@ -2346,7 +2406,7 @@ void lower_dw_ops(const lwrdw_param_t *param) if (! prim_types) prim_types = pmap_create(); if (! intrinsic_fkt) - intrinsic_fkt = new_set(cmp_op_mode, iro_MaxOpcode); + intrinsic_fkt = new_set(cmp_op_mode, iro_Last + 1); if (! conv_types) conv_types = new_set(cmp_conv_tp, 16); if (! lowered_type) @@ -2435,7 +2495,7 @@ void lower_dw_ops(const lwrdw_param_t *param) LOWER(Call); LOWER(Unknown); LOWER(Phi); - LOWER(Psi); + LOWER(Mux); LOWER(Start); LOWER_BIN(Add); @@ -2444,7 +2504,7 @@ void lower_dw_ops(const lwrdw_param_t *param) LOWER(Shl); LOWER(Shr); LOWER(Shrs); - LOWER(Rot); + LOWER(Rotl); LOWER(DivMod); LOWER(Div); LOWER(Mod); @@ -2467,14 +2527,15 @@ void lower_dw_ops(const lwrdw_param_t *param) obstack_init(&lenv.obst); n_idx = get_irg_last_idx(irg); + n_idx = n_idx + (n_idx >> 2); /* add 25% */ lenv.n_entries = n_idx; - lenv.entries = xmalloc(n_idx * sizeof(lenv.entries[0])); + lenv.entries = NEW_ARR_F(node_entry_t *, n_idx); memset(lenv.entries, 0, n_idx * sizeof(lenv.entries[0])); /* first step: link all nodes and allocate data */ lenv.flags = 0; lenv.proj_2_block = pmap_create(); - irg_walk_graph(irg, firm_clear_link, prepare_links, &lenv); + irg_walk_graph(irg, firm_clear_link, prepare_links_and_handle_rotl, &lenv); if (lenv.flags & MUST_BE_LOWERED) { DB((dbg, LEVEL_1, "Lowering graph %+F\n", irg)); @@ -2502,7 +2563,7 @@ void lower_dw_ops(const lwrdw_param_t *param) } /* if */ } /* if */ pmap_destroy(lenv.proj_2_block); - free(lenv.entries); + DEL_ARR_F(lenv.entries); obstack_free(&lenv.obst, NULL); } /* for */ del_pdeq(lenv.waitq);