X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fir%2Firvrfy.c;h=d43c915b930fc337718bf7f1d73eb8d30a47b474;hb=26baaebd4406b34b8b04ef441d4e45e23c10a747;hp=f674c1571d511a719124a7019c46e98adc5f7c02;hpb=5e62beee699b19e66fa0ab631ff10560e04594b4;p=libfirm

diff --git a/ir/ir/irvrfy.c b/ir/ir/irvrfy.c
index f674c1571..d43c915b9 100644
--- a/ir/ir/irvrfy.c
+++ b/ir/ir/irvrfy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
  *
  * This file is part of libFirm.
  *
@@ -277,11 +277,15 @@ static void show_phi_inputs(ir_node *phi, ir_node *block) {
 
 #endif /* #ifndef NDEBUG */
 
-/** If the address is Sel or SymConst, return the entity. */
+/**
+ * If the address is Sel or SymConst, return the entity.
+ *
+ * @param ptr  the node representing the address
+ */
 static ir_entity *get_ptr_entity(ir_node *ptr) {
 	if (get_irn_op(ptr) == op_Sel) {
 		return get_Sel_entity(ptr);
-	} else if ((get_irn_op(ptr) == op_SymConst) && (get_SymConst_kind(ptr) == symconst_addr_ent)) {
+	} else if (is_SymConst_addr_ent(ptr)) {
 		return get_SymConst_entity(ptr);
 	}
 	return NULL;
@@ -300,7 +304,6 @@ static int verify_node_Proj_Start(ir_node *n, ir_node *p) {
 			(proj == pn_Start_X_initial_exec && mode == mode_X) ||
 			(proj == pn_Start_M         && mode == mode_M) ||
 			(proj == pn_Start_P_frame_base && mode_is_reference(mode)) ||
-			(proj == pn_Start_P_globals && mode_is_reference(mode)) ||
 			(proj == pn_Start_P_tls     && mode_is_reference(mode)) ||
 			(proj == pn_Start_T_args    && mode == mode_T) ||
 			(proj == pn_Start_P_value_arg_base && mode_is_reference(mode)) ||
@@ -388,6 +391,7 @@ static int verify_node_Proj_Call(ir_node *n, ir_node *p) {
 		"wrong Proj from Call", 0,
 		show_proj_failure(p);
 	);
+	/* if we have exception flow, we must have a real Memory input */
 	if (proj == pn_Call_X_regular)
 		ASSERT_AND_RET(
 			get_irn_op(get_Call_mem(n)) != op_NoMem,
@@ -545,6 +549,11 @@ static int verify_node_Proj_Cmp(ir_node *n, ir_node *p) {
 		"wrong Proj from Cmp", 0,
 		show_proj_failure(p);
 	);
+	ASSERT_AND_RET_DBG(
+		(mode_is_float(get_irn_mode(get_Cmp_left(n))) || !(proj & pn_Cmp_Uo)),
+		"unordered Proj for non-float Cmp", 0,
+		show_proj_failure(p);
+	);
 	return 1;
 }
 
@@ -855,23 +864,39 @@ static int verify_node_Block(ir_node *n, ir_graph *irg) {
 	ASSERT_AND_RET(is_Block(mb) || is_Bad(mb), "Block node with wrong MacroBlock", 0);
 
 	if (is_Block(mb) && mb != n) {
+		ir_node *pred;
+
 		/* Blocks with more than one predecessor must be header blocks */
 		ASSERT_AND_RET(get_Block_n_cfgpreds(n) == 1, "partBlock with more than one predecessor", 0);
+		if (get_irg_phase_state(irg) != phase_backend) {
+			pred = get_Block_cfgpred(n, 0);
+			if (is_Proj(pred)) {
+				/* the predecessor MUST be a regular Proj */
+				ir_node *frag_op = get_Proj_pred(pred);
+				ASSERT_AND_RET(
+					is_fragile_op(frag_op) && get_Proj_proj(pred) == pn_Generic_X_regular,
+					"partBlock with non-regular predecessor", 0);
+			} else {
+				/* We allow Jmps to be predecessors of partBlocks. This can happen due to optimization
+				   of fragile nodes during construction. It does not violate our assumption of dominance
+				   so let it. */
+				ASSERT_AND_RET(is_Jmp(pred) || is_Bad(pred),
+					"partBlock with non-regular predecessor", 0);
+			}
+		} else {
+			/* relax in backend: Bound nodes are probably lowered into conditional jumps */
+		}
 	}
 
 	for (i = get_Block_n_cfgpreds(n) - 1; i >= 0; --i) {
 		ir_node *pred =  get_Block_cfgpred(n, i);
 		ASSERT_AND_RET(
-			(
-				is_Bad(pred)     ||
-				is_Unknown(pred) ||
-				(get_irn_mode(pred) == mode_X)
-			),
-			"Block node", 0);
+			is_Bad(pred) ||	(get_irn_mode(pred) == mode_X),
+			"Block node must have a mode_X predecessor", 0);
 	}
 
 	if (n == get_irg_end_block(irg) && get_irg_phase_state(irg) != phase_backend)
-		/*  End block may only have Return, Raise or fragile ops as preds. */
+		/* End block may only have Return, Raise or fragile ops as preds. */
 		for (i = get_Block_n_cfgpreds(n) - 1; i >= 0; --i) {
 			ir_node *pred =  skip_Proj(get_Block_cfgpred(n, i));
 			if (is_Proj(pred) || is_Tuple(pred))
@@ -1518,21 +1543,21 @@ static int verify_node_Shift(ir_node *n, ir_graph *irg) {
 #define verify_node_Shrs  verify_node_Shift
 
 /**
- * verify a Rot node
+ * verify a Rotl node
  */
-static int verify_node_Rot(ir_node *n, ir_graph *irg) {
+static int verify_node_Rotl(ir_node *n, ir_graph *irg) {
 	ir_mode *mymode  = get_irn_mode(n);
-	ir_mode *op1mode = get_irn_mode(get_Rot_left(n));
-	ir_mode *op2mode = get_irn_mode(get_Rot_right(n));
+	ir_mode *op1mode = get_irn_mode(get_Rotl_left(n));
+	ir_mode *op2mode = get_irn_mode(get_Rotl_right(n));
 	(void) irg;
 
 	ASSERT_AND_RET_DBG(
-		/* Rot: BB x int x int --> int */
+		/* Rotl: BB x int x int --> int */
 		mode_is_int(op1mode) &&
 		mode_is_int(op2mode) &&
 		mymode == op1mode,
-		"Rot node", 0,
-		show_binop_failure(n, "/* Rot: BB x int x int --> int */");
+		"Rotl node", 0,
+		show_binop_failure(n, "/* Rotl: BB x int x int --> int */");
 	);
 	return 1;
 }
@@ -1729,7 +1754,7 @@ static int verify_node_Alloc(ir_node *n, ir_graph *irg) {
 		!mode_is_signed(op2mode) &&
 		mymode == mode_T,
 		"Alloc node", 0,
-		show_binop_failure(n, "/* Alloc: BB x M x int_u --> M x X x ref */");
+		show_node_failure(n);
 	);
 	return 1;
 }
@@ -2021,7 +2046,10 @@ int irg_verify(ir_graph *irg, unsigned flags) {
 
 	rem = current_ir_graph;
 	current_ir_graph = irg;
-	last_irg_error = NULL;
+
+#ifndef NDEBUG
+    last_irg_error = NULL;
+#endif /* NDEBUG */
 
 	assert(get_irg_pinned(irg) == op_pin_state_pinned && "Verification need pinned graph");
 
@@ -2227,7 +2255,7 @@ void firm_set_default_verifyer(ir_opcode code, ir_op_ops *ops) {
 	CASE(Shl);
 	CASE(Shr);
 	CASE(Shrs);
-	CASE(Rot);
+	CASE(Rotl);
 	CASE(Conv);
 	CASE(Cast);
 	CASE(Phi);