X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fppc32%2Fbearch_ppc32.c;h=6268c71e143583f46b9f8cbb22ad63887b5e2e29;hb=11d99dd205c877b0a72a8ed5d3cb601b4ec6615f;hp=707c0381f5dbf73a3302dcdaf5335e4d7d2093ae;hpb=11b7b651234355a0298e1075d57703c554e0ef4d;p=libfirm diff --git a/ir/be/ppc32/bearch_ppc32.c b/ir/be/ppc32/bearch_ppc32.c index 707c0381f..6268c71e1 100644 --- a/ir/be/ppc32/bearch_ppc32.c +++ b/ir/be/ppc32/bearch_ppc32.c @@ -37,25 +37,26 @@ #include "debug.h" #include "error.h" -#include "../bearch_t.h" /* the general register allocator interface */ -#include "../benode_t.h" +#include "../bearch.h" +#include "../benode.h" #include "../belower.h" -#include "../besched_t.h" +#include "../besched.h" #include "be.h" #include "../beabi.h" #include "../bemachine.h" #include "../bemodule.h" #include "../bespillslots.h" #include "../beblocksched.h" -#include "../beirg_t.h" +#include "../beirg.h" #include "../begnuas.h" +#include "../belistsched.h" #include "pset.h" #include "bearch_ppc32_t.h" -#include "ppc32_new_nodes.h" /* ppc nodes interface */ -#include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */ +#include "ppc32_new_nodes.h" +#include "gen_ppc32_regalloc_if.h" #include "ppc32_transform.h" #include "ppc32_transform_conv.h" #include "ppc32_emitter.h" @@ -79,139 +80,9 @@ static set *cur_reg_set = NULL; * |___/ **************************************************/ -/** - * Return register requirements for a ppc node. - * If the node returns a tuple (mode_T) then the proj's - * will be asked for this information. - */ -static const arch_register_req_t *ppc32_get_irn_reg_req(const ir_node *irn, - int pos) -{ - long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(irn); - FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE); - - if (is_Block(irn) || mode == mode_X || mode == mode_M) { - DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn)); - return arch_no_register_req; - } - - if (mode == mode_T && pos < 0) { - DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn)); - return arch_no_register_req; - } - - DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn)); - - if (is_Proj(irn)) { - /* in case of a proj, we need to get the correct OUT slot */ - /* of the node corresponding to the proj number */ - if (pos == -1) { - node_pos = ppc32_translate_proj_pos(irn); - } else { - node_pos = pos; - } - - irn = skip_Proj_const(irn); - - DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos)); - } - - /* get requirements for our own nodes */ - if (is_ppc32_irn(irn)) { - const arch_register_req_t *req; - if (pos >= 0) { - req = get_ppc32_in_req(irn, pos); - } else { - req = get_ppc32_out_req(irn, node_pos); - } - - DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos)); - return req; - } - - /* unknowns should be transformed by now */ - assert(!is_Unknown(irn)); - - DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn)); - return arch_no_register_req; -} - -static void ppc32_set_irn_reg(ir_node *irn, const arch_register_t *reg) -{ - int pos = 0; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return; - } - - pos = ppc32_translate_proj_pos(irn); - irn = skip_Proj(irn); - } - - if (is_ppc32_irn(irn)) { - const arch_register_t **slots; - - slots = get_ppc32_slots(irn); - slots[pos] = reg; - } - else { - /* here we set the registers for the Phi nodes */ - ppc32_set_firm_reg(irn, reg, cur_reg_set); - } -} - -static const arch_register_t *ppc32_get_irn_reg(const ir_node *irn) -{ - int pos = 0; - const arch_register_t *reg = NULL; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return NULL; - } - - pos = ppc32_translate_proj_pos(irn); - irn = skip_Proj_const(irn); - } - - if (is_ppc32_irn(irn)) { - const arch_register_t **slots; - slots = get_ppc32_slots(irn); - reg = slots[pos]; - } - else { - reg = ppc32_get_firm_reg(irn, cur_reg_set); - } - - return reg; -} - static arch_irn_class_t ppc32_classify(const ir_node *irn) { - irn = skip_Proj_const(irn); - - if (is_cfop(irn)) { - return arch_irn_class_branch; - } - - return 0; -} - -static arch_irn_flags_t ppc32_get_flags(const ir_node *irn) -{ - irn = skip_Proj_const(irn); - - if (is_ppc32_irn(irn)) { - return get_ppc32_flags(irn); - } - else if (is_Unknown(irn)) { - return arch_irn_flags_ignore; - } - + (void) irn; return 0; } @@ -289,8 +160,8 @@ static ir_type *ppc32_abi_get_between_type(void *self) if(!between_type) { ir_entity *ret_addr_ent; - ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P); - ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P); + ir_type *ret_addr_type = new_type_primitive(mode_P); + ir_type *old_bp_type = new_type_primitive(mode_P); between_type = new_type_class(new_id_from_str("ppc32_between_type")); old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type); @@ -358,11 +229,8 @@ static const be_abi_callbacks_t ppc32_abi_callbacks = { /* fill register allocator interface */ static const arch_irn_ops_t ppc32_irn_ops = { - ppc32_get_irn_reg_req, - ppc32_set_irn_reg, - ppc32_get_irn_reg, + get_ppc32_in_req, ppc32_classify, - ppc32_get_flags, ppc32_get_frame_entity, ppc32_set_frame_entity, ppc32_set_stack_bias, @@ -469,19 +337,19 @@ static void ppc32_transform_spill(ir_node *node, void *env) if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) { - store = new_rd_ppc32_Stw(dbg, current_ir_graph, block, - get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph)); + store = new_bd_ppc32_Stw(dbg, block, + get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem()); } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) { - store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block, - get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph)); + store = new_bd_ppc32_Stfd(dbg, block, + get_irn_n(node, 0), get_irn_n(node, 1), new_NoMem()); } else panic("Spill for register class not supported yet!"); set_ppc32_frame_entity(store, be_get_frame_entity(node)); - proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M); + proj = new_rd_Proj(dbg, block, store, mode_M, pn_Store_M); if (sched_is_scheduled(node)) { sched_add_after(sched_prev(node), store); @@ -505,17 +373,17 @@ static void ppc32_transform_spill(ir_node *node, void *env) if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) { - load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1)); + load = new_bd_ppc32_Lwz(dbg, block, get_irn_n(node, 0), get_irn_n(node, 1)); } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) { - load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1)); + load = new_bd_ppc32_Lfd(dbg, block, get_irn_n(node, 0), get_irn_n(node, 1)); } else panic("Reload for register class not supported yet!"); set_ppc32_frame_entity(load, be_get_frame_entity(node)); - proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res); + proj = new_rd_Proj(dbg, block, load, mode, pn_Load_res); if (sched_is_scheduled(node)) { sched_add_after(sched_prev(node), load); @@ -615,6 +483,7 @@ static ppc32_isa_t ppc32_isa_template = { &ppc32_isa_if, /* isa interface */ &ppc32_gp_regs[REG_R1], /* stack pointer */ &ppc32_gp_regs[REG_R31], /* base pointer */ + &ppc32_reg_classes[CLASS_ppc32_gp], /* static link pointer class */ -1, /* stack is decreasing */ 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ @@ -705,14 +574,13 @@ static void ppc32_done(void *self) { -static unsigned ppc32_get_n_reg_class(const void *self) { - (void) self; +static unsigned ppc32_get_n_reg_class(void) +{ return N_CLASSES; } -static const arch_register_class_t *ppc32_get_reg_class(const void *self, - unsigned i) { - (void) self; +static const arch_register_class_t *ppc32_get_reg_class(unsigned i) +{ assert(i < N_CLASSES && "Invalid ppc register class requested."); return &ppc32_reg_classes[i]; } @@ -725,8 +593,8 @@ static const arch_register_class_t *ppc32_get_reg_class(const void *self, * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) { - (void) self; +const arch_register_class_t *ppc32_get_reg_class_for_mode(const ir_mode *mode) +{ if (mode_is_float(mode)) return &ppc32_reg_classes[CLASS_ppc32_fp]; else @@ -852,15 +720,13 @@ static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self /** * Returns the necessary byte alignment for storing a register of given class. */ -static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { +static int ppc32_get_reg_class_alignment(const arch_register_class_t *cls) +{ ir_mode *mode = arch_register_class_mode(cls); - (void) self; - return get_mode_size_bytes(mode); } -static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) { - (void) self; +static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const ir_node *irn) { (void) irn; /* TODO */ panic("Unimplemented ppc32_get_allowed_execution_units()"); @@ -890,30 +756,30 @@ static const backend_params *ppc32_get_libfirm_params(void) { static backend_params p = { 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - 0, /* no immediate floating point mode. */ - NULL, /* no additional opcodes */ NULL, /* will be set later */ NULL, /* but yet no creator function */ NULL, /* context for create_intrinsic_fkt */ NULL, /* no if conversion settings */ - NULL /* no immediate fp mode */ + NULL, /* no float arithmetic mode (TODO) */ + 0, /* no trampoline support: size 0 */ + 0, /* no trampoline support: align 0 */ + NULL, /* no trampoline support: no trampoline builder */ + 4 /* alignment of stack parameter */ }; return &p; } -static asm_constraint_flags_t ppc32_parse_asm_constraint(const void *self, const char **c) +static asm_constraint_flags_t ppc32_parse_asm_constraint(const char **c) { /* no asm support yet */ - (void) self; (void) c; return ASM_CONSTRAINT_FLAG_INVALID; } -static int ppc32_is_valid_clobber(const void *self, const char *clobber) +static int ppc32_is_valid_clobber(const char *clobber) { /* no asm support yet */ - (void) self; (void) clobber; return 0; } @@ -921,6 +787,7 @@ static int ppc32_is_valid_clobber(const void *self, const char *clobber) const arch_isa_if_t ppc32_isa_if = { ppc32_init, ppc32_done, + NULL, /* handle intrinsics */ ppc32_get_n_reg_class, ppc32_get_reg_class, ppc32_get_reg_class_for_mode,