X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fmips%2Fmips_spec.pl;h=e93e2be7e2fcc8904392f6b4e77602af76d8fcf1;hb=f7dfa0917a2f0469129bbf9b4c0884d37810abcd;hp=dbea8bab9b4e54b34859873ebbb036fb2b5caeac;hpb=511aeabe9b78ea09a5feb0283ec0c70b77953684;p=libfirm diff --git a/ir/be/mips/mips_spec.pl b/ir/be/mips/mips_spec.pl index dbea8bab9..e93e2be7e 100644 --- a/ir/be/mips/mips_spec.pl +++ b/ir/be/mips/mips_spec.pl @@ -5,10 +5,7 @@ # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...) $arch = "mips"; - -# this strings mark the beginning and the end of a comment in emit -$comment_string = "#"; -$comment_string_end = ""; +$new_emit_syntax = 1; # The node description is done as a perl hash initializer with the # following structure: @@ -91,47 +88,81 @@ $comment_string_end = ""; # 4 - ignore (do not assign this register) # NOTE: Last entry of each class is the largest Firm-Mode a register can hold\ %reg_classes = ( - "gp" => [ - { name => "zero", type => 4+2 }, # always zero - { name => "at", type => 4 }, # reserved for assembler - { name => "v0", type => 1 }, # first return value - { name => "v1", type => 1 }, # second return value - { name => "a0", type => 1 }, # first argument - { name => "a1", type => 1 }, # second argument - { name => "a2", type => 1 }, # third argument - { name => "a3", type => 1 }, # fourth argument - { name => "t0", type => 1 }, - { name => "t1", type => 1 }, - { name => "t2", type => 1 }, - { name => "t3", type => 1 }, - { name => "t4", type => 1 }, - { name => "t5", type => 1 }, - { name => "t6", type => 1 }, - { name => "t7", type => 1 }, - { name => "s0", type => 2 }, - { name => "s1", type => 2 }, - { name => "s2", type => 2 }, - { name => "s3", type => 2 }, - { name => "s4", type => 2 }, - { name => "s5", type => 2 }, - { name => "s6", type => 2 }, - { name => "s7", type => 2 }, - { name => "t8", type => 1 }, - { name => "t9", type => 1 }, - { name => "k0", type => 4 }, # reserved for OS - { name => "k1", type => 4 }, # reserved for OS - { name => "gp", type => 4 }, # general purpose - { name => "sp", type => 4+2 }, # stack pointer - { name => "fp", type => 4+2 }, # frame pointer - { name => "ra", type => 2+1 }, # return address. This is also caller save, because - # the jla instruction that is used for calls modifies - # the ra register. It is callee save too, because at the last - # command of a function (the ja $ra) it needs to have it's - # old value. - { mode => "mode_P" } - ], + "gp" => [ + { name => "zero", type => 4+2 }, # always zero + { name => "at", type => 4 }, # reserved for assembler + { name => "v0", realname => "2", type => 1 }, # first return value + { name => "v1", realname => "3", type => 1 }, # second return value + { name => "a0", realname => "4", type => 1 }, # first argument + { name => "a1", realname => "5", type => 1 }, # second argument + { name => "a2", realname => "6", type => 1 }, # third argument + { name => "a3", realname => "7", type => 1 }, # fourth argument + { name => "t0", realname => "8", type => 1 }, + { name => "t1", realname => "9", type => 1 }, + { name => "t2", realname => "10", type => 1 }, + { name => "t3", realname => "11", type => 1 }, + { name => "t4", realname => "12", type => 1 }, + { name => "t5", realname => "13", type => 1 }, + { name => "t6", realname => "14", type => 1 }, + { name => "t7", realname => "15", type => 1 }, + { name => "s0", realname => "16", type => 2 }, + { name => "s1", realname => "17", type => 2 }, + { name => "s2", realname => "18", type => 2 }, + { name => "s3", realname => "19", type => 2 }, + { name => "s4", realname => "20", type => 2 }, + { name => "s5", realname => "21", type => 2 }, + { name => "s6", realname => "22", type => 2 }, + { name => "s7", realname => "23", type => 2 }, + { name => "t8", realname => "24", type => 1 }, + { name => "t9", realname => "25", type => 1 }, + { name => "kt0", type => 4 }, # reserved for OS + { name => "kt1", type => 4 }, # reserved for OS + { name => "gp", type => 4 }, # general purpose + { name => "sp", type => 4 }, # stack pointer + { name => "fp", type => 4 }, # frame pointer + { name => "ra", type => 2+1 }, # return address + { name => "gp_NOREG", realname => "!NOREG_INVALID!", type => 4 | 8 | 16 }, #dummy register for immediate nodes + { mode => "mode_Iu" } + ], ); # %reg_classes +%emit_templates = ( + S0 => "${arch}_emit_source_register(env, node, 0);", + S1 => "${arch}_emit_source_register(env, node, 1);", + S2 => "${arch}_emit_source_register(env, node, 2);", + SI1 => "${arch}_emit_source_register_or_immediate(env, node, 1);", + D0 => "${arch}_emit_dest_register(env, node, 0);", + D1 => "${arch}_emit_dest_register(env, node, 1);", + D2 => "${arch}_emit_dest_register(env, node, 2);", + A0 => "${arch}_emit_load_store_address(env, node, 0);", + I => "${arch}_emit_immediate_suffix(env, node, 1);", + C => "${arch}_emit_immediate(env, node);", + JumpTarget => "${arch}_emit_jump_target(env, node);", + JumpTarget1 => "${arch}_emit_jump_target_proj(env, node, 1);", + JumpOrFallthrough => "${arch}_emit_jump_or_fallthrough(env, node, 0);", +); + +$default_attr_type = "mips_attr_t"; +$default_copy_attr = "mips_copy_attr"; + +$mode_gp = "mode_Iu"; + +%init_attr = ( + mips_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + + mips_immediate_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_mips_immediate_attributes(res, imm_type, entity, val);", + + mips_load_store_attr_t => "\tinit_mips_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_mips_load_store_attributes(res, entity, offset);", +); + +%compare_attr = ( + mips_attr_t => "mips_compare_nodes_attr", + mips_immediate_attr_t => "mips_compare_immediate_attr", + mips_load_store_attr_t => "mips_compare_load_store_attr", +); + #--------------------------------------------------# # _ # # (_) # @@ -145,6 +176,16 @@ $comment_string_end = ""; %nodes = ( +Immediate => { + state => "pinned", + op_flags => "c", + irn_flags => "I", + reg_req => { out => [ "gp_NOREG" ] }, + attr => "mips_immediate_type_t imm_type, ir_entity *entity, long val", + attr_type => "mips_immediate_attr_t", + mode => $mode_gp, +}, + #-----------------------------------------------------------------# # _ _ _ # # (_) | | | | # @@ -158,211 +199,156 @@ $comment_string_end = ""; # commutative operations -add => { - op_flags => "C", - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. addu %D1, %S1, %S2' -}, - -addi => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. addiu %D1, %S1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', +addu => { + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. add%I%.u %D0, %S0, %SI1', + mode => $mode_gp, }, and => { - op_flags => "C", - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. and %D1, %S1, %S2', + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. and%I %D0, %S0, %SI1', + mode => $mode_gp, }, -andi => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. andi %D1, %S1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', +div => { + reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] }, + ins => [ "left", "right" ], + outs => [ "lohi", "M" ], + emit => '. div %S0, %S1', + mode => "mode_M", }, -div => { - reg_req => { in => [ "gp", "gp" ], out => [ "none", "none", "none", "none" ] }, - emit => ' - mips_attr_t *attr = get_mips_attr(n); - if (attr->modes.original_mode->sign) { -2. div %S1, %S2 - } else { -2. divu %S1, %S2 - } -', +divu => { + reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] }, + ins => [ "left", "right" ], + outs => [ "lohi", "M" ], + emit => '. divu %S0, %S1', + mode => "mode_M", }, mult => { - op_flags => "C", - reg_req => { in => [ "gp", "gp" ], out => [ "none" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. mult %S1, %S2 - } - else { -2. multu %S1, %S2 - } -', + reg_req => { in => [ "gp", "gp" ], out => [ "none" ] }, + ins => [ "left", "right" ], + emit => '. mult %S0, %S1', + mode => "mode_M" }, -nor => { - op_flags => "C", - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. nor %D1, %S1, %S2' +multu => { + reg_req => { in => [ "gp", "gp" ], out => [ "none" ] }, + ins => [ "left", "right" ], + emit => '. multu %S0, %S1', + mode => "mode_M", }, -not => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. nor %D1, %S1, $zero' +nor => { + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + emit => '. nor%I %D0, %S0, %SI1', + mode => $mode_gp }, or => { - op_flags => "C", - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. or %D1, %S1, %S2' + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. or%I %D0, %S0, %SI1', + mode => $mode_gp }, -ori => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. ori %D1, %S1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', -}, - -sl => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. sal %D1, %S1, %S2 - } - else { -2. sll %D1, %S1, %S2 - } -', -}, - -sli => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. sal %D1, %S1, %C - } - else { -2. sll %D1, %S1, %C - } -', +sll => { + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. sll %D0, %S0, %SI1', + mode => $mode_gp, }, sra => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. sra %D1, %S1, %S2', -}, - -srai => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. sra %D1, %S1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', -}, - -sr => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. sra %D1, %S1, %S2 - } - else { -2. srl %D1, %S1, %S2 - } -', -}, - -sri => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. sra %D1, %S1, %C - } - else { -2. srl %D1, %S1, %C - } -', -}, - -srlv => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. srlv %D1, %S1, %S2', + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. sra %D0, %S0, %SI1', + mode => $mode_gp }, -sllv => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. sllv %D1, %S1, %S2', +srl => { + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. srl %D0, %S0, %SI1', + mode => $mode_gp, }, -sub => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. subu %D1, %S1, %S2', -}, - -subuzero => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. subu %D1, $zero, %S1', +subu => { + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. subu %D0, %S0, %S1', + mode => $mode_gp }, xor => { - reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => '. xor %D1, %S1, %S2' + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "left", "right" ], + emit => '. xor%I %D0, %S0, %SI1', + mode => $mode_gp, }, -xori => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. xori %D1, %S1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', +seb => { + op_flags => "R", + reg_req => { in => [ "gp" ], out => [ "gp" ] }, + ins => [ "val" ], + emit => '.seb %D0, %S0', + mode => $mode_gp, }, -# ____ _ _ -# / ___|___ _ __ ___| |_ __ _ _ __ | |_ ___ -# | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __| -# | |__| (_) | | | \__ \ || (_| | | | | |_\__ \ -# \____\___/|_| |_|___/\__\__,_|_| |_|\__|___/ -# - -# load upper imediate -lui => { - op_flags => "c", - reg_req => { out => [ "gp" ] }, - emit => '. lui %D1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', -}, - -# load lower immediate -lli => { - op_flags => "c", - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. ori %D1, %S1, %C', - cmp_attr => 'return attr_a->tv != attr_b->tv;', +seh => { + op_flags => "R", + reg_req => { in => [ "gp" ], out => [ "gp" ] }, + ins => [ "val" ], + emit => '.seh %D0, %S0', + mode => $mode_gp, }, -la => { - op_flags => "c", - reg_req => { out => [ "gp" ] }, - emit => '. la %D1, %C', - cmp_attr => 'return attr_a->symconst_id != attr_b->symconst_id;', +lui => { + op_flags => "c", + irn_flags => "R", + reg_req => { out => [ "gp" ] }, + emit => '.lui %D0, %C', + attr_type => "mips_immediate_attr_t", + attr => "mips_immediate_type_t imm_type, ir_entity *entity, long val", + mode => $mode_gp, }, mflo => { - reg_req => { in => [ "none" ], out => [ "gp" ] }, - emit => '. mflo %D1' + irn_flags => "R", + reg_req => { in => [ "none" ], out => [ "gp" ] }, + ins => [ "lohi" ], + emit => '. mflo %D0', + mode => $mode_gp }, mfhi => { - reg_req => { in => [ "none" ], out => [ "gp" ] }, - emit => '. mfhi %D1' + irn_flags => "R", + reg_req => { in => [ "none" ], out => [ "gp" ] }, + ins => [ "lohi" ], + emit => '. mfhi %D0', + mode => $mode_gp }, zero => { - reg_req => { out => [ "zero" ] }, - emit => '', + state => "pinned", + op_flags => "c", + irn_flags => "I", + reg_req => { out => [ "zero" ] }, + emit => '', + mode => $mode_gp }, # @@ -375,164 +361,71 @@ zero => { # slt => { + op_flags => "R", reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. slt %D1, %S1, %S2 - } - else { -2. sltu %D1, %S1, %S2 - } -', -}, - -slti => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => ' - if (mode_is_signed(get_irn_mode(n))) { -2. slti %D1, %S1, %C - } - else { -2. sltiu %D1, %S1, %C - } -', - cmp_attr => 'return attr_a->tv != attr_b->tv;', + emit => '. slt%I %D0, %S0, %SI1', + mode => $mode_gp, }, -beq => { - op_flags => "X|Y", - # TxT -> TxX - reg_req => { in => [ "gp", "gp" ], out => [ "in_r0", "none" ] }, - emit => ' - ir_node *jumpblock = mips_get_jump_block(n, 1); - assert(jumpblock != NULL); +sltu => { + op_flags => "R", + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + emit => '. slt%I%.u %D0, %S0, %SI1', + mode => $mode_gp, +}, - (void) cmd_buf; - (void) cmnt_buf; - lc_efprintf(arg_env, F, "\tbeq %1S, %2S, BLOCK_%d\n", n, n, get_irn_node_nr(jumpblock)); -' +beq => { + op_flags => "X|Y", + reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] }, + outs => [ "false", "true" ], + emit => '. beq %S0, %S1, %JumpTarget1 + . %JumpOrFallthrough' }, bne => { - op_flags => "X|Y", - # TxT -> TxX - reg_req => { in => [ "gp", "gp" ], out => [ "in_r0", "none" ] }, - emit => ' - ir_node *jumpblock = mips_get_jump_block(n, 1); - assert(jumpblock != NULL); - - (void) cmd_buf; - (void) cmnt_buf; - lc_efprintf(arg_env, F, "\tbne %1S, %2S, BLOCK_%d\n", n, n, get_irn_node_nr(jumpblock)); -' + op_flags => "X|Y", + reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] }, + outs => [ "false", "true" ], + emit => '. bne %S0, %S1, %JumpTarget1 + . %JumpOrFallthrough' }, bgtz => { - op_flags => "X|Y", - # TxT -> TxX - reg_req => { in => [ "gp" ], out => [ "in_r0", "none" ] }, - emit => ' - ir_node *jumpblock = mips_get_jump_block(n, 1); - assert(jumpblock != NULL); - - (void) cmd_buf; - (void) cmnt_buf; - lc_efprintf(arg_env, F, "\tbgtz %1S, BLOCK_%d\n", n, get_irn_node_nr(jumpblock)); -' + op_flags => "X|Y", + reg_req => { in => [ "gp" ], out => [ "none", "none" ] }, + outs => [ "false", "true" ], + emit => '. bgtz %S0, %JumpTarget1 + . %JumpOrFallthrough' }, blez => { - op_flags => "X|Y", - # TxT -> TxX - reg_req => { in => [ "gp" ], out => [ "in_r0", "none" ] }, - emit => ' - ir_node *jumpblock = mips_get_jump_block(n, 1); - assert(jumpblock != NULL); - - (void) cmd_buf; - (void) cmnt_buf; - lc_efprintf(arg_env, F, "\tblez %1S, BLOCK_%d\n", n, get_irn_node_nr(jumpblock)); -' -}, - -j => { - op_flags => "X", - reg_req => { in => [ "gp" ] }, - emit => '. j %S1', + op_flags => "X|Y", + reg_req => { in => [ "gp" ], out => [ "none", "none" ] }, + outs => [ "false", "true" ], + emit => '. blez %S0, %JumpTarget1 + . %JumpOrFallthrough' }, b => { - op_flags => "X", - # -> X - reg_req => { in => [ ], out => [ "none" ] }, - emit => ' - ir_node *jumpblock = get_irn_link(n); - assert(jumpblock != NULL); - - (void) cmd_buf; - (void) cmnt_buf; - lc_efprintf(arg_env, F, "\tb BLOCK_%d\t\t\t# mips_b\n", get_irn_node_nr(jumpblock)); -' + op_flags => "X", + reg_req => { in => [ ], out => [ "none" ] }, + emit => '. b %JumpTarget', + mode => 'mode_X' }, -fallthrough => { - op_flags => "X", - # -> X - reg_req => { in => [ ], out => [ "none" ] }, - emit => '. # fallthrough' +jr => { + op_flags => "X", + reg_req => { in => [ "gp" ], out => [ "none" ] }, + emit => '. jr %S0', + mode => 'mode_X' }, SwitchJump => { - op_flags => "X", - # -> X,X,... - reg_req => { in => [ "gp" ], out => [ "none" ] }, - emit => '. j %S1' -}, - -# _ _ -# | | ___ __ _ __| | -# | | / _ \ / _` |/ _` | -# | |__| (_) | (_| | (_| | -# |_____\___/ \__,_|\__,_| -# - -load_r => { - reg_req => { in => [ "none", "gp" ], out => [ "none", "none", "gp" ] }, - emit => ' - mips_attr_t* attr = get_mips_attr(n); - ir_mode *mode; - - mode = attr->modes.load_store_mode; - - switch (get_mode_size_bits(mode)) { - case 8: - if (mode_is_signed(mode)) { -3. lb %D3, %C(%S2) - } - else { -3. lbu %D3, %C(%S2) - } - break; - case 16: - if (mode_is_signed(mode)) { -3. lh %D3, %C(%S2) - } - else { -3. lhu %D3, %C(%S2) - } - break; - case 32: -2. lw %D3, %C(%S2) - break; - default: - assert(! "Only 8, 16 and 32 bit loads supported"); - break; - } -', - cmp_attr => 'return attr_a->tv != attr_b->tv || attr_a->stack_entity != attr_b->stack_entity;', + op_flags => "X", + reg_req => { in => [ "gp" ], out => [ "none" ] }, + emit => '. jr %S0' }, - # _ _ ______ _ # | | ___ __ _ __| | / / ___|| |_ ___ _ __ ___ # | | / _ \ / _` |/ _` | / /\___ \| __/ _ \| '__/ _ \ @@ -540,74 +433,92 @@ load_r => { # |_____\___/ \__,_|\__,_/_/ |____/ \__\___/|_| \___| # -store_r => { - reg_req => { in => [ "none", "gp", "gp" ], out => [ "none", "none" ] }, - emit => ' - mips_attr_t* attr = get_mips_attr(n); - ir_mode* mode; - - mode = attr->modes.load_store_mode; - - switch (get_mode_size_bits(mode)) { - case 8: - if (mode_is_signed(mode)) -2. sb %S3, %C(%S2) - break; - case 16: - if (mode_is_signed(mode)) -2. sh %S3, %C(%S2) - break; - case 32: -2. sw %S3, %C(%S2) - break; - default: - assert(! "Only 8, 16 and 32 bit stores supported"); - break; - } -', - cmp_attr => 'return attr_a->tv != attr_b->tv;', -}, - -store_i => { - reg_req => { in => [ "none", "none", "gp" ], out => [ "none", "none" ] }, - emit => ' - mips_attr_t* attr = get_mips_attr(n); - ir_mode *mode; - - mode = attr->modes.load_store_mode; - - switch (get_mode_size_bits(mode)) { - case 8: -2. sb %S3, %C - break; - case 16: -2. sh %S3, %C - break; - case 32: -2. sw %S3, %C - break; - default: - assert(! "Only 8, 16 and 32 bit stores supported"); - break; - } -', - cmp_attr => ' - return attr_a->stack_entity != attr_b->stack_entity; -', -}, - -move => { - reg_req => { in => [ "gp" ], out => [ "gp" ] }, - emit => '. or %D1, $zero, %S1' -}, - -# -# Conversion -# - -reinterpret_conv => { - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, - emit => '. # reinterpret %S1 -> %D1', +lw => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] }, + ins => [ "ptr", "mem" ], + outs => [ "res", "M" ], + emit => '. lw %D0, %A0', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +lh => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] }, + ins => [ "ptr", "mem" ], + outs => [ "res", "M" ], + emit => '. lh %D0, %A0', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +lhu => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] }, + ins => [ "ptr", "mem" ], + outs => [ "res", "M" ], + emit => '. lhu %D0, %A0', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +lb => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] }, + ins => [ "ptr", "mem" ], + outs => [ "res", "M" ], + emit => '. lb %D0, %A0', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +lbu => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] }, + ins => [ "ptr", "mem" ], + outs => [ "res", "M" ], + emit => '. lbu %D0, %A0', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +sw => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "ptr", "val", "mem" ], + emit => '. sw %S1, %A0', + mode => 'mode_M', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +sh => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "ptr", "val", "mem" ], + emit => '. sh %S1, %A0', + mode => 'mode_M', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", +}, + +sb => { + op_flags => "L|F", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "ptr", "val", "mem" ], + emit => '. sb %S1, %A0', + mode => 'mode_M', + attr_type => "mips_load_store_attr_t", + attr => "ir_entity *entity, long offset", }, # @@ -615,9 +526,9 @@ reinterpret_conv => { # nop => { - op_flags => "K", - reg_req => { in => [], out => [ "none" ] }, - emit => '. nop # nop', + op_flags => "K", + reg_req => { in => [], out => [ "none" ] }, + emit => '. nop', }, ); # end of %nodes