X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fmips%2Fbearch_mips.c;h=62b946b8f649b179ef673b33c1453ce8e44c1f1c;hb=39cb52264857d7c21c7141ba82bb55adaa78064d;hp=f6b7734053758a0c4acf4a65234f872bc3ff57a2;hpb=fcba9f9a3500dcd4763ac05b7382157e99b53fd5;p=libfirm diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c index f6b773405..62b946b8f 100644 --- a/ir/be/mips/bearch_mips.c +++ b/ir/be/mips/bearch_mips.c @@ -42,12 +42,12 @@ #include "bitset.h" #include "debug.h" -#include "../bearch_t.h" -#include "../benode_t.h" +#include "../bearch.h" +#include "../benode.h" #include "../belower.h" -#include "../besched_t.h" +#include "../besched.h" #include "../beblocksched.h" -#include "../beirg_t.h" +#include "../beirg.h" #include "be.h" #include "../beabi.h" #include "../bemachine.h" @@ -82,89 +82,9 @@ static set *cur_reg_set = NULL; * |___/ **************************************************/ -/** - * Return register requirements for a mips node. - * If the node returns a tuple (mode_T) then the proj's - * will be asked for this information. - */ -static const -arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos) -{ - long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(node); - - if (is_Block(node) || mode == mode_X || mode == mode_M) { - return arch_no_register_req; - } - - if (mode == mode_T && pos < 0) { - return arch_no_register_req; - } - - if (is_Proj(node)) { - /* in case of a proj, we need to get the correct OUT slot */ - /* of the node corresponding to the proj number */ - if (pos == -1) { - node_pos = mips_translate_proj_pos(node); - } - else { - node_pos = pos; - } - - node = skip_Proj_const(node); - } - - /* get requirements for our own nodes */ - if (is_mips_irn(node)) { - const arch_register_req_t *req; - if (pos >= 0) { - req = get_mips_in_req(node, pos); - } else { - req = get_mips_out_req(node, node_pos); - } - - return req; - } - - /* unknown should be translated by now */ - assert(!is_Unknown(node)); - - return arch_no_register_req; -} - -static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg) -{ - int pos = 0; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return; - } - - pos = mips_translate_proj_pos(irn); - irn = skip_Proj(irn); - } - - if (is_mips_irn(irn)) { - const arch_register_t **slots; - - slots = get_mips_slots(irn); - slots[pos] = reg; - } else { - /* here we set the registers for the Phi nodes */ - mips_set_firm_reg(irn, reg, cur_reg_set); - } -} - static arch_irn_class_t mips_classify(const ir_node *irn) { - irn = skip_Proj_const(irn); - - if (is_cfop(irn)) { - return arch_irn_class_branch; - } - + (void) irn; return 0; } @@ -239,7 +159,8 @@ static int mips_get_sp_bias(const ir_node *irn) /* fill register allocator interface */ static const arch_irn_ops_t mips_irn_ops = { - mips_get_irn_reg_req, + get_mips_in_req, + get_mips_out_req, mips_classify, mips_get_frame_entity, mips_set_frame_entity, @@ -391,6 +312,7 @@ static mips_isa_t mips_isa_template = { &mips_isa_if, &mips_gp_regs[REG_SP], &mips_gp_regs[REG_FP], + &mips_reg_classes[CLASS_mips_gp], -1, /* stack direction */ 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ @@ -442,16 +364,13 @@ static void mips_done(void *self) free(isa); } -static unsigned mips_get_n_reg_class(const void *self) +static unsigned mips_get_n_reg_class(void) { - (void) self; return N_CLASSES; } -static const arch_register_class_t *mips_get_reg_class(const void *self, - unsigned i) +static const arch_register_class_t *mips_get_reg_class(unsigned i) { - (void) self; assert(i < N_CLASSES); return &mips_reg_classes[i]; } @@ -464,10 +383,8 @@ static const arch_register_class_t *mips_get_reg_class(const void *self, * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, - const ir_mode *mode) +const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode) { - (void) self; (void) mode; ASSERT_NO_FLOAT(mode); return &mips_reg_classes[CLASS_mips_gp]; @@ -517,7 +434,7 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap // - setup first part of stackframe sp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(initialstackframesize)); - mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); panic("FIXME Use IncSP or set register requirement with ignore"); /* TODO: where to get an edge with a0-a3 @@ -546,7 +463,7 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap /* Note: ideally we would route these mem edges directly towards the * epilogue, but this is currently not supported so we sync all mems * together */ - sync = new_r_Sync(irg, block, 2, mm+4); + sync = new_r_Sync(block, 2, mm+4); *mem = sync; } else { ir_node *reg, *store; @@ -555,7 +472,7 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap // save old framepointer sp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(-initialstackframesize)); - mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); panic("FIXME Use IncSP or set register requirement with ignore"); reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); @@ -567,7 +484,7 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap // setup framepointer fp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(-initialstackframesize)); - mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]); + arch_set_irn_register(fp, &mips_gp_regs[REG_FP]); panic("FIXME Use IncSP or set register requirement with ignore"); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); @@ -580,7 +497,6 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r { mips_abi_env_t *env = self; - ir_graph *irg = env->irg; ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); ir_node *load; @@ -589,7 +505,7 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r // copy fp to sp sp = new_bd_mips_or(NULL, block, fp, mips_create_zero()); - mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); panic("FIXME Use be_Copy or set register requirement with ignore"); // 1. restore fp @@ -597,8 +513,8 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r fp_save_offset - initial_frame_size); panic("FIXME register requirement with ignore"); - fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res); - *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M); + fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res); + *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M); arch_set_irn_register(fp, &mips_gp_regs[REG_FP]); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); @@ -736,18 +652,15 @@ static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) /** * Returns the necessary byte alignment for storing a register of given class. */ -static int mips_get_reg_class_alignment(const void *self, - const arch_register_class_t *cls) +static int mips_get_reg_class_alignment(const arch_register_class_t *cls) { ir_mode *mode = arch_register_class_mode(cls); - (void) self; return get_mode_size_bytes(mode); } static const be_execution_unit_t ***mips_get_allowed_execution_units( - const void *self, const ir_node *irn) + const ir_node *irn) { - (void) self; (void) irn; /* TODO */ panic("Unimplemented mips_get_allowed_execution_units()"); @@ -791,17 +704,14 @@ static const backend_params *mips_get_libfirm_params(void) { return &p; } -static asm_constraint_flags_t mips_parse_asm_constraint(const void *self, - const char **c) +static asm_constraint_flags_t mips_parse_asm_constraint(const char **c) { - (void) self; (void) c; return ASM_CONSTRAINT_FLAG_INVALID; } -static int mips_is_valid_clobber(const void *self, const char *clobber) +static int mips_is_valid_clobber(const char *clobber) { - (void) self; (void) clobber; return 0; }